* Re: [PATCH 1/3] Move FIMD register headers to include/video/
From: Tomasz Figa @ 2012-07-30 14:32 UTC (permalink / raw)
To: Leela Krishna Amudala
Cc: Jingoo Han, linux-arm-kernel, linux-samsung-soc, dri-devel,
linux-fbdev, ben-linux, inki.dae, kgene.kim, joshi,
Marek Szyprowski
In-Reply-To: <CAL1wa8e7Joghf9S=SgbQLJFWcYOrP5uK6qYXsV_N6rX1MVEALg@mail.gmail.com>
Hi,
On Monday 30 of July 2012 at 16:46:03, Leela Krishna Amudala wrote:
> Hello Jingoo Han,
>
> On Mon, Jul 30, 2012 at 2:23 PM, Jingoo Han <jg1.han@samsung.com> wrote:
> > On Monday, July 30, 2012 5:45 PM, Leela Krishna Amudala wrote:
> >> Moved the contents of regs-fb-v4.h and regs-fb.h from arch side
> >> to include/video/samsung_fimd.h
> >>
> >> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> >> ---
> >>
> >> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 159 -------
> >> arch/arm/plat-samsung/include/plat/regs-fb.h | 403 -----------------
> >> include/video/samsung_fimd.h | 533
> >> +++++++++++++++++++++++ 3 files changed, 533 insertions(+), 562
> >> deletions(-)
> >> delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h
> >> create mode 100644 include/video/samsung_fimd.h
> >>
> >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> b/arch/arm/plat-samsung/include/plat/regs- fb-v4.h
> >> deleted file mode 100644
> >> index 4c3647f..0000000
> >> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> +++ /dev/null
> >> @@ -1,159 +0,0 @@
> >> -/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> >> - *
> >> - * Copyright 2008 Openmoko, Inc.
> >> - * Copyright 2008 Simtec Electronics
> >> - * http://armlinux.simtec.co.uk/
> >> - * Ben Dooks <ben@simtec.co.uk>
> >> - *
> >> - * S3C64XX - new-style framebuffer register definitions
> >> - *
> >> - * This is the register set for the new style framebuffer interface
> >> - * found from the S3C2443 onwards and specifically the S3C64XX series
> >> - * S3C6400 and S3C6410.
> >> - *
> >> - * The file contains the cpu specific items which change between
> >> whichever
> >> - * architecture is selected. See <plat/regs-fb.h> for the core
> >> definitions
> >> - * that are the same.
> >> - *
> >> - * This program is free software; you can redistribute it and/or modify
> >> - * it under the terms of the GNU General Public License version 2 as
> >> - * published by the Free Software Foundation.
> >> -*/
> >> -
> >> -/* include the core definitions here, in case we really do need to
> >> - * override them at a later date.
> >> -*/
> >> -
> >> -#include <plat/regs-fb.h>
> >> -
> >> -#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
> >> -#define VIDCON1_FSTATUS_EVEN (1 << 15)
> >> -
> >> -/* Video timing controls */
> >> -#define VIDTCON0 (0x10)
> >> -#define VIDTCON1 (0x14)
> >> -#define VIDTCON2 (0x18)
> >> -
> >> -/* Window position controls */
> >> -
> >> -#define WINCON(_win) (0x20 + ((_win) * 4))
> >> -
> >> -/* OSD1 and OSD4 do not have register D */
> >> -
> >> -#define VIDOSD_BASE (0x40)
> >> -
> >> -#define VIDINTCON0 (0x130)
> >> -
> >> -/* WINCONx */
> >> -
> >> -#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> >> -#define WINCONx_CSCWIDTH_SHIFT (26)
> >> -#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> >> -#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
> >> -
> >> -#define WINCONx_ENLOCAL (1 << 22)
> >> -#define WINCONx_BUFSTATUS (1 << 21)
> >> -#define WINCONx_BUFSEL (1 << 20)
> >> -#define WINCONx_BUFAUTOEN (1 << 19)
> >> -#define WINCONx_YCbCr (1 << 13)
> >> -
> >> -#define WINCON1_LOCALSEL_CAMIF (1 << 23)
> >> -
> >> -#define WINCON2_LOCALSEL_CAMIF (1 << 23)
> >> -#define WINCON2_BLD_PIX (1 << 6)
> >> -
> >> -#define WINCON2_ALPHA_SEL (1 << 1)
> >> -#define WINCON2_BPPMODE_MASK (0xf << 2)
> >> -#define WINCON2_BPPMODE_SHIFT (2)
> >> -#define WINCON2_BPPMODE_1BPP (0x0 << 2)
> >> -#define WINCON2_BPPMODE_2BPP (0x1 << 2)
> >> -#define WINCON2_BPPMODE_4BPP (0x2 << 2)
> >> -#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
> >> -#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
> >> -#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
> >> -#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
> >> -#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
> >> -#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
> >> -#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
> >> -#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
> >> -#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
> >> -#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
> >> -#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
> >> -
> >> -#define WINCON3_BLD_PIX (1 << 6)
> >> -
> >> -#define WINCON3_ALPHA_SEL (1 << 1)
> >> -#define WINCON3_BPPMODE_MASK (0xf << 2)
> >> -#define WINCON3_BPPMODE_SHIFT (2)
> >> -#define WINCON3_BPPMODE_1BPP (0x0 << 2)
> >> -#define WINCON3_BPPMODE_2BPP (0x1 << 2)
> >> -#define WINCON3_BPPMODE_4BPP (0x2 << 2)
> >> -#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
> >> -#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
> >> -#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
> >> -#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
> >> -#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
> >> -#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
> >> -#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
> >> -#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
> >> -#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
> >> -#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
> >> -
> >> -#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
> >> -#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
> >> -#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
> >> -
> >> -#define DITHMODE (0x170)
> >> -#define WINxMAP(_win) (0x180 + ((_win) *
> >> 4)) -
> >> -
> >> -#define DITHMODE_R_POS_MASK (0x3 << 5)
> >> -#define DITHMODE_R_POS_SHIFT (5)
> >> -#define DITHMODE_R_POS_8BIT (0x0 << 5)
> >> -#define DITHMODE_R_POS_6BIT (0x1 << 5)
> >> -#define DITHMODE_R_POS_5BIT (0x2 << 5)
> >> -
> >> -#define DITHMODE_G_POS_MASK (0x3 << 3)
> >> -#define DITHMODE_G_POS_SHIFT (3)
> >> -#define DITHMODE_G_POS_8BIT (0x0 << 3)
> >> -#define DITHMODE_G_POS_6BIT (0x1 << 3)
> >> -#define DITHMODE_G_POS_5BIT (0x2 << 3)
> >> -
> >> -#define DITHMODE_B_POS_MASK (0x3 << 1)
> >> -#define DITHMODE_B_POS_SHIFT (1)
> >> -#define DITHMODE_B_POS_8BIT (0x0 << 1)
> >> -#define DITHMODE_B_POS_6BIT (0x1 << 1)
> >> -#define DITHMODE_B_POS_5BIT (0x2 << 1)
> >> -
> >> -#define DITHMODE_DITH_EN (1 << 0)
> >> -
> >> -#define WPALCON (0x1A0)
> >> -
> >> -/* Palette control */
> >> -/* Note for S5PC100: you can still use those macros on WPALCON (aka
> >> WPALCON_L), - * but make sure that WPALCON_H W2PAL-W4PAL entries are
> >> zeroed out */ -#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
> >> -#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
> >> -#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
> >> -
> >> -
> >> -/* Notes on per-window bpp settings
> >> - *
> >> - * Value Win0 Win1 Win2 Win3 Win 4
> >> - * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
> >> - * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
> >> - * 0010 4(P) 4(P) 4(P) 4(P) -none-
> >> - * 0011 8(P) 8(P) -none- -none- -none-
> >> - * 0100 -none- 8(A232) 8(A232) -none- -none-
> >> - * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
> >> - * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
> >> - * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
> >> - * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
> >> - * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
> >> - * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
> >> - * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
> >> - * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
> >> - * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
> >> - * 1110 -none- -none- -none- -none- -none-
> >> - * 1111 -none- -none- -none- -none- -none-
> >> -*/
> >> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> b/arch/arm/plat-samsung/include/plat/regs-fb.h deleted file mode 100644
> >> index 9a78012..0000000
> >> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> >> +++ /dev/null
> >> @@ -1,403 +0,0 @@
> >> -/* arch/arm/plat-samsung/include/plat/regs-fb.h
> >> - *
> >> - * Copyright 2008 Openmoko, Inc.
> >> - * Copyright 2008 Simtec Electronics
> >> - * http://armlinux.simtec.co.uk/
> >> - * Ben Dooks <ben@simtec.co.uk>
> >> - *
> >> - * S3C Platform - new-style framebuffer register definitions
> >> - *
> >> - * This is the register set for the new style framebuffer interface
> >> - * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
> >> - * S3C64XX series such as the S3C6400 and S3C6410.
> >> - *
> >> - * The file does not contain the cpu specific items which are based on
> >> - * whichever architecture is selected, it only contains the core of the
> >> - * register set. See <mach/regs-fb.h> to get the specifics.
> >> - *
> >> - * Note, we changed to using regs-fb.h as it avoids any clashes with
> >> - * the original regs-lcd.h so out of the way of regs-lcd.h as well as
> >> - * indicating the newer block is much more than just an LCD interface.
> >> - *
> >> - * This program is free software; you can redistribute it and/or modify
> >> - * it under the terms of the GNU General Public License version 2 as
> >> - * published by the Free Software Foundation.
> >> -*/
> >> -
> >> -/* Please do not include this file directly, use <mach/regs-fb.h> to
> >> - * ensure all the localised SoC support is included as necessary.
> >> -*/
> >> -
> >> -/* VIDCON0 */
> >> -
> >> -#define VIDCON0 (0x00)
> >> -#define VIDCON0_INTERLACE (1 << 29)
> >> -#define VIDCON0_VIDOUT_MASK (0x3 << 26)
> >> -#define VIDCON0_VIDOUT_SHIFT (26)
> >> -#define VIDCON0_VIDOUT_RGB (0x0 << 26)
> >> -#define VIDCON0_VIDOUT_TV (0x1 << 26)
> >> -#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> >> -#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> >> -
> >> -#define VIDCON0_L1_DATA_MASK (0x7 << 23)
> >> -#define VIDCON0_L1_DATA_SHIFT (23)
> >> -#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
> >> -#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
> >> -#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
> >> -#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
> >> -#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
> >> -#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
> >> -
> >> -#define VIDCON0_L0_DATA_MASK (0x7 << 20)
> >> -#define VIDCON0_L0_DATA_SHIFT (20)
> >> -#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
> >> -#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
> >> -#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
> >> -#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
> >> -#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
> >> -#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
> >> -
> >> -#define VIDCON0_PNRMODE_MASK (0x3 << 17)
> >> -#define VIDCON0_PNRMODE_SHIFT (17)
> >> -#define VIDCON0_PNRMODE_RGB (0x0 << 17)
> >> -#define VIDCON0_PNRMODE_BGR (0x1 << 17)
> >> -#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
> >> -#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
> >> -
> >> -#define VIDCON0_CLKVALUP (1 << 16)
> >> -#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
> >> -#define VIDCON0_CLKVAL_F_SHIFT (6)
> >> -#define VIDCON0_CLKVAL_F_LIMIT (0xff)
> >> -#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
> >> -#define VIDCON0_VLCKFREE (1 << 5)
> >> -#define VIDCON0_CLKDIR (1 << 4)
> >> -
> >> -#define VIDCON0_CLKSEL_MASK (0x3 << 2)
> >> -#define VIDCON0_CLKSEL_SHIFT (2)
> >> -#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
> >> -#define VIDCON0_CLKSEL_LCD (0x1 << 2)
> >> -#define VIDCON0_CLKSEL_27M (0x3 << 2)
> >> -
> >> -#define VIDCON0_ENVID (1 << 1)
> >> -#define VIDCON0_ENVID_F (1 << 0)
> >> -
> >> -#define VIDCON1 (0x04)
> >> -#define VIDCON1_LINECNT_MASK (0x7ff << 16)
> >> -#define VIDCON1_LINECNT_SHIFT (16)
> >> -#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) &
> >> 0x7ff) -#define VIDCON1_VSTATUS_MASK (0x3 << 13)
> >> -#define VIDCON1_VSTATUS_SHIFT (13)
> >> -#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
> >> -#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
> >> -#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
> >> -#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
> >> -#define VIDCON1_VCLK_MASK (0x3 << 9)
> >> -#define VIDCON1_VCLK_HOLD (0x0 << 9)
> >> -#define VIDCON1_VCLK_RUN (0x1 << 9)
> >> -
> >> -#define VIDCON1_INV_VCLK (1 << 7)
> >> -#define VIDCON1_INV_HSYNC (1 << 6)
> >> -#define VIDCON1_INV_VSYNC (1 << 5)
> >> -#define VIDCON1_INV_VDEN (1 << 4)
> >> -
> >> -/* VIDCON2 */
> >> -
> >> -#define VIDCON2 (0x08)
> >> -#define VIDCON2_EN601 (1 << 23)
> >> -#define VIDCON2_TVFMTSEL_SW (1 << 14)
> >> -
> >> -#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> >> -#define VIDCON2_TVFMTSEL1_SHIFT (12)
> >> -#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> -#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> -#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >> -
> >> -#define VIDCON2_ORGYCbCr (1 << 8)
> >> -#define VIDCON2_YUVORDCrCb (1 << 7)
> >> -
> >> -/* PRTCON (S3C6410, S5PC100)
> >> - * Might not be present in the S3C6410 documentation,
> >> - * but tests prove it's there almost for sure; shouldn't hurt in any
> >> case.
> >> - */
> >> -#define PRTCON (0x0c)
> >> -#define PRTCON_PROTECT (1 << 11)
> >> -
> >> -/* VIDTCON0 */
> >> -
> >> -#define VIDTCON0_VBPDE_MASK (0xff << 24)
> >> -#define VIDTCON0_VBPDE_SHIFT (24)
> >> -#define VIDTCON0_VBPDE_LIMIT (0xff)
> >> -#define VIDTCON0_VBPDE(_x) ((_x) << 24)
> >> -
> >> -#define VIDTCON0_VBPD_MASK (0xff << 16)
> >> -#define VIDTCON0_VBPD_SHIFT (16)
> >> -#define VIDTCON0_VBPD_LIMIT (0xff)
> >> -#define VIDTCON0_VBPD(_x) ((_x) << 16)
> >> -
> >> -#define VIDTCON0_VFPD_MASK (0xff << 8)
> >> -#define VIDTCON0_VFPD_SHIFT (8)
> >> -#define VIDTCON0_VFPD_LIMIT (0xff)
> >> -#define VIDTCON0_VFPD(_x) ((_x) << 8)
> >> -
> >> -#define VIDTCON0_VSPW_MASK (0xff << 0)
> >> -#define VIDTCON0_VSPW_SHIFT (0)
> >> -#define VIDTCON0_VSPW_LIMIT (0xff)
> >> -#define VIDTCON0_VSPW(_x) ((_x) << 0)
> >> -
> >> -/* VIDTCON1 */
> >> -
> >> -#define VIDTCON1_VFPDE_MASK (0xff << 24)
> >> -#define VIDTCON1_VFPDE_SHIFT (24)
> >> -#define VIDTCON1_VFPDE_LIMIT (0xff)
> >> -#define VIDTCON1_VFPDE(_x) ((_x) << 24)
> >> -
> >> -#define VIDTCON1_HBPD_MASK (0xff << 16)
> >> -#define VIDTCON1_HBPD_SHIFT (16)
> >> -#define VIDTCON1_HBPD_LIMIT (0xff)
> >> -#define VIDTCON1_HBPD(_x) ((_x) << 16)
> >> -
> >> -#define VIDTCON1_HFPD_MASK (0xff << 8)
> >> -#define VIDTCON1_HFPD_SHIFT (8)
> >> -#define VIDTCON1_HFPD_LIMIT (0xff)
> >> -#define VIDTCON1_HFPD(_x) ((_x) << 8)
> >> -
> >> -#define VIDTCON1_HSPW_MASK (0xff << 0)
> >> -#define VIDTCON1_HSPW_SHIFT (0)
> >> -#define VIDTCON1_HSPW_LIMIT (0xff)
> >> -#define VIDTCON1_HSPW(_x) ((_x) << 0)
> >> -
> >> -#define VIDTCON2 (0x18)
> >> -#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >>
> >> 11) << 23) -#define VIDTCON2_LINEVAL_MASK (0x7ff
> >> << 11) -#define VIDTCON2_LINEVAL_SHIFT (11)
> >> -#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
> >> -#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
> >> -
> >> -#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >>
> >> 11) << 22) -#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
> >> -#define VIDTCON2_HOZVAL_SHIFT (0)
> >> -#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
> >> -#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
> >> -
> >> -/* WINCONx */
> >> -
> >> -
> >> -#define WINCONx_BITSWP (1 << 18)
> >> -#define WINCONx_BYTSWP (1 << 17)
> >> -#define WINCONx_HAWSWP (1 << 16)
> >> -#define WINCONx_WSWP (1 << 15)
> >> -#define WINCONx_BURSTLEN_MASK (0x3 << 9)
> >> -#define WINCONx_BURSTLEN_SHIFT (9)
> >> -#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> >> -#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
> >> -#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
> >> -
> >> -#define WINCONx_ENWIN (1 << 0)
> >> -#define WINCON0_BPPMODE_MASK (0xf << 2)
> >> -#define WINCON0_BPPMODE_SHIFT (2)
> >> -#define WINCON0_BPPMODE_1BPP (0x0 << 2)
> >> -#define WINCON0_BPPMODE_2BPP (0x1 << 2)
> >> -#define WINCON0_BPPMODE_4BPP (0x2 << 2)
> >> -#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
> >> -#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
> >> -#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
> >> -#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
> >> -#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
> >> -
> >> -#define WINCON1_BLD_PIX (1 << 6)
> >> -
> >> -#define WINCON1_ALPHA_SEL (1 << 1)
> >> -#define WINCON1_BPPMODE_MASK (0xf << 2)
> >> -#define WINCON1_BPPMODE_SHIFT (2)
> >> -#define WINCON1_BPPMODE_1BPP (0x0 << 2)
> >> -#define WINCON1_BPPMODE_2BPP (0x1 << 2)
> >> -#define WINCON1_BPPMODE_4BPP (0x2 << 2)
> >> -#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
> >> -#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
> >> -#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
> >> -#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
> >> -#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
> >> -#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
> >> -#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
> >> -#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
> >> -#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
> >> -#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
> >> -#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
> >> -#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
> >> -
> >> -/* S5PV210 */
> >> -#define SHADOWCON (0x34)
> >> -#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
> >> -/* DMA channels (all windows) */
> >> -#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
> >> -/* Local input channels (windows 0-2) */
> >> -#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
> >> -
> >> -#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) <<
> >> 23) -#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
> >> -#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
> >> -#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
> >> -#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) <<
> >> 11) -
> >> -#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) <<
> >> 22) -#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
> >> -#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
> >> -#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
> >> -#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) <<
> >> 0)
> >> -
> >> -#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) <<
> >> 23) -#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
> >> -#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
> >> -#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
> >> -#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) <<
> >> 11) -
> >> -#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) <<
> >> 22) -#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
> >> -#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
> >> -#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
> >> -#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) <<
> >> 0)
> >> -
> >> -/* For VIDOSD[1..4]C */
> >> -#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
> >> -#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
> >> -#define VIDISD14C_ALPHA0_G_SHIFT (16)
> >> -#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
> >> -#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
> >> -#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
> >> -#define VIDISD14C_ALPHA0_B_SHIFT (12)
> >> -#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
> >> -#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
> >> -#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
> >> -#define VIDISD14C_ALPHA1_R_SHIFT (8)
> >> -#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
> >> -#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
> >> -#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
> >> -#define VIDISD14C_ALPHA1_G_SHIFT (4)
> >> -#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
> >> -#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
> >> -#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
> >> -#define VIDISD14C_ALPHA1_B_SHIFT (0)
> >> -#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
> >> -#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
> >> -
> >> -/* Video buffer addresses */
> >> -#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) *
> >> 8)) -#define VIDW_BUF_START1(_buff) (0xA4 +
> >> ((_buff) * 8)) -#define VIDW_BUF_END(_buff) (0xD0 +
> >> ((_buff) * 8)) -#define VIDW_BUF_END1(_buff) (0xD4 +
> >> ((_buff) * 8)) -#define VIDW_BUF_SIZE(_buff) (0x100 +
> >> ((_buff) * 4)) -
> >> -#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) <<
> >> 27) -#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
> >> -#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
> >> -#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
> >> -#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
> >> -
> >> -#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000)
> >> >> 13) << 26) -#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff <<
> >> 0)
> >> -#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
> >> -#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
> >> -#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
> >> -
> >> -/* Interrupt controls and status */
> >> -
> >> -#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
> >> -#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
> >> -#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
> >> -#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
> >> -
> >> -#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
> >> -#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
> >> -#define VIDINTCON0_INT_I80IFDONE (1 << 17)
> >> -
> >> -#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
> >> -#define VIDINTCON0_FRAMESEL0_SHIFT (15)
> >> -#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
> >> -#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
> >> -#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
> >> -#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
> >> -
> >> -#define VIDINTCON0_FRAMESEL1 (1 << 13)
> >> -#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
> >> -#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
> >> -#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
> >> -#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
> >> -#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
> >> -
> >> -#define VIDINTCON0_INT_FRAME (1 << 12)
> >> -#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
> >> -#define VIDINTCON0_FIFIOSEL_SHIFT (5)
> >> -#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
> >> -#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
> >> -
> >> -#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
> >> -#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
> >> -#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
> >> -#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
> >> -#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
> >> -#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
> >> -#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
> >> -
> >> -#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
> >> -#define VIDINTCON0_INT_FIFO_SHIFT (0)
> >> -#define VIDINTCON0_INT_ENABLE (1 << 0)
> >> -
> >> -#define VIDINTCON1 (0x134)
> >> -#define VIDINTCON1_INT_I180 (1 << 2)
> >> -#define VIDINTCON1_INT_FRAME (1 << 1)
> >> -#define VIDINTCON1_INT_FIFO (1 << 0)
> >> -
> >> -/* Window colour-key control registers */
> >> -#define WKEYCON (0x140) /*
> >> 6410,V210 */ -
> >> -#define WKEYCON0 (0x00)
> >> -#define WKEYCON1 (0x04)
> >> -
> >> -#define WxKEYCON0_KEYBL_EN (1 << 26)
> >> -#define WxKEYCON0_KEYEN_F (1 << 25)
> >> -#define WxKEYCON0_DIRCON (1 << 24)
> >> -#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
> >> -#define WxKEYCON0_COMPKEY_SHIFT (0)
> >> -#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
> >> -#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
> >> -#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
> >> -#define WxKEYCON1_COLVAL_SHIFT (0)
> >> -#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
> >> -#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
> >> -
> >> -
> >> -/* Window blanking (MAP) */
> >> -
> >> -#define WINxMAP_MAP (1 << 24)
> >> -#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
> >> -#define WINxMAP_MAP_COLOUR_SHIFT (0)
> >> -#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
> >> -#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
> >> -
> >> -#define WPALCON_PAL_UPDATE (1 << 9)
> >> -#define WPALCON_W1PAL_MASK (0x7 << 3)
> >> -#define WPALCON_W1PAL_SHIFT (3)
> >> -#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
> >> -#define WPALCON_W1PAL_24BPP (0x1 << 3)
> >> -#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
> >> -#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
> >> -#define WPALCON_W1PAL_18BPP (0x4 << 3)
> >> -#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
> >> -#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
> >> -
> >> -#define WPALCON_W0PAL_MASK (0x7 << 0)
> >> -#define WPALCON_W0PAL_SHIFT (0)
> >> -#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
> >> -#define WPALCON_W0PAL_24BPP (0x1 << 0)
> >> -#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
> >> -#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
> >> -#define WPALCON_W0PAL_18BPP (0x4 << 0)
> >> -#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> >> -#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
> >> -
> >> -/* Blending equation control */
> >> -#define BLENDCON (0x260)
> >> -#define BLENDCON_NEW_MASK (1 << 0)
> >> -#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> >> -#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
> >> -
> >> diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
> >> new file mode 100644
> >> index 0000000..1b5ff4c
> >> --- /dev/null
> >> +++ b/include/video/samsung_fimd.h
> >> @@ -0,0 +1,533 @@
> >> +/* include/video/samsung_fimd.h
> >> + *
> >> + * Copyright 2008 Openmoko, Inc.
> >> + * Copyright 2008 Simtec Electronics
> >> + * http://armlinux.simtec.co.uk/
> >> + * Ben Dooks <ben@simtec.co.uk>
> >> + *
> >> + * S3C Platform - new-style fimd and framebuffer register definitions
> >> + *
> >> + * This is the register set for the fimd and new style framebuffer
> >> interface + * found from the S3C2443 onwards into the S3C2416, S3C2450
> >> and the + * S3C64XX series such as the S3C6400 and S3C6410.
> >> + *
> >> + * The file does not contain the cpu specific items which are based on
> >> + * whichever architecture is selected, it only contains the core of the
> >> + * register set. See <mach/regs-fb.h> to get the specifics.
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License version 2 as
> >> + * published by the Free Software Foundation.
> >> +*/
> >> +
> >> +/* VIDCON0 */
> >> +
> >> +#define VIDCON0 (0x00)
> >> +#define VIDCON0_INTERLACE (1 << 29)
> >> +#define VIDCON0_VIDOUT_MASK (0x3 << 26)
> >> +#define VIDCON0_VIDOUT_SHIFT (26)
> >> +#define VIDCON0_VIDOUT_RGB (0x0 << 26)
> >> +#define VIDCON0_VIDOUT_TV (0x1 << 26)
> >> +#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> >> +#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> >> +
> >> +#define VIDCON0_L1_DATA_MASK (0x7 << 23)
> >> +#define VIDCON0_L1_DATA_SHIFT (23)
> >> +#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
> >> +#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
> >> +#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
> >> +#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
> >> +#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
> >> +#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
> >> +
> >> +#define VIDCON0_L0_DATA_MASK (0x7 << 20)
> >> +#define VIDCON0_L0_DATA_SHIFT (20)
> >> +#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
> >> +#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
> >> +#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
> >> +#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
> >> +#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
> >> +#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
> >> +
> >> +#define VIDCON0_PNRMODE_MASK (0x3 << 17)
> >> +#define VIDCON0_PNRMODE_SHIFT (17)
> >> +#define VIDCON0_PNRMODE_RGB (0x0 << 17)
> >> +#define VIDCON0_PNRMODE_BGR (0x1 << 17)
> >> +#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
> >> +#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
> >> +
> >> +#define VIDCON0_CLKVALUP (1 << 16)
> >> +#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
> >> +#define VIDCON0_CLKVAL_F_SHIFT (6)
> >> +#define VIDCON0_CLKVAL_F_LIMIT (0xff)
> >> +#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
> >> +#define VIDCON0_VLCKFREE (1 << 5)
> >> +#define VIDCON0_CLKDIR (1 << 4)
> >> +
> >> +#define VIDCON0_CLKSEL_MASK (0x3 << 2)
> >> +#define VIDCON0_CLKSEL_SHIFT (2)
> >> +#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
> >> +#define VIDCON0_CLKSEL_LCD (0x1 << 2)
> >> +#define VIDCON0_CLKSEL_27M (0x3 << 2)
> >> +
> >> +#define VIDCON0_ENVID (1 << 1)
> >> +#define VIDCON0_ENVID_F (1 << 0)
> >> +
> >> +#define VIDCON1 (0x04)
> >> +#define VIDCON1_LINECNT_MASK (0x7ff << 16)
> >> +#define VIDCON1_LINECNT_SHIFT (16)
> >> +#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) &
> >> 0x7ff) +#define VIDCON1_VSTATUS_MASK (0x3 << 13)
> >> +#define VIDCON1_VSTATUS_SHIFT (13)
> >> +#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
> >> +#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
> >> +#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
> >> +#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
> >> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> >> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> >> +#define VIDCON1_VCLK_RUN (0x1 << 9)
> >> +
> >> +#define VIDCON1_INV_VCLK (1 << 7)
> >> +#define VIDCON1_INV_HSYNC (1 << 6)
> >> +#define VIDCON1_INV_VSYNC (1 << 5)
> >> +#define VIDCON1_INV_VDEN (1 << 4)
> >> +
> >> +/* VIDCON2 */
> >> +
> >> +#define VIDCON2 (0x08)
> >> +#define VIDCON2_EN601 (1 << 23)
> >> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> >> +
> >> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> >> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> >> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> >> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> >> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> >> +
> >> +#define VIDCON2_ORGYCbCr (1 << 8)
> >> +#define VIDCON2_YUVORDCrCb (1 << 7)
> >> +
> >> +/* PRTCON (S3C6410, S5PC100)
> >> + * Might not be present in the S3C6410 documentation,
> >> + * but tests prove it's there almost for sure; shouldn't hurt in any
> >> case.
> >> + */
> >> +#define PRTCON (0x0c)
> >> +#define PRTCON_PROTECT (1 << 11)
> >> +
> >> +/* VIDTCON0 */
> >> +
> >> +#define VIDTCON0_VBPDE_MASK (0xff << 24)
> >> +#define VIDTCON0_VBPDE_SHIFT (24)
> >> +#define VIDTCON0_VBPDE_LIMIT (0xff)
> >> +#define VIDTCON0_VBPDE(_x) ((_x) << 24)
> >> +
> >> +#define VIDTCON0_VBPD_MASK (0xff << 16)
> >> +#define VIDTCON0_VBPD_SHIFT (16)
> >> +#define VIDTCON0_VBPD_LIMIT (0xff)
> >> +#define VIDTCON0_VBPD(_x) ((_x) << 16)
> >> +
> >> +#define VIDTCON0_VFPD_MASK (0xff << 8)
> >> +#define VIDTCON0_VFPD_SHIFT (8)
> >> +#define VIDTCON0_VFPD_LIMIT (0xff)
> >> +#define VIDTCON0_VFPD(_x) ((_x) << 8)
> >> +
> >> +#define VIDTCON0_VSPW_MASK (0xff << 0)
> >> +#define VIDTCON0_VSPW_SHIFT (0)
> >> +#define VIDTCON0_VSPW_LIMIT (0xff)
> >> +#define VIDTCON0_VSPW(_x) ((_x) << 0)
> >> +
> >> +/* VIDTCON1 */
> >> +
> >> +#define VIDTCON1_VFPDE_MASK (0xff << 24)
> >> +#define VIDTCON1_VFPDE_SHIFT (24)
> >> +#define VIDTCON1_VFPDE_LIMIT (0xff)
> >> +#define VIDTCON1_VFPDE(_x) ((_x) << 24)
> >> +
> >> +#define VIDTCON1_HBPD_MASK (0xff << 16)
> >> +#define VIDTCON1_HBPD_SHIFT (16)
> >> +#define VIDTCON1_HBPD_LIMIT (0xff)
> >> +#define VIDTCON1_HBPD(_x) ((_x) << 16)
> >> +
> >> +#define VIDTCON1_HFPD_MASK (0xff << 8)
> >> +#define VIDTCON1_HFPD_SHIFT (8)
> >> +#define VIDTCON1_HFPD_LIMIT (0xff)
> >> +#define VIDTCON1_HFPD(_x) ((_x) << 8)
> >> +
> >> +#define VIDTCON1_HSPW_MASK (0xff << 0)
> >> +#define VIDTCON1_HSPW_SHIFT (0)
> >> +#define VIDTCON1_HSPW_LIMIT (0xff)
> >> +#define VIDTCON1_HSPW(_x) ((_x) << 0)
> >> +
> >> +#define VIDTCON2 (0x18)
> >> +#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >>
> >> 11) << 23) +#define VIDTCON2_LINEVAL_MASK (0x7ff
> >> << 11) +#define VIDTCON2_LINEVAL_SHIFT (11)
> >> +#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
> >> +#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
> >> +
> >> +#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >>
> >> 11) << 22) +#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
> >> +#define VIDTCON2_HOZVAL_SHIFT (0)
> >> +#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
> >> +#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
> >> +
> >> +/* WINCONx */
> >> +
> >> +
> >> +#define WINCONx_BITSWP (1 << 18)
> >> +#define WINCONx_BYTSWP (1 << 17)
> >> +#define WINCONx_HAWSWP (1 << 16)
> >> +#define WINCONx_WSWP (1 << 15)
> >> +#define WINCONx_BURSTLEN_MASK (0x3 << 9)
> >> +#define WINCONx_BURSTLEN_SHIFT (9)
> >> +#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> >> +#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
> >> +#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
> >> +
> >> +#define WINCONx_ENWIN (1 << 0)
> >> +#define WINCON0_BPPMODE_MASK (0xf << 2)
> >> +#define WINCON0_BPPMODE_SHIFT (2)
> >> +#define WINCON0_BPPMODE_1BPP (0x0 << 2)
> >> +#define WINCON0_BPPMODE_2BPP (0x1 << 2)
> >> +#define WINCON0_BPPMODE_4BPP (0x2 << 2)
> >> +#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
> >> +#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
> >> +#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
> >> +#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
> >> +#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
> >> +
> >> +#define WINCON1_BLD_PIX (1 << 6)
> >> +
> >> +#define WINCON1_ALPHA_SEL (1 << 1)
> >> +#define WINCON1_BPPMODE_MASK (0xf << 2)
> >> +#define WINCON1_BPPMODE_SHIFT (2)
> >> +#define WINCON1_BPPMODE_1BPP (0x0 << 2)
> >> +#define WINCON1_BPPMODE_2BPP (0x1 << 2)
> >> +#define WINCON1_BPPMODE_4BPP (0x2 << 2)
> >> +#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
> >> +#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
> >> +#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
> >> +#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
> >> +#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
> >> +#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
> >> +#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
> >> +#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
> >> +#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
> >> +#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
> >> +#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
> >> +#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
> >> +
> >> +/* S5PV210 */
> >> +#define SHADOWCON (0x34)
> >> +#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
> >> +/* DMA channels (all windows) */
> >> +#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
> >> +/* Local input channels (windows 0-2) */
> >> +#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
> >> +
> >> +#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) <<
> >> 23) +#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
> >> +#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
> >> +#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
> >> +#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) <<
> >> 11) +
> >> +#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) <<
> >> 22) +#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
> >> +#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
> >> +#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
> >> +#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) <<
> >> 0)
> >> +
> >> +#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) <<
> >> 23) +#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
> >> +#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
> >> +#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
> >> +#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) <<
> >> 11) +
> >> +#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) <<
> >> 22) +#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
> >> +#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
> >> +#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
> >> +#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) <<
> >> 0)
> >> +
> >> +/* For VIDOSD[1..4]C */
> >> +#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
> >> +#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
> >> +#define VIDISD14C_ALPHA0_G_SHIFT (16)
> >> +#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
> >> +#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
> >> +#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
> >> +#define VIDISD14C_ALPHA0_B_SHIFT (12)
> >> +#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
> >> +#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
> >> +#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
> >> +#define VIDISD14C_ALPHA1_R_SHIFT (8)
> >> +#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
> >> +#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
> >> +#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
> >> +#define VIDISD14C_ALPHA1_G_SHIFT (4)
> >> +#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
> >> +#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
> >> +#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
> >> +#define VIDISD14C_ALPHA1_B_SHIFT (0)
> >> +#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
> >> +#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
> >> +
> >> +/* Video buffer addresses */
> >> +#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) *
> >> 8)) +#define VIDW_BUF_START1(_buff) (0xA4 +
> >> ((_buff) * 8)) +#define VIDW_BUF_END(_buff) (0xD0 +
> >> ((_buff) * 8)) +#define VIDW_BUF_END1(_buff) (0xD4 +
> >> ((_buff) * 8)) +#define VIDW_BUF_SIZE(_buff) (0x100 +
> >> ((_buff) * 4)) +
> >> +#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) <<
> >> 27) +#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
> >> +#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
> >> +#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
> >> +#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
> >> +
> >> +#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000)
> >> >> 13) << 26) +#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff <<
> >> 0)
> >> +#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
> >> +#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
> >> +#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
> >> +
> >> +/* Interrupt controls and status */
> >> +
> >> +#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
> >> +#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
> >> +#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
> >> +#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
> >> +
> >> +#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
> >> +#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
> >> +#define VIDINTCON0_INT_I80IFDONE (1 << 17)
> >> +
> >> +#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
> >> +#define VIDINTCON0_FRAMESEL0_SHIFT (15)
> >> +#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
> >> +#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
> >> +#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
> >> +#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
> >> +
> >> +#define VIDINTCON0_FRAMESEL1 (1 << 13)
> >> +#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
> >> +#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
> >> +#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
> >> +#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
> >> +#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
> >> +
> >> +#define VIDINTCON0_INT_FRAME (1 << 12)
> >> +#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
> >> +#define VIDINTCON0_FIFIOSEL_SHIFT (5)
> >> +#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
> >> +#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
> >> +
> >> +#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
> >> +#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
> >> +#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
> >> +#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
> >> +#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
> >> +#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
> >> +#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
> >> +
> >> +#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
> >> +#define VIDINTCON0_INT_FIFO_SHIFT (0)
> >> +#define VIDINTCON0_INT_ENABLE (1 << 0)
> >> +
> >> +#define VIDINTCON1 (0x134)
> >> +#define VIDINTCON1_INT_I180 (1 << 2)
> >> +#define VIDINTCON1_INT_FRAME (1 << 1)
> >> +#define VIDINTCON1_INT_FIFO (1 << 0)
> >> +
> >> +/* Window colour-key control registers */
> >> +#define WKEYCON (0x140) /*
> >> 6410,V210 */ +
> >> +#define WKEYCON0 (0x00)
> >> +#define WKEYCON1 (0x04)
> >> +
> >> +#define WxKEYCON0_KEYBL_EN (1 << 26)
> >> +#define WxKEYCON0_KEYEN_F (1 << 25)
> >> +#define WxKEYCON0_DIRCON (1 << 24)
> >> +#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
> >> +#define WxKEYCON0_COMPKEY_SHIFT (0)
> >> +#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
> >> +#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
> >> +#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
> >> +#define WxKEYCON1_COLVAL_SHIFT (0)
> >> +#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
> >> +#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
> >> +
> >> +
> >> +/* Window blanking (MAP) */
> >> +
> >> +#define WINxMAP_MAP (1 << 24)
> >> +#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
> >> +#define WINxMAP_MAP_COLOUR_SHIFT (0)
> >> +#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
> >> +#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
> >> +
> >> +#define WPALCON_PAL_UPDATE (1 << 9)
> >> +#define WPALCON_W1PAL_MASK (0x7 << 3)
> >> +#define WPALCON_W1PAL_SHIFT (3)
> >> +#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
> >> +#define WPALCON_W1PAL_24BPP (0x1 << 3)
> >> +#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
> >> +#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
> >> +#define WPALCON_W1PAL_18BPP (0x4 << 3)
> >> +#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
> >> +#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
> >> +
> >> +#define WPALCON_W0PAL_MASK (0x7 << 0)
> >> +#define WPALCON_W0PAL_SHIFT (0)
> >> +#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
> >> +#define WPALCON_W0PAL_24BPP (0x1 << 0)
> >> +#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
> >> +#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
> >> +#define WPALCON_W0PAL_18BPP (0x4 << 0)
> >> +#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> >> +#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
> >> +
> >> +/* Blending equation control */
> >> +#define BLENDCON (0x260)
> >> +#define BLENDCON_NEW_MASK (1 << 0)
> >> +#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> >> +#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
> >> +
> >> +#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
> >> +#define VIDCON1_FSTATUS_EVEN (1 << 15)
> >> +
> >> +/* Video timing controls */
> >> +#define VIDTCON0 (0x10)
> >> +#define VIDTCON1 (0x14)
> >> +#define VIDTCON2 (0x18)
> >> +
> >> +/* Window position controls */
> >> +
> >> +#define WINCON(_win) (0x20 + ((_win) * 4))
> >> +
> >> +/* OSD1 and OSD4 do not have register D */
> >> +
> >> +#define VIDOSD_BASE (0x40)
> >> +
> >> +#define VIDINTCON0 (0x130)
> >> +
> >> +/* WINCONx */
> >> +
> >> +#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> >> +#define WINCONx_CSCWIDTH_SHIFT (26)
> >> +#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> >> +#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
> >> +
> >> +#define WINCONx_ENLOCAL (1 << 22)
> >> +#define WINCONx_BUFSTATUS (1 << 21)
> >> +#define WINCONx_BUFSEL (1 << 20)
> >> +#define WINCONx_BUFAUTOEN (1 << 19)
> >> +#define WINCONx_YCbCr (1 << 13)
> >> +
> >> +#define WINCON1_LOCALSEL_CAMIF (1 << 23)
> >> +
> >> +#define WINCON2_LOCALSEL_CAMIF (1 << 23)
> >> +#define WINCON2_BLD_PIX (1 << 6)
> >> +
> >> +#define WINCON2_ALPHA_SEL (1 << 1)
> >> +#define WINCON2_BPPMODE_MASK (0xf << 2)
> >> +#define WINCON2_BPPMODE_SHIFT (2)
> >> +#define WINCON2_BPPMODE_1BPP (0x0 << 2)
> >> +#define WINCON2_BPPMODE_2BPP (0x1 << 2)
> >> +#define WINCON2_BPPMODE_4BPP (0x2 << 2)
> >> +#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
> >> +#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
> >> +#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
> >> +#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
> >> +#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
> >> +#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
> >> +#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
> >> +#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
> >> +#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
> >> +#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
> >> +#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
> >> +
> >> +#define WINCON3_BLD_PIX (1 << 6)
> >> +
> >> +#define WINCON3_ALPHA_SEL (1 << 1)
> >> +#define WINCON3_BPPMODE_MASK (0xf << 2)
> >> +#define WINCON3_BPPMODE_SHIFT (2)
> >> +#define WINCON3_BPPMODE_1BPP (0x0 << 2)
> >> +#define WINCON3_BPPMODE_2BPP (0x1 << 2)
> >> +#define WINCON3_BPPMODE_4BPP (0x2 << 2)
> >> +#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
> >> +#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
> >> +#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
> >> +#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
> >> +#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
> >> +#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
> >> +#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
> >> +#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
> >> +#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
> >> +#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
> >> +
> >> +#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
> >> +#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
> >> +#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
> >> +
> >> +#define DITHMODE (0x170)
> >> +#define WINxMAP(_win) (0x180 + ((_win) *
> >> 4)) +
> >> +
> >> +#define DITHMODE_R_POS_MASK (0x3 << 5)
> >> +#define DITHMODE_R_POS_SHIFT (5)
> >> +#define DITHMODE_R_POS_8BIT (0x0 << 5)
> >> +#define DITHMODE_R_POS_6BIT (0x1 << 5)
> >> +#define DITHMODE_R_POS_5BIT (0x2 << 5)
> >> +
> >> +#define DITHMODE_G_POS_MASK (0x3 << 3)
> >> +#define DITHMODE_G_POS_SHIFT (3)
> >> +#define DITHMODE_G_POS_8BIT (0x0 << 3)
> >> +#define DITHMODE_G_POS_6BIT (0x1 << 3)
> >> +#define DITHMODE_G_POS_5BIT (0x2 << 3)
> >> +
> >> +#define DITHMODE_B_POS_MASK (0x3 << 1)
> >> +#define DITHMODE_B_POS_SHIFT (1)
> >> +#define DITHMODE_B_POS_8BIT (0x0 << 1)
> >> +#define DITHMODE_B_POS_6BIT (0x1 << 1)
> >> +#define DITHMODE_B_POS_5BIT (0x2 << 1)
> >> +
> >> +#define DITHMODE_DITH_EN (1 << 0)
> >> +
> >> +#define WPALCON (0x1A0)
> >> +
> >> +/* Palette control */
> >> +/* Note for S5PC100: you can still use those macros on WPALCON (aka
> >> WPALCON_L), + * but make sure that WPALCON_H W2PAL-W4PAL entries are
> >> zeroed out */ +#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
> >> +#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
> >> +#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
> >> +
> >> +
> >> +/* Notes on per-window bpp settings
> >> + *
> >> + * Value Win0 Win1 Win2 Win3 Win 4
> >> + * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
> >> + * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
> >> + * 0010 4(P) 4(P) 4(P) 4(P) -none-
> >> + * 0011 8(P) 8(P) -none- -none- -none-
> >> + * 0100 -none- 8(A232) 8(A232) -none- -none-
> >> + * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
> >> + * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
> >> + * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
> >> + * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
> >> + * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
> >> + * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
> >> + * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
> >> + * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
> >> + * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
> >> + * 1110 -none- -none- -none- -none- -none-
> >> + * 1111 -none- -none- -none- -none- -none-
> >> +*/
> >> +
> >> +/*FIMD V8 REG OFFSET */
> >> +#define FIMD_V8_VIDTCON0 (0x20010)
> >> +#define FIMD_V8_VIDTCON1 (0x20014)
> >> +#define FIMD_V8_VIDTCON2 (0x20018)
> >> +#define FIMD_V8_VIDTCON3 (0x2001C)
> >> +#define FIMD_V8_VIDCON1 (0x20004)
> >
> > CC'ed Marek.
> >
> > To Leela Krishna Amudala,
> >
> > Don't add these definitions for FIMD_V8_xxx registers, which are not
> > related to current "regs-fb-v4.h and regs-fb.h". Just "move" and "merge"
> > regs-fb-v4.h and regs-fb.h to one header file, not "add" new definitions.
> > If you want to add these definitions, please make new patch for this.
> Will do it in the suggested way,
>
> > Also, "#define FIMD_V8_xxx" is ugly.
> > I think that there is better way.
> > Please, find other way.
>
> I used FIMD_V8_xxx instead of EXYNOS5_FIMD_*, because in future,
> there is a possibility that version 8 FIMD can be used in other
> application processors also.
> Thanks for reviewing the patch.
Possibly a simple "#define REGNAME_V8 ..." would be better?
Best regards,
Tomasz Figa
>
> Best Wishes,
> Leela Krishna.
>
> >> --
> >> 1.7.0.4
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH] Fix newport con crashes
From: Ralf Baechle @ 2012-07-30 13:34 UTC (permalink / raw)
To: Thomas Bogendoerfer; +Cc: linux-mips, linux-fbdev, FlorianSchandinat
In-Reply-To: <20120730105416.DBB961D1CF@solo.franken.de>
On Mon, Jul 30, 2012 at 12:54:16PM +0200, Thomas Bogendoerfer wrote:
> Because of commit e84de0c61905030a0fe66b7210b6f1bb7c3e1eab
> [MIPS: GIO bus support for SGI IP22/28] newport con is now taking over
> console from dummy con, therefore it's necessary to resize the VC to
> the correct size to avoid crashes and garbage on console
>
> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
I've applied your patch to master and the affected -stable branches of the
lmo git tree.
Florian, since this is a driver specific to certain MIPS platforms I'd like
to merge it through the MIPS tree with your ack, if that's ok?
Thanks folks,
Ralf
^ permalink raw reply
* Re: [RFC][PATCH v3 1/3] runtime interpreted power sequences
From: Thierry Reding @ 2012-07-30 11:33 UTC (permalink / raw)
To: Alexandre Courbot
Cc: linux-fbdev-u79uwXL29TY76Z2rM5mHXA, Stephen Warren,
Greg Kroah-Hartman, Mark Brown,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <1343390750-3642-2-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 24790 bytes --]
On Fri, Jul 27, 2012 at 09:05:48PM +0900, Alexandre Courbot wrote:
> Some device drivers (panel backlights especially) need to follow precise
> sequences for powering on and off, involving gpios, regulators, PWMs
> with a precise powering order and delays to respect between each steps.
> These sequences are board-specific, and do not belong to a particular
> driver - therefore they have been performed by board-specific hook
> functions to far.
>
> With the advent of the device tree and of ARM kernels that are not
> board-tied, we cannot rely on these board-specific hooks anymore but
> need a way to implement these sequences in a portable manner. This patch
> introduces a simple interpreter that can execute such power sequences
> encoded either as platform data or within the device tree.
>
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
> ---
> Documentation/power/power_seq.txt | 120 +++++++++++++++
> drivers/base/Kconfig | 4 +
> drivers/base/Makefile | 1 +
> drivers/base/power_seq.c | 300 ++++++++++++++++++++++++++++++++++++++
> include/linux/power_seq.h | 139 ++++++++++++++++++
> 5 files changed, 564 insertions(+)
> create mode 100644 Documentation/power/power_seq.txt
> create mode 100644 drivers/base/power_seq.c
> create mode 100644 include/linux/power_seq.h
>
> diff --git a/Documentation/power/power_seq.txt b/Documentation/power/power_seq.txt
> new file mode 100644
> index 0000000..aa2ceb5
> --- /dev/null
> +++ b/Documentation/power/power_seq.txt
> @@ -0,0 +1,120 @@
> +Runtime Interpreted Power Sequences
> +-----------------------------------
> +
> +Problem
> +-------
> +One very common board-dependent code is the out-of-driver code that is used to
> +turn a device on or off. For instance, SoC boards very commonly use a GPIO
> +(abstracted to a regulator or not) to control the power supply of a backlight,
> +disabling it when the backlight is not used in order to save power. The GPIO
> +that should be used, however, as well as the exact power sequence that may
> +involve different resources, is board-dependent and thus unknown of the driver.
> +
> +This has been addressed so far by using hooks in the device's platform data that
> +are called whenever the state of the device might reflect a power change. This
> +approach, however, introduces board-dependant code into the kernel and is not
> +compatible with the device tree.
> +
> +The Runtime Interpreted Power Sequences (or power sequences for short) aim at
> +turning this code into platform data or device tree nodes. Power sequences are
> +described using a simple format and run by a simple interpreter whenever needed.
> +This allows to remove the callback mechanism and makes the kernel less
> +board-dependant.
> +
> +Sequences Format
> +----------------
> +Power sequences are a series of sequential steps during which an action is
> +performed on a resource. The supported resources so far are:
> +- GPIOs
> +- Regulators
> +- PWMs
> +
> +Each step designates a resource and the following parameters:
> +- Whether the step should enable or disable the resource,
> +- Delay to wait before performing the action,
> +- Delay to wait after performing the action.
> +
> +Both new resources and parameters can be introduced, but the goal is of course
> +to keep things as simple and compact as possible.
> +
> +The platform data is a simple array of platform_power_seq_step instances, each
> +instance describing a step. The type as well as one of id or gpio members
> +(depending on the type) must be specified. The last step must be of type
> +POWER_SEQ_STOP. Regulator and PWM resources are identified by name. GPIO are
> +identified by number. For example, the following sequence will turn on the
> +"power" regulator of the device, wait 10ms, and set GPIO number 110 to 1:
> +
> +struct platform_power_seq_step power_on_seq[] = {
> + {
> + .type = POWER_SEQ_REGULATOR,
> + .id = "power",
> + .params = {
> + .enable = 1,
> + .post_delay = 10,
> + },
> + },
> + {
> + .type = POWER_SEQ_GPIO,
> + .gpio = 110,
> + .params = {
> + .enable = 1,
> + },
> + },
> + {
> + .type = POWER_SEQ_STOP,
> + },
> +};
> +
> +Usage by Drivers and Resources Management
> +-----------------------------------------
> +Power sequences make use of resources that must be properly allocated and
> +managed. The power_seq_build() function takes care of resolving the resources as
> +they are met in the sequence and to allocate them if needed:
> +
> +power_seq *power_seq_build(struct device *dev, power_seq_resources *ress,
> + platform_power_seq *pseq);
> +
> +You will need an instance of power_seq_resources to keep track of the resources
> +that are already allocated. On success, the function returns a devm allocated
> +resolved sequence that is ready to be passed to power_seq_run(). In case of
> +failure, and error code is returned.
I don't quite understand why the struct power_seq_resources is needed.
Can this not be stored within power_seq?
> +
> +A resolved power sequence returned by power_seq_build can be run by
> +power_run_run():
> +
> +int power_seq_run(struct device *dev, power_seq *seq);
Why is the struct device required here? It already is passed during the
call to pwm_seq_build(), so perhaps you should keep a reference to it
within struct power_seq?
> +
> +It returns 0 if the sequence has successfully been run, or an error code if a
> +problem occured.
> +
> +Finally, some resources that cannot be allocated through devm need to be freed
> +manually. Therefore, be sure to call power_seq_free_resources() in your device
> +remove function:
> +
> +void power_seq_free_resources(power_seq_resources *ress);
Could this not also be handled by a managed version? If a power_seq is
always managed, then I would assume that it also takes care of freeing
the resources, even if the resources have no managed equivalents.
Perhaps it would also make sense to provide non-managed version of these
functions. I think that would make the managed versions easier and more
canonical to implement.
> +
> +Device tree
> +-----------
> +All the same, power sequences can be encoded as device tree nodes. The following
> +properties and nodes are equivalent to the platform data defined previously:
> +
> + power-supply = <&mydevice_reg>;
> + enable-gpio = <&gpio 6 0>;
> +
> + power-on-sequence {
> + regulator@0 {
> + id = "power";
> + enable;
> + post-delay = <10>;
> + };
> + gpio@1 {
> + id = "enable-gpio";
> + enable;
> + };
> + };
> +
> +Note that first, the phandles of the regulator and gpio used in the sequences
> +are defined as properties. Then the sequence references them through the id
> +property of every step. The name of sub-properties defines the type of the step.
> +Valid names are "regulator", "gpio" and "pwm". Steps must be numbered
> +sequentially.
I think there has been quite some discussion regarding the naming of
subnodes and the conclusion seems to have been to name them uniformly
after what they represent. As such the power-on-sequence subnodes should
be called step@0, step@1, etc. However, that will require the addition
of a property to define the type of resource.
Also, is there some way we can make the id property for GPIOs not
require the -gpio suffix? If the resource type is already GPIO, then it
seems redundant to add -gpio to the ID.
> diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
> index 08b4c52..65bebfe 100644
> --- a/drivers/base/Kconfig
> +++ b/drivers/base/Kconfig
> @@ -282,4 +282,8 @@ config CMA_AREAS
>
> endif
>
> +config POWER_SEQ
> + bool
> + default n
> +
"default n" is already the default, so you can drop that line.
> endmenu
> diff --git a/drivers/base/Makefile b/drivers/base/Makefile
> index 5aa2d70..4c498c1 100644
> --- a/drivers/base/Makefile
> +++ b/drivers/base/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_MEMORY_HOTPLUG_SPARSE) += memory.o
> ifeq ($(CONFIG_SYSFS),y)
> obj-$(CONFIG_MODULES) += module.o
> endif
> +obj-$(CONFIG_POWER_SEQ) += power_seq.o
> obj-$(CONFIG_SYS_HYPERVISOR) += hypervisor.o
> obj-$(CONFIG_REGMAP) += regmap/
> obj-$(CONFIG_SOC_BUS) += soc.o
> diff --git a/drivers/base/power_seq.c b/drivers/base/power_seq.c
> new file mode 100644
> index 0000000..6ccefa1
> --- /dev/null
> +++ b/drivers/base/power_seq.c
> @@ -0,0 +1,300 @@
> +/*
> + * power_seq.c - A simple power sequence interpreter for platform devices
> + * and device tree.
> + *
> + * Author: Alexandre Courbot <acourbot@nvidia.com>
> + *
> + * Copyright (c) 2012 NVIDIA Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
> + *
> + */
> +
> +#include <linux/power_seq.h>
> +#include <linux/module.h>
> +#include <linux/err.h>
> +#include <linux/device.h>
> +#include <linux/slab.h>
> +#include <linux/delay.h>
> +#include <linux/pwm.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/gpio.h>
> +
> +#ifdef CONFIG_OF
> +#include <linux/of.h>
> +#include <linux/of_gpio.h>
> +#endif
I think you don't need the CONFIG_OF guard around these. Both of.h and
of_gpio.h can be included unconditionally and actually contain dummy
definitions for the public functions in the !OF case.
> +
> +static int power_seq_step_run(struct power_seq_step *step)
> +{
> + int err = 0;
> +
> + if (step->params.pre_delay)
> + mdelay(step->params.pre_delay);
> +
> + switch (step->resource->type) {
> +#ifdef CONFIG_REGULATOR
> + case POWER_SEQ_REGULATOR:
> + if (step->params.enable)
> + err = regulator_enable(step->resource->regulator);
> + else
> + err = regulator_disable(step->resource->regulator);
> + break;
> +#endif
> +#ifdef CONFIG_PWM
> + case POWER_SEQ_PWM:
> + if (step->params.enable)
> + err = pwm_enable(step->resource->pwm);
> + else
> + pwm_disable(step->resource->pwm);
> + break;
> +#endif
> +#ifdef CONFIG_GPIOLIB
> + case POWER_SEQ_GPIO:
> + gpio_set_value_cansleep(step->resource->gpio,
> + step->params.enable);
> + break;
> +#endif
This kind of #ifdef'ery is quite ugly. I don't know if adding separate
*_run() functions for each type of resource would be any better, though.
Alternatively, maybe POWER_SEQ should depend on the REGULATOR, PWM and
GPIOLIB symbols to side-step the issue completely?
> + /*
> + * should never happen unless the sequence includes a step which
> + * type does not have support compiled in
> + */
> + default:
> + return -EINVAL;
> + }
> +
> + if (err < 0)
> + return err;
> +
> + if (step->params.post_delay)
> + mdelay(step->params.post_delay);
> +
> + return 0;
> +}
> +
> +int power_seq_run(struct device *dev, power_seq *seq)
> +{
> + int err;
> +
> + if (!seq) return 0;
I don't think this is acceptable according to the coding style. Also,
perhaps returning -EINVAL would be more meaningful?
> +
> + while (seq->resource) {
Perhaps this should check for POWER_SEQ_STOP instead?
> + if ((err = power_seq_step_run(seq++))) {
> + dev_err(dev, "error %d while running power sequence!\n",
> + err);
For this kind of diagnostics it could be useful to have a name
associated with the power sequence. But I'm not sure that making the
power sequence code output an error here is the best solution. I find it
to be annoying when core code starts outputting too many error codes. In
this case it's particularily easy to catch the errors in the caller.
> + return err;
> + }
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(power_seq_run);
> +
> +#ifdef CONFIG_OF
> +static int of_parse_power_seq_step(struct device *dev, struct device_node *node,
> + struct platform_power_seq_step *step)
> +{
> + if (of_property_read_string(node, "id", &step->id)) {
> + dev_err(dev, "missing id property!\n");
> + return -EINVAL;
> + }
> +
> + if (!strcmp(node->name, "regulator")) {
> + step->type = POWER_SEQ_REGULATOR;
> +#ifdef CONFIG_OF_GPIO
> + } else if (!strcmp(node->name, "gpio")) {
> + int gpio;
> +
> + step->type = POWER_SEQ_GPIO;
> + gpio = of_get_named_gpio(dev->of_node, step->id, 0);
> + if (gpio < 0) {
> + dev_err(dev, "cannot resolve gpio \"%s\"\n", step->id);
> + return gpio;
> + }
> + step->gpio = gpio;
> +#endif /* CONFIG_OF_GPIO */
> + } else if (!strcmp(node->name, "pwm")) {
> + step->type = POWER_SEQ_PWM;
> + } else {
> + dev_err(dev, "invalid power seq step type!\n");
> + return -EINVAL;
> + }
> +
> + if (of_find_property(node, "enable", NULL)) {
> + step->params.enable = 1;
> + } else if (!of_find_property(node, "disable", NULL)) {
> + dev_err(dev, "missing enable or disable property!\n");
> + return -EINVAL;
> + }
> +
> + of_property_read_u32(node, "pre-delay", &step->params.pre_delay);
> + of_property_read_u32(node, "post-delay", &step->params.post_delay);
> +
> + return 0;
> +}
> +
> +platform_power_seq *of_parse_power_seq(struct device *dev,
> + struct device_node *node)
> +{
> + struct device_node *child = NULL;
> + platform_power_seq *ret;
> + int cpt = 0;
> + int err;
> +
> + if (!node) return NULL;
Again, this should probably be split across two lines.
> +
> + while ((child = of_get_next_child(node, child)))
> + cpt++;
for_each_child_of_node()?
> +
> + /* allocate one more step to signal end of sequence */
> + ret = devm_kzalloc(dev, sizeof(*ret) * (cpt + 1), GFP_KERNEL);
> + if (!ret)
> + return ERR_PTR(-ENOMEM);
> +
> + cpt = 0;
> + while ((child = of_get_next_child(node, child))) {
Here as well.
> + if ((err = of_parse_power_seq_step(dev, child, &ret[cpt++])))
> + return ERR_PTR(err);
> + }
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(of_parse_power_seq);
> +#endif /* CONFIG_OF */
> +
> +static
> +struct power_seq_resource * power_seq_find_resource(power_seq_resources *ress,
> + struct platform_power_seq_step *res)
> +{
> + struct power_seq_resource *step;
> +
> + list_for_each_entry(step, ress, list) {
> + if (step->type != res->type) continue;
> + switch (res->type) {
> + case POWER_SEQ_GPIO:
> + if (step->gpio == res->gpio)
> + return step;
> + break;
> + default:
> + if (!strcmp(step->id, res->id))
> + return step;
> + break;
> + }
> + }
> +
> + return NULL;
> +}
> +
> +static int power_seq_allocate_resource(struct device *dev,
> + struct power_seq_resource *res)
> +{
> + int err;
> +
> + switch (res->type) {
> +#ifdef CONFIG_REGULATOR
> + case POWER_SEQ_REGULATOR:
> + res->regulator = devm_regulator_get(dev, res->id);
> + if (IS_ERR(res->regulator)) {
> + dev_err(dev, "cannot get regulator \"%s\"\n", res->id);
> + return PTR_ERR(res->regulator);
> + }
> + break;
> +#endif
> +#ifdef CONFIG_PWM
> + case POWER_SEQ_PWM:
> + res->pwm = pwm_get(dev, res->id);
> + if (IS_ERR(res->pwm)) {
> + dev_err(dev, "cannot get pwm \"%s\"\n", res->id);
> + return PTR_ERR(res->pwm);
> + }
> + break;
> +#endif
> +#ifdef CONFIG_GPIOLIB
> + case POWER_SEQ_GPIO:
> + err = devm_gpio_request_one(dev, res->gpio, GPIOF_OUT_INIT_HIGH,
> + "backlight_gpio");
> + if (err) {
> + dev_err(dev, "cannot get gpio %d\n", res->gpio);
> + return err;
> + }
> + break;
> +#endif
> + default:
> + dev_err(dev, "invalid resource type %d\n", res->type);
> + return -EINVAL;
> + break;
> + }
> +
> + return 0;
> +}
> +
> +power_seq *power_seq_build(struct device *dev, power_seq_resources *ress,
> + platform_power_seq *pseq)
> +{
> + struct power_seq_step *seq = NULL, *ret;
> + struct power_seq_resource *res;
> + int cpt, err;
> +
> + /* first pass to count the number of steps to allocate */
> + for (cpt = 0; pseq[cpt].type != POWER_SEQ_STOP; cpt++);
Wouldn't it be easier to pass around the number of steps in the sequence
instead of having to count in various places? This would be more along
the lines of how struct platform_device defines associated resources.
> +
> + if (!cpt)
> + return seq;
Perhaps this should return an error-code as well? I find it nice to not
have to handle NULL specially when using ERR_PTR et al.
> +
> + /* 1 more for the STOP step */
> + ret = seq = devm_kzalloc(dev, sizeof(*seq) * (cpt + 1), GFP_KERNEL);
> + if (!seq)
> + return ERR_PTR(-ENOMEM);
> +
> + for (; pseq->type != POWER_SEQ_STOP; pseq++, seq++) {
> + /* create resource node if not referenced already */
> + if (!(res = power_seq_find_resource(ress, pseq))) {
> + res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
> + if (!res)
> + return ERR_PTR(-ENOMEM);
> + res->type = pseq->type;
> +
> + if (res->type == POWER_SEQ_GPIO)
> + res->gpio = pseq->gpio;
> + else
> + res->id = pseq->id;
> +
> + if ((err = power_seq_allocate_resource(dev, res)) < 0)
> + return ERR_PTR(err);
> +
> + list_add(&res->list, ress);
> + }
> + seq->resource = res;
> + memcpy(&seq->params, &pseq->params, sizeof(seq->params));
> + }
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(power_seq_build);
> +
> +void power_seq_free_resources(power_seq_resources *ress) {
The brace needs to go on a line by itself.
> + struct power_seq_resource *res;
> +
> +#ifdef CONFIG_PWM
> + list_for_each_entry(res, ress, list) {
> + if (res->type == POWER_SEQ_PWM)
> + pwm_put(res->pwm);
> + }
> +#endif
> +}
> +EXPORT_SYMBOL_GPL(power_seq_free_resources);
> +
> +MODULE_AUTHOR("Alexandre Courbot <acourbot@nvidia.com>");
> +MODULE_DESCRIPTION("Runtime Interpreted Power Sequences");
> +MODULE_LICENSE("GPL");
> diff --git a/include/linux/power_seq.h b/include/linux/power_seq.h
> new file mode 100644
> index 0000000..da0593a
> --- /dev/null
> +++ b/include/linux/power_seq.h
> @@ -0,0 +1,139 @@
> +/*
> + * power_seq.h
> + *
> + * Simple interpreter for defining power sequences as platform data or device
> + * tree properties. Initially designed for use with backlight drivers.
> + *
> + * Power sequences are designed to replace the callbacks typically used in
> + * board-specific files that implement board-specific power sequences of devices
> + * such as backlights. A power sequence is an array of resources (which can a
> + * regulator, a GPIO, a PWM, ...) with an action to perform on it (enable or
> + * disable) and optional pre and post step delays. By having them interpreted
> + * instead of arbitrarily executed, it is possible to describe these in the
> + * device tree and thus remove board-specific code from the kernel.
> + *
> + * Author: Alexandre Courbot <acourbot@nvidia.com>
> + *
> + * Copyright (c) 2012 NVIDIA Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
> + *
> + */
> +
> +#ifndef __LINUX_POWER_SEQ_H
> +#define __LINUX_POWER_SEQ_H
> +
> +#include <linux/types.h>
> +
> +struct device;
> +struct regulator;
> +struct pwm_device;
> +struct device_node;
> +
> +/**
> + * The different kinds of resources that can be controlled during the sequences.
> + */
> +typedef enum {
> + POWER_SEQ_STOP = 0,
> + POWER_SEQ_REGULATOR,
> + POWER_SEQ_PWM,
> + POWER_SEQ_GPIO,
> + POWER_SEQ_MAX,
> +} power_res_type;
Maybe the prefix power_seq should be used here as well, so:
power_seq_res_type.
> +
> +struct power_seq_resource {
> + power_res_type type;
> + /* name to resolve for resources with a name (regulator, pwm) */
> + const char *id;
> + /* resolved resource */
> + union {
> + struct regulator *regulator;
> + struct pwm_device *pwm;
> + int gpio;
> + };
> + /* used to maintain the list of resources used by the driver */
> + struct list_head list;
> +};
> +typedef struct list_head power_seq_resources;
No type definitions like this, please. Also, why define this particular
type globally?
> +
> +struct power_step_params {
> + /* enable the resource if 1, disable if 0 */
> + bool enable;
> + /* delay (in ms) to wait before executing the step */
> + int pre_delay;
> + /* delay (in ms) to wait after executing the step */
> + int post_delay;
unsigned int for the delays?
> +};
> +
> +/**
> + * Platform definition of power sequences. A sequence is an array of these,
> + * terminated by a STOP instance.
> + */
> +struct platform_power_seq_step {
> + power_res_type type;
> + union {
> + /* Used by REGULATOR and PWM types to name the resource */
> + const char *id;
> + /* Used by GPIO */
> + int gpio;
> + };
> + struct power_step_params params;
> +};
> +typedef struct platform_power_seq_step platform_power_seq;
Why are the parameters kept in a separate structure? What are the
disadvantages of keeping the in the sequence step structure directly?
> +
> +/**
> + * Power sequence steps resolved against their resource. Built by
> + * power_seq_build and used to run the sequence.
> + */
> +struct power_seq_step {
> + struct power_seq_resource *resource;
> + struct power_step_params params;
> +};
> +typedef struct power_seq_step power_seq;
Would it make sense to make the struct power_seq opaque? I don't see why
anyone but the power_seq code should access the internals. For resource
managing it might also be easier to separate struct power_seq_step and
struct power_seq, making the power_seq basically something like:
struct power_seq {
struct power_seq_step *steps;
unsigned int num_steps;
};
Perhaps a name field can be included for diagnostic purposes.
> +
> +#ifdef CONFIG_OF
> +/**
> + * Build a platform data sequence from a device tree node. Memory for the
> + * sequence is allocated using devm_kzalloc on dev.
> + */
> +platform_power_seq *of_parse_power_seq(struct device *dev,
> + struct device_node *node);
> +#else
> +platform_power_seq *of_parse_power_seq(struct device *dev,
> + struct device_node *node)
> +{
> + return NULL;
> +}
> +#endif
> +
> +/**
> + * Build a runnable power sequence from platform data, and add the resources
> + * it uses into ress. Memory for the sequence is allocated using devm_kzalloc
> + * on dev.
> + */
> +power_seq *power_seq_build(struct device *dev, power_seq_resources *ress,
> + platform_power_seq *pseq);
I already mentioned this above: I fail to see why the ress parameter is
needed here. It is an internal implementation detail of the power
sequence code. Maybe a better place would be to include it within the
struct power_seq.
> +/**
> + * Free all the resources previously allocated by power_seq_allocate_resources.
> + */
> +void power_seq_free_resources(power_seq_resources *ress);
> +
> +/**
> + * Run the given power sequence. Returns 0 on success, error code in case of
> + * failure.
> + */
> +int power_seq_run(struct device *dev, power_seq *seq);
I think the API is too fine grained here. From a user's point of view,
I'd expect a sequence like this:
seq = power_seq_build(dev, sequence);
...
power_seq_run(seq);
...
power_seq_free(seq);
Perhaps with managed variants where the power_seq_free() is executed
automatically:
seq = devm_power_seq_build(dev, sequence);
...
power_seq_run(seq);
Generally I really like where this is going.
Thierry
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^ permalink raw reply
* Re: [PATCH 1/3] Move FIMD register headers to include/video/
From: Leela Krishna Amudala @ 2012-07-30 11:28 UTC (permalink / raw)
To: Jingoo Han
Cc: linux-arm-kernel, linux-samsung-soc, dri-devel, linux-fbdev,
ben-linux, inki.dae, kgene.kim, joshi, Marek Szyprowski
In-Reply-To: <000001cd6e30$da849520$8f8dbf60$%han@samsung.com>
Hello Jingoo Han,
On Mon, Jul 30, 2012 at 2:23 PM, Jingoo Han <jg1.han@samsung.com> wrote:
> On Monday, July 30, 2012 5:45 PM, Leela Krishna Amudala wrote:
>>
>> Moved the contents of regs-fb-v4.h and regs-fb.h from arch side
>> to include/video/samsung_fimd.h
>>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> ---
>> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 159 -------
>> arch/arm/plat-samsung/include/plat/regs-fb.h | 403 -----------------
>> include/video/samsung_fimd.h | 533 +++++++++++++++++++++++
>> 3 files changed, 533 insertions(+), 562 deletions(-)
>> delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h
>> create mode 100644 include/video/samsung_fimd.h
>>
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-
>> fb-v4.h
>> deleted file mode 100644
>> index 4c3647f..0000000
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> +++ /dev/null
>> @@ -1,159 +0,0 @@
>> -/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h
>> - *
>> - * Copyright 2008 Openmoko, Inc.
>> - * Copyright 2008 Simtec Electronics
>> - * http://armlinux.simtec.co.uk/
>> - * Ben Dooks <ben@simtec.co.uk>
>> - *
>> - * S3C64XX - new-style framebuffer register definitions
>> - *
>> - * This is the register set for the new style framebuffer interface
>> - * found from the S3C2443 onwards and specifically the S3C64XX series
>> - * S3C6400 and S3C6410.
>> - *
>> - * The file contains the cpu specific items which change between whichever
>> - * architecture is selected. See <plat/regs-fb.h> for the core definitions
>> - * that are the same.
>> - *
>> - * This program is free software; you can redistribute it and/or modify
>> - * it under the terms of the GNU General Public License version 2 as
>> - * published by the Free Software Foundation.
>> -*/
>> -
>> -/* include the core definitions here, in case we really do need to
>> - * override them at a later date.
>> -*/
>> -
>> -#include <plat/regs-fb.h>
>> -
>> -#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
>> -#define VIDCON1_FSTATUS_EVEN (1 << 15)
>> -
>> -/* Video timing controls */
>> -#define VIDTCON0 (0x10)
>> -#define VIDTCON1 (0x14)
>> -#define VIDTCON2 (0x18)
>> -
>> -/* Window position controls */
>> -
>> -#define WINCON(_win) (0x20 + ((_win) * 4))
>> -
>> -/* OSD1 and OSD4 do not have register D */
>> -
>> -#define VIDOSD_BASE (0x40)
>> -
>> -#define VIDINTCON0 (0x130)
>> -
>> -/* WINCONx */
>> -
>> -#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
>> -#define WINCONx_CSCWIDTH_SHIFT (26)
>> -#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
>> -#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
>> -
>> -#define WINCONx_ENLOCAL (1 << 22)
>> -#define WINCONx_BUFSTATUS (1 << 21)
>> -#define WINCONx_BUFSEL (1 << 20)
>> -#define WINCONx_BUFAUTOEN (1 << 19)
>> -#define WINCONx_YCbCr (1 << 13)
>> -
>> -#define WINCON1_LOCALSEL_CAMIF (1 << 23)
>> -
>> -#define WINCON2_LOCALSEL_CAMIF (1 << 23)
>> -#define WINCON2_BLD_PIX (1 << 6)
>> -
>> -#define WINCON2_ALPHA_SEL (1 << 1)
>> -#define WINCON2_BPPMODE_MASK (0xf << 2)
>> -#define WINCON2_BPPMODE_SHIFT (2)
>> -#define WINCON2_BPPMODE_1BPP (0x0 << 2)
>> -#define WINCON2_BPPMODE_2BPP (0x1 << 2)
>> -#define WINCON2_BPPMODE_4BPP (0x2 << 2)
>> -#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
>> -#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
>> -#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
>> -#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
>> -#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
>> -#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
>> -#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
>> -#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
>> -#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
>> -#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
>> -#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
>> -
>> -#define WINCON3_BLD_PIX (1 << 6)
>> -
>> -#define WINCON3_ALPHA_SEL (1 << 1)
>> -#define WINCON3_BPPMODE_MASK (0xf << 2)
>> -#define WINCON3_BPPMODE_SHIFT (2)
>> -#define WINCON3_BPPMODE_1BPP (0x0 << 2)
>> -#define WINCON3_BPPMODE_2BPP (0x1 << 2)
>> -#define WINCON3_BPPMODE_4BPP (0x2 << 2)
>> -#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
>> -#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
>> -#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
>> -#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
>> -#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
>> -#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
>> -#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
>> -#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
>> -#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
>> -#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
>> -
>> -#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
>> -#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
>> -#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
>> -
>> -#define DITHMODE (0x170)
>> -#define WINxMAP(_win) (0x180 + ((_win) * 4))
>> -
>> -
>> -#define DITHMODE_R_POS_MASK (0x3 << 5)
>> -#define DITHMODE_R_POS_SHIFT (5)
>> -#define DITHMODE_R_POS_8BIT (0x0 << 5)
>> -#define DITHMODE_R_POS_6BIT (0x1 << 5)
>> -#define DITHMODE_R_POS_5BIT (0x2 << 5)
>> -
>> -#define DITHMODE_G_POS_MASK (0x3 << 3)
>> -#define DITHMODE_G_POS_SHIFT (3)
>> -#define DITHMODE_G_POS_8BIT (0x0 << 3)
>> -#define DITHMODE_G_POS_6BIT (0x1 << 3)
>> -#define DITHMODE_G_POS_5BIT (0x2 << 3)
>> -
>> -#define DITHMODE_B_POS_MASK (0x3 << 1)
>> -#define DITHMODE_B_POS_SHIFT (1)
>> -#define DITHMODE_B_POS_8BIT (0x0 << 1)
>> -#define DITHMODE_B_POS_6BIT (0x1 << 1)
>> -#define DITHMODE_B_POS_5BIT (0x2 << 1)
>> -
>> -#define DITHMODE_DITH_EN (1 << 0)
>> -
>> -#define WPALCON (0x1A0)
>> -
>> -/* Palette control */
>> -/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
>> - * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
>> -#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
>> -#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
>> -#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
>> -
>> -
>> -/* Notes on per-window bpp settings
>> - *
>> - * Value Win0 Win1 Win2 Win3 Win 4
>> - * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
>> - * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
>> - * 0010 4(P) 4(P) 4(P) 4(P) -none-
>> - * 0011 8(P) 8(P) -none- -none- -none-
>> - * 0100 -none- 8(A232) 8(A232) -none- -none-
>> - * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
>> - * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
>> - * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
>> - * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
>> - * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
>> - * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
>> - * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
>> - * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
>> - * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
>> - * 1110 -none- -none- -none- -none- -none-
>> - * 1111 -none- -none- -none- -none- -none-
>> -*/
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
>> deleted file mode 100644
>> index 9a78012..0000000
>> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
>> +++ /dev/null
>> @@ -1,403 +0,0 @@
>> -/* arch/arm/plat-samsung/include/plat/regs-fb.h
>> - *
>> - * Copyright 2008 Openmoko, Inc.
>> - * Copyright 2008 Simtec Electronics
>> - * http://armlinux.simtec.co.uk/
>> - * Ben Dooks <ben@simtec.co.uk>
>> - *
>> - * S3C Platform - new-style framebuffer register definitions
>> - *
>> - * This is the register set for the new style framebuffer interface
>> - * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
>> - * S3C64XX series such as the S3C6400 and S3C6410.
>> - *
>> - * The file does not contain the cpu specific items which are based on
>> - * whichever architecture is selected, it only contains the core of the
>> - * register set. See <mach/regs-fb.h> to get the specifics.
>> - *
>> - * Note, we changed to using regs-fb.h as it avoids any clashes with
>> - * the original regs-lcd.h so out of the way of regs-lcd.h as well as
>> - * indicating the newer block is much more than just an LCD interface.
>> - *
>> - * This program is free software; you can redistribute it and/or modify
>> - * it under the terms of the GNU General Public License version 2 as
>> - * published by the Free Software Foundation.
>> -*/
>> -
>> -/* Please do not include this file directly, use <mach/regs-fb.h> to
>> - * ensure all the localised SoC support is included as necessary.
>> -*/
>> -
>> -/* VIDCON0 */
>> -
>> -#define VIDCON0 (0x00)
>> -#define VIDCON0_INTERLACE (1 << 29)
>> -#define VIDCON0_VIDOUT_MASK (0x3 << 26)
>> -#define VIDCON0_VIDOUT_SHIFT (26)
>> -#define VIDCON0_VIDOUT_RGB (0x0 << 26)
>> -#define VIDCON0_VIDOUT_TV (0x1 << 26)
>> -#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
>> -#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
>> -
>> -#define VIDCON0_L1_DATA_MASK (0x7 << 23)
>> -#define VIDCON0_L1_DATA_SHIFT (23)
>> -#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
>> -#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
>> -#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
>> -#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
>> -#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
>> -#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
>> -
>> -#define VIDCON0_L0_DATA_MASK (0x7 << 20)
>> -#define VIDCON0_L0_DATA_SHIFT (20)
>> -#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
>> -#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
>> -#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
>> -#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
>> -#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
>> -#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
>> -
>> -#define VIDCON0_PNRMODE_MASK (0x3 << 17)
>> -#define VIDCON0_PNRMODE_SHIFT (17)
>> -#define VIDCON0_PNRMODE_RGB (0x0 << 17)
>> -#define VIDCON0_PNRMODE_BGR (0x1 << 17)
>> -#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
>> -#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
>> -
>> -#define VIDCON0_CLKVALUP (1 << 16)
>> -#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
>> -#define VIDCON0_CLKVAL_F_SHIFT (6)
>> -#define VIDCON0_CLKVAL_F_LIMIT (0xff)
>> -#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
>> -#define VIDCON0_VLCKFREE (1 << 5)
>> -#define VIDCON0_CLKDIR (1 << 4)
>> -
>> -#define VIDCON0_CLKSEL_MASK (0x3 << 2)
>> -#define VIDCON0_CLKSEL_SHIFT (2)
>> -#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
>> -#define VIDCON0_CLKSEL_LCD (0x1 << 2)
>> -#define VIDCON0_CLKSEL_27M (0x3 << 2)
>> -
>> -#define VIDCON0_ENVID (1 << 1)
>> -#define VIDCON0_ENVID_F (1 << 0)
>> -
>> -#define VIDCON1 (0x04)
>> -#define VIDCON1_LINECNT_MASK (0x7ff << 16)
>> -#define VIDCON1_LINECNT_SHIFT (16)
>> -#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
>> -#define VIDCON1_VSTATUS_MASK (0x3 << 13)
>> -#define VIDCON1_VSTATUS_SHIFT (13)
>> -#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
>> -#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
>> -#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
>> -#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
>> -#define VIDCON1_VCLK_MASK (0x3 << 9)
>> -#define VIDCON1_VCLK_HOLD (0x0 << 9)
>> -#define VIDCON1_VCLK_RUN (0x1 << 9)
>> -
>> -#define VIDCON1_INV_VCLK (1 << 7)
>> -#define VIDCON1_INV_HSYNC (1 << 6)
>> -#define VIDCON1_INV_VSYNC (1 << 5)
>> -#define VIDCON1_INV_VDEN (1 << 4)
>> -
>> -/* VIDCON2 */
>> -
>> -#define VIDCON2 (0x08)
>> -#define VIDCON2_EN601 (1 << 23)
>> -#define VIDCON2_TVFMTSEL_SW (1 << 14)
>> -
>> -#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
>> -#define VIDCON2_TVFMTSEL1_SHIFT (12)
>> -#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> -#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> -#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>> -
>> -#define VIDCON2_ORGYCbCr (1 << 8)
>> -#define VIDCON2_YUVORDCrCb (1 << 7)
>> -
>> -/* PRTCON (S3C6410, S5PC100)
>> - * Might not be present in the S3C6410 documentation,
>> - * but tests prove it's there almost for sure; shouldn't hurt in any case.
>> - */
>> -#define PRTCON (0x0c)
>> -#define PRTCON_PROTECT (1 << 11)
>> -
>> -/* VIDTCON0 */
>> -
>> -#define VIDTCON0_VBPDE_MASK (0xff << 24)
>> -#define VIDTCON0_VBPDE_SHIFT (24)
>> -#define VIDTCON0_VBPDE_LIMIT (0xff)
>> -#define VIDTCON0_VBPDE(_x) ((_x) << 24)
>> -
>> -#define VIDTCON0_VBPD_MASK (0xff << 16)
>> -#define VIDTCON0_VBPD_SHIFT (16)
>> -#define VIDTCON0_VBPD_LIMIT (0xff)
>> -#define VIDTCON0_VBPD(_x) ((_x) << 16)
>> -
>> -#define VIDTCON0_VFPD_MASK (0xff << 8)
>> -#define VIDTCON0_VFPD_SHIFT (8)
>> -#define VIDTCON0_VFPD_LIMIT (0xff)
>> -#define VIDTCON0_VFPD(_x) ((_x) << 8)
>> -
>> -#define VIDTCON0_VSPW_MASK (0xff << 0)
>> -#define VIDTCON0_VSPW_SHIFT (0)
>> -#define VIDTCON0_VSPW_LIMIT (0xff)
>> -#define VIDTCON0_VSPW(_x) ((_x) << 0)
>> -
>> -/* VIDTCON1 */
>> -
>> -#define VIDTCON1_VFPDE_MASK (0xff << 24)
>> -#define VIDTCON1_VFPDE_SHIFT (24)
>> -#define VIDTCON1_VFPDE_LIMIT (0xff)
>> -#define VIDTCON1_VFPDE(_x) ((_x) << 24)
>> -
>> -#define VIDTCON1_HBPD_MASK (0xff << 16)
>> -#define VIDTCON1_HBPD_SHIFT (16)
>> -#define VIDTCON1_HBPD_LIMIT (0xff)
>> -#define VIDTCON1_HBPD(_x) ((_x) << 16)
>> -
>> -#define VIDTCON1_HFPD_MASK (0xff << 8)
>> -#define VIDTCON1_HFPD_SHIFT (8)
>> -#define VIDTCON1_HFPD_LIMIT (0xff)
>> -#define VIDTCON1_HFPD(_x) ((_x) << 8)
>> -
>> -#define VIDTCON1_HSPW_MASK (0xff << 0)
>> -#define VIDTCON1_HSPW_SHIFT (0)
>> -#define VIDTCON1_HSPW_LIMIT (0xff)
>> -#define VIDTCON1_HSPW(_x) ((_x) << 0)
>> -
>> -#define VIDTCON2 (0x18)
>> -#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
>> -#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
>> -#define VIDTCON2_LINEVAL_SHIFT (11)
>> -#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
>> -#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
>> -
>> -#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
>> -#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
>> -#define VIDTCON2_HOZVAL_SHIFT (0)
>> -#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
>> -#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
>> -
>> -/* WINCONx */
>> -
>> -
>> -#define WINCONx_BITSWP (1 << 18)
>> -#define WINCONx_BYTSWP (1 << 17)
>> -#define WINCONx_HAWSWP (1 << 16)
>> -#define WINCONx_WSWP (1 << 15)
>> -#define WINCONx_BURSTLEN_MASK (0x3 << 9)
>> -#define WINCONx_BURSTLEN_SHIFT (9)
>> -#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
>> -#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
>> -#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
>> -
>> -#define WINCONx_ENWIN (1 << 0)
>> -#define WINCON0_BPPMODE_MASK (0xf << 2)
>> -#define WINCON0_BPPMODE_SHIFT (2)
>> -#define WINCON0_BPPMODE_1BPP (0x0 << 2)
>> -#define WINCON0_BPPMODE_2BPP (0x1 << 2)
>> -#define WINCON0_BPPMODE_4BPP (0x2 << 2)
>> -#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
>> -#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
>> -#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
>> -#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
>> -#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>> -
>> -#define WINCON1_BLD_PIX (1 << 6)
>> -
>> -#define WINCON1_ALPHA_SEL (1 << 1)
>> -#define WINCON1_BPPMODE_MASK (0xf << 2)
>> -#define WINCON1_BPPMODE_SHIFT (2)
>> -#define WINCON1_BPPMODE_1BPP (0x0 << 2)
>> -#define WINCON1_BPPMODE_2BPP (0x1 << 2)
>> -#define WINCON1_BPPMODE_4BPP (0x2 << 2)
>> -#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
>> -#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
>> -#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
>> -#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
>> -#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
>> -#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
>> -#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
>> -#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
>> -#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
>> -#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
>> -#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
>> -#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
>> -
>> -/* S5PV210 */
>> -#define SHADOWCON (0x34)
>> -#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
>> -/* DMA channels (all windows) */
>> -#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
>> -/* Local input channels (windows 0-2) */
>> -#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
>> -
>> -#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
>> -#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
>> -#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
>> -#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
>> -#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
>> -
>> -#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
>> -#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
>> -#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
>> -#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
>> -#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
>> -
>> -#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
>> -#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
>> -#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
>> -#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
>> -#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
>> -
>> -#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
>> -#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
>> -#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
>> -#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
>> -#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
>> -
>> -/* For VIDOSD[1..4]C */
>> -#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
>> -#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
>> -#define VIDISD14C_ALPHA0_G_SHIFT (16)
>> -#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
>> -#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
>> -#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
>> -#define VIDISD14C_ALPHA0_B_SHIFT (12)
>> -#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
>> -#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
>> -#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
>> -#define VIDISD14C_ALPHA1_R_SHIFT (8)
>> -#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
>> -#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
>> -#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
>> -#define VIDISD14C_ALPHA1_G_SHIFT (4)
>> -#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
>> -#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
>> -#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
>> -#define VIDISD14C_ALPHA1_B_SHIFT (0)
>> -#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
>> -#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
>> -
>> -/* Video buffer addresses */
>> -#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
>> -#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
>> -#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
>> -#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
>> -#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
>> -
>> -#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
>> -#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
>> -#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
>> -#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
>> -#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
>> -
>> -#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
>> -#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
>> -#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
>> -#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
>> -#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
>> -
>> -/* Interrupt controls and status */
>> -
>> -#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
>> -#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
>> -#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
>> -#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
>> -
>> -#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
>> -#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
>> -#define VIDINTCON0_INT_I80IFDONE (1 << 17)
>> -
>> -#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
>> -#define VIDINTCON0_FRAMESEL0_SHIFT (15)
>> -#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
>> -#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
>> -#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
>> -#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
>> -
>> -#define VIDINTCON0_FRAMESEL1 (1 << 13)
>> -#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
>> -#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
>> -#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
>> -#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
>> -#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
>> -
>> -#define VIDINTCON0_INT_FRAME (1 << 12)
>> -#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
>> -#define VIDINTCON0_FIFIOSEL_SHIFT (5)
>> -#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
>> -#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
>> -
>> -#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
>> -#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
>> -#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
>> -#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
>> -#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
>> -#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
>> -#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
>> -
>> -#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
>> -#define VIDINTCON0_INT_FIFO_SHIFT (0)
>> -#define VIDINTCON0_INT_ENABLE (1 << 0)
>> -
>> -#define VIDINTCON1 (0x134)
>> -#define VIDINTCON1_INT_I180 (1 << 2)
>> -#define VIDINTCON1_INT_FRAME (1 << 1)
>> -#define VIDINTCON1_INT_FIFO (1 << 0)
>> -
>> -/* Window colour-key control registers */
>> -#define WKEYCON (0x140) /* 6410,V210 */
>> -
>> -#define WKEYCON0 (0x00)
>> -#define WKEYCON1 (0x04)
>> -
>> -#define WxKEYCON0_KEYBL_EN (1 << 26)
>> -#define WxKEYCON0_KEYEN_F (1 << 25)
>> -#define WxKEYCON0_DIRCON (1 << 24)
>> -#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
>> -#define WxKEYCON0_COMPKEY_SHIFT (0)
>> -#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
>> -#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
>> -#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
>> -#define WxKEYCON1_COLVAL_SHIFT (0)
>> -#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
>> -#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
>> -
>> -
>> -/* Window blanking (MAP) */
>> -
>> -#define WINxMAP_MAP (1 << 24)
>> -#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
>> -#define WINxMAP_MAP_COLOUR_SHIFT (0)
>> -#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
>> -#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
>> -
>> -#define WPALCON_PAL_UPDATE (1 << 9)
>> -#define WPALCON_W1PAL_MASK (0x7 << 3)
>> -#define WPALCON_W1PAL_SHIFT (3)
>> -#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
>> -#define WPALCON_W1PAL_24BPP (0x1 << 3)
>> -#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
>> -#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
>> -#define WPALCON_W1PAL_18BPP (0x4 << 3)
>> -#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
>> -#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
>> -
>> -#define WPALCON_W0PAL_MASK (0x7 << 0)
>> -#define WPALCON_W0PAL_SHIFT (0)
>> -#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
>> -#define WPALCON_W0PAL_24BPP (0x1 << 0)
>> -#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
>> -#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
>> -#define WPALCON_W0PAL_18BPP (0x4 << 0)
>> -#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
>> -#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>> -
>> -/* Blending equation control */
>> -#define BLENDCON (0x260)
>> -#define BLENDCON_NEW_MASK (1 << 0)
>> -#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
>> -#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>> -
>> diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
>> new file mode 100644
>> index 0000000..1b5ff4c
>> --- /dev/null
>> +++ b/include/video/samsung_fimd.h
>> @@ -0,0 +1,533 @@
>> +/* include/video/samsung_fimd.h
>> + *
>> + * Copyright 2008 Openmoko, Inc.
>> + * Copyright 2008 Simtec Electronics
>> + * http://armlinux.simtec.co.uk/
>> + * Ben Dooks <ben@simtec.co.uk>
>> + *
>> + * S3C Platform - new-style fimd and framebuffer register definitions
>> + *
>> + * This is the register set for the fimd and new style framebuffer interface
>> + * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
>> + * S3C64XX series such as the S3C6400 and S3C6410.
>> + *
>> + * The file does not contain the cpu specific items which are based on
>> + * whichever architecture is selected, it only contains the core of the
>> + * register set. See <mach/regs-fb.h> to get the specifics.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +/* VIDCON0 */
>> +
>> +#define VIDCON0 (0x00)
>> +#define VIDCON0_INTERLACE (1 << 29)
>> +#define VIDCON0_VIDOUT_MASK (0x3 << 26)
>> +#define VIDCON0_VIDOUT_SHIFT (26)
>> +#define VIDCON0_VIDOUT_RGB (0x0 << 26)
>> +#define VIDCON0_VIDOUT_TV (0x1 << 26)
>> +#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
>> +#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
>> +
>> +#define VIDCON0_L1_DATA_MASK (0x7 << 23)
>> +#define VIDCON0_L1_DATA_SHIFT (23)
>> +#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
>> +#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
>> +#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
>> +#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
>> +#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
>> +#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
>> +
>> +#define VIDCON0_L0_DATA_MASK (0x7 << 20)
>> +#define VIDCON0_L0_DATA_SHIFT (20)
>> +#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
>> +#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
>> +#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
>> +#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
>> +#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
>> +#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
>> +
>> +#define VIDCON0_PNRMODE_MASK (0x3 << 17)
>> +#define VIDCON0_PNRMODE_SHIFT (17)
>> +#define VIDCON0_PNRMODE_RGB (0x0 << 17)
>> +#define VIDCON0_PNRMODE_BGR (0x1 << 17)
>> +#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
>> +#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
>> +
>> +#define VIDCON0_CLKVALUP (1 << 16)
>> +#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
>> +#define VIDCON0_CLKVAL_F_SHIFT (6)
>> +#define VIDCON0_CLKVAL_F_LIMIT (0xff)
>> +#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
>> +#define VIDCON0_VLCKFREE (1 << 5)
>> +#define VIDCON0_CLKDIR (1 << 4)
>> +
>> +#define VIDCON0_CLKSEL_MASK (0x3 << 2)
>> +#define VIDCON0_CLKSEL_SHIFT (2)
>> +#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
>> +#define VIDCON0_CLKSEL_LCD (0x1 << 2)
>> +#define VIDCON0_CLKSEL_27M (0x3 << 2)
>> +
>> +#define VIDCON0_ENVID (1 << 1)
>> +#define VIDCON0_ENVID_F (1 << 0)
>> +
>> +#define VIDCON1 (0x04)
>> +#define VIDCON1_LINECNT_MASK (0x7ff << 16)
>> +#define VIDCON1_LINECNT_SHIFT (16)
>> +#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
>> +#define VIDCON1_VSTATUS_MASK (0x3 << 13)
>> +#define VIDCON1_VSTATUS_SHIFT (13)
>> +#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
>> +#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
>> +#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
>> +#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
>> +#define VIDCON1_VCLK_MASK (0x3 << 9)
>> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
>> +#define VIDCON1_VCLK_RUN (0x1 << 9)
>> +
>> +#define VIDCON1_INV_VCLK (1 << 7)
>> +#define VIDCON1_INV_HSYNC (1 << 6)
>> +#define VIDCON1_INV_VSYNC (1 << 5)
>> +#define VIDCON1_INV_VDEN (1 << 4)
>> +
>> +/* VIDCON2 */
>> +
>> +#define VIDCON2 (0x08)
>> +#define VIDCON2_EN601 (1 << 23)
>> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
>> +
>> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
>> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
>> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
>> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
>> +
>> +#define VIDCON2_ORGYCbCr (1 << 8)
>> +#define VIDCON2_YUVORDCrCb (1 << 7)
>> +
>> +/* PRTCON (S3C6410, S5PC100)
>> + * Might not be present in the S3C6410 documentation,
>> + * but tests prove it's there almost for sure; shouldn't hurt in any case.
>> + */
>> +#define PRTCON (0x0c)
>> +#define PRTCON_PROTECT (1 << 11)
>> +
>> +/* VIDTCON0 */
>> +
>> +#define VIDTCON0_VBPDE_MASK (0xff << 24)
>> +#define VIDTCON0_VBPDE_SHIFT (24)
>> +#define VIDTCON0_VBPDE_LIMIT (0xff)
>> +#define VIDTCON0_VBPDE(_x) ((_x) << 24)
>> +
>> +#define VIDTCON0_VBPD_MASK (0xff << 16)
>> +#define VIDTCON0_VBPD_SHIFT (16)
>> +#define VIDTCON0_VBPD_LIMIT (0xff)
>> +#define VIDTCON0_VBPD(_x) ((_x) << 16)
>> +
>> +#define VIDTCON0_VFPD_MASK (0xff << 8)
>> +#define VIDTCON0_VFPD_SHIFT (8)
>> +#define VIDTCON0_VFPD_LIMIT (0xff)
>> +#define VIDTCON0_VFPD(_x) ((_x) << 8)
>> +
>> +#define VIDTCON0_VSPW_MASK (0xff << 0)
>> +#define VIDTCON0_VSPW_SHIFT (0)
>> +#define VIDTCON0_VSPW_LIMIT (0xff)
>> +#define VIDTCON0_VSPW(_x) ((_x) << 0)
>> +
>> +/* VIDTCON1 */
>> +
>> +#define VIDTCON1_VFPDE_MASK (0xff << 24)
>> +#define VIDTCON1_VFPDE_SHIFT (24)
>> +#define VIDTCON1_VFPDE_LIMIT (0xff)
>> +#define VIDTCON1_VFPDE(_x) ((_x) << 24)
>> +
>> +#define VIDTCON1_HBPD_MASK (0xff << 16)
>> +#define VIDTCON1_HBPD_SHIFT (16)
>> +#define VIDTCON1_HBPD_LIMIT (0xff)
>> +#define VIDTCON1_HBPD(_x) ((_x) << 16)
>> +
>> +#define VIDTCON1_HFPD_MASK (0xff << 8)
>> +#define VIDTCON1_HFPD_SHIFT (8)
>> +#define VIDTCON1_HFPD_LIMIT (0xff)
>> +#define VIDTCON1_HFPD(_x) ((_x) << 8)
>> +
>> +#define VIDTCON1_HSPW_MASK (0xff << 0)
>> +#define VIDTCON1_HSPW_SHIFT (0)
>> +#define VIDTCON1_HSPW_LIMIT (0xff)
>> +#define VIDTCON1_HSPW(_x) ((_x) << 0)
>> +
>> +#define VIDTCON2 (0x18)
>> +#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
>> +#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
>> +#define VIDTCON2_LINEVAL_SHIFT (11)
>> +#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
>> +#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
>> +
>> +#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
>> +#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
>> +#define VIDTCON2_HOZVAL_SHIFT (0)
>> +#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
>> +#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
>> +
>> +/* WINCONx */
>> +
>> +
>> +#define WINCONx_BITSWP (1 << 18)
>> +#define WINCONx_BYTSWP (1 << 17)
>> +#define WINCONx_HAWSWP (1 << 16)
>> +#define WINCONx_WSWP (1 << 15)
>> +#define WINCONx_BURSTLEN_MASK (0x3 << 9)
>> +#define WINCONx_BURSTLEN_SHIFT (9)
>> +#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
>> +#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
>> +#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
>> +
>> +#define WINCONx_ENWIN (1 << 0)
>> +#define WINCON0_BPPMODE_MASK (0xf << 2)
>> +#define WINCON0_BPPMODE_SHIFT (2)
>> +#define WINCON0_BPPMODE_1BPP (0x0 << 2)
>> +#define WINCON0_BPPMODE_2BPP (0x1 << 2)
>> +#define WINCON0_BPPMODE_4BPP (0x2 << 2)
>> +#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
>> +#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
>> +#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
>> +#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
>> +#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
>> +
>> +#define WINCON1_BLD_PIX (1 << 6)
>> +
>> +#define WINCON1_ALPHA_SEL (1 << 1)
>> +#define WINCON1_BPPMODE_MASK (0xf << 2)
>> +#define WINCON1_BPPMODE_SHIFT (2)
>> +#define WINCON1_BPPMODE_1BPP (0x0 << 2)
>> +#define WINCON1_BPPMODE_2BPP (0x1 << 2)
>> +#define WINCON1_BPPMODE_4BPP (0x2 << 2)
>> +#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
>> +#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
>> +#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
>> +#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
>> +#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
>> +#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
>> +#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
>> +#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
>> +#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
>> +#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
>> +#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
>> +#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
>> +
>> +/* S5PV210 */
>> +#define SHADOWCON (0x34)
>> +#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
>> +/* DMA channels (all windows) */
>> +#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
>> +/* Local input channels (windows 0-2) */
>> +#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
>> +
>> +#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
>> +#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
>> +#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
>> +#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
>> +#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
>> +
>> +#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
>> +#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
>> +#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
>> +#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
>> +#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
>> +
>> +#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
>> +#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
>> +#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
>> +#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
>> +#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
>> +
>> +#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
>> +#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
>> +#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
>> +#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
>> +#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
>> +
>> +/* For VIDOSD[1..4]C */
>> +#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
>> +#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
>> +#define VIDISD14C_ALPHA0_G_SHIFT (16)
>> +#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
>> +#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
>> +#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
>> +#define VIDISD14C_ALPHA0_B_SHIFT (12)
>> +#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
>> +#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
>> +#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
>> +#define VIDISD14C_ALPHA1_R_SHIFT (8)
>> +#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
>> +#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
>> +#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
>> +#define VIDISD14C_ALPHA1_G_SHIFT (4)
>> +#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
>> +#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
>> +#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
>> +#define VIDISD14C_ALPHA1_B_SHIFT (0)
>> +#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
>> +#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
>> +
>> +/* Video buffer addresses */
>> +#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
>> +#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
>> +#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
>> +#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
>> +#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
>> +
>> +#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
>> +#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
>> +#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
>> +#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
>> +#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
>> +
>> +#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
>> +#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
>> +#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
>> +#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
>> +#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
>> +
>> +/* Interrupt controls and status */
>> +
>> +#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
>> +#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
>> +#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
>> +#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
>> +
>> +#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
>> +#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
>> +#define VIDINTCON0_INT_I80IFDONE (1 << 17)
>> +
>> +#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
>> +#define VIDINTCON0_FRAMESEL0_SHIFT (15)
>> +#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
>> +#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
>> +#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
>> +#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
>> +
>> +#define VIDINTCON0_FRAMESEL1 (1 << 13)
>> +#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
>> +#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
>> +#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
>> +#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
>> +#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
>> +
>> +#define VIDINTCON0_INT_FRAME (1 << 12)
>> +#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
>> +#define VIDINTCON0_FIFIOSEL_SHIFT (5)
>> +#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
>> +#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
>> +
>> +#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
>> +#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
>> +#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
>> +#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
>> +#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
>> +#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
>> +#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
>> +
>> +#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
>> +#define VIDINTCON0_INT_FIFO_SHIFT (0)
>> +#define VIDINTCON0_INT_ENABLE (1 << 0)
>> +
>> +#define VIDINTCON1 (0x134)
>> +#define VIDINTCON1_INT_I180 (1 << 2)
>> +#define VIDINTCON1_INT_FRAME (1 << 1)
>> +#define VIDINTCON1_INT_FIFO (1 << 0)
>> +
>> +/* Window colour-key control registers */
>> +#define WKEYCON (0x140) /* 6410,V210 */
>> +
>> +#define WKEYCON0 (0x00)
>> +#define WKEYCON1 (0x04)
>> +
>> +#define WxKEYCON0_KEYBL_EN (1 << 26)
>> +#define WxKEYCON0_KEYEN_F (1 << 25)
>> +#define WxKEYCON0_DIRCON (1 << 24)
>> +#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
>> +#define WxKEYCON0_COMPKEY_SHIFT (0)
>> +#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
>> +#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
>> +#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
>> +#define WxKEYCON1_COLVAL_SHIFT (0)
>> +#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
>> +#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
>> +
>> +
>> +/* Window blanking (MAP) */
>> +
>> +#define WINxMAP_MAP (1 << 24)
>> +#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
>> +#define WINxMAP_MAP_COLOUR_SHIFT (0)
>> +#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
>> +#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
>> +
>> +#define WPALCON_PAL_UPDATE (1 << 9)
>> +#define WPALCON_W1PAL_MASK (0x7 << 3)
>> +#define WPALCON_W1PAL_SHIFT (3)
>> +#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
>> +#define WPALCON_W1PAL_24BPP (0x1 << 3)
>> +#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
>> +#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
>> +#define WPALCON_W1PAL_18BPP (0x4 << 3)
>> +#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
>> +#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
>> +
>> +#define WPALCON_W0PAL_MASK (0x7 << 0)
>> +#define WPALCON_W0PAL_SHIFT (0)
>> +#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
>> +#define WPALCON_W0PAL_24BPP (0x1 << 0)
>> +#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
>> +#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
>> +#define WPALCON_W0PAL_18BPP (0x4 << 0)
>> +#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
>> +#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
>> +
>> +/* Blending equation control */
>> +#define BLENDCON (0x260)
>> +#define BLENDCON_NEW_MASK (1 << 0)
>> +#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
>> +#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
>> +
>> +#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
>> +#define VIDCON1_FSTATUS_EVEN (1 << 15)
>> +
>> +/* Video timing controls */
>> +#define VIDTCON0 (0x10)
>> +#define VIDTCON1 (0x14)
>> +#define VIDTCON2 (0x18)
>> +
>> +/* Window position controls */
>> +
>> +#define WINCON(_win) (0x20 + ((_win) * 4))
>> +
>> +/* OSD1 and OSD4 do not have register D */
>> +
>> +#define VIDOSD_BASE (0x40)
>> +
>> +#define VIDINTCON0 (0x130)
>> +
>> +/* WINCONx */
>> +
>> +#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
>> +#define WINCONx_CSCWIDTH_SHIFT (26)
>> +#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
>> +#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
>> +
>> +#define WINCONx_ENLOCAL (1 << 22)
>> +#define WINCONx_BUFSTATUS (1 << 21)
>> +#define WINCONx_BUFSEL (1 << 20)
>> +#define WINCONx_BUFAUTOEN (1 << 19)
>> +#define WINCONx_YCbCr (1 << 13)
>> +
>> +#define WINCON1_LOCALSEL_CAMIF (1 << 23)
>> +
>> +#define WINCON2_LOCALSEL_CAMIF (1 << 23)
>> +#define WINCON2_BLD_PIX (1 << 6)
>> +
>> +#define WINCON2_ALPHA_SEL (1 << 1)
>> +#define WINCON2_BPPMODE_MASK (0xf << 2)
>> +#define WINCON2_BPPMODE_SHIFT (2)
>> +#define WINCON2_BPPMODE_1BPP (0x0 << 2)
>> +#define WINCON2_BPPMODE_2BPP (0x1 << 2)
>> +#define WINCON2_BPPMODE_4BPP (0x2 << 2)
>> +#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
>> +#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
>> +#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
>> +#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
>> +#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
>> +#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
>> +#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
>> +#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
>> +#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
>> +#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
>> +#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
>> +
>> +#define WINCON3_BLD_PIX (1 << 6)
>> +
>> +#define WINCON3_ALPHA_SEL (1 << 1)
>> +#define WINCON3_BPPMODE_MASK (0xf << 2)
>> +#define WINCON3_BPPMODE_SHIFT (2)
>> +#define WINCON3_BPPMODE_1BPP (0x0 << 2)
>> +#define WINCON3_BPPMODE_2BPP (0x1 << 2)
>> +#define WINCON3_BPPMODE_4BPP (0x2 << 2)
>> +#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
>> +#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
>> +#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
>> +#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
>> +#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
>> +#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
>> +#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
>> +#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
>> +#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
>> +#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
>> +
>> +#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
>> +#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
>> +#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
>> +
>> +#define DITHMODE (0x170)
>> +#define WINxMAP(_win) (0x180 + ((_win) * 4))
>> +
>> +
>> +#define DITHMODE_R_POS_MASK (0x3 << 5)
>> +#define DITHMODE_R_POS_SHIFT (5)
>> +#define DITHMODE_R_POS_8BIT (0x0 << 5)
>> +#define DITHMODE_R_POS_6BIT (0x1 << 5)
>> +#define DITHMODE_R_POS_5BIT (0x2 << 5)
>> +
>> +#define DITHMODE_G_POS_MASK (0x3 << 3)
>> +#define DITHMODE_G_POS_SHIFT (3)
>> +#define DITHMODE_G_POS_8BIT (0x0 << 3)
>> +#define DITHMODE_G_POS_6BIT (0x1 << 3)
>> +#define DITHMODE_G_POS_5BIT (0x2 << 3)
>> +
>> +#define DITHMODE_B_POS_MASK (0x3 << 1)
>> +#define DITHMODE_B_POS_SHIFT (1)
>> +#define DITHMODE_B_POS_8BIT (0x0 << 1)
>> +#define DITHMODE_B_POS_6BIT (0x1 << 1)
>> +#define DITHMODE_B_POS_5BIT (0x2 << 1)
>> +
>> +#define DITHMODE_DITH_EN (1 << 0)
>> +
>> +#define WPALCON (0x1A0)
>> +
>> +/* Palette control */
>> +/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
>> + * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
>> +#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
>> +#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
>> +#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
>> +
>> +
>> +/* Notes on per-window bpp settings
>> + *
>> + * Value Win0 Win1 Win2 Win3 Win 4
>> + * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
>> + * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
>> + * 0010 4(P) 4(P) 4(P) 4(P) -none-
>> + * 0011 8(P) 8(P) -none- -none- -none-
>> + * 0100 -none- 8(A232) 8(A232) -none- -none-
>> + * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
>> + * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
>> + * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
>> + * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
>> + * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
>> + * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
>> + * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
>> + * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
>> + * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
>> + * 1110 -none- -none- -none- -none- -none-
>> + * 1111 -none- -none- -none- -none- -none-
>> +*/
>> +
>> +/*FIMD V8 REG OFFSET */
>> +#define FIMD_V8_VIDTCON0 (0x20010)
>> +#define FIMD_V8_VIDTCON1 (0x20014)
>> +#define FIMD_V8_VIDTCON2 (0x20018)
>> +#define FIMD_V8_VIDTCON3 (0x2001C)
>> +#define FIMD_V8_VIDCON1 (0x20004)
>
>
> CC'ed Marek.
>
> To Leela Krishna Amudala,
>
> Don't add these definitions for FIMD_V8_xxx registers, which are not related to current "regs-fb-v4.h and regs-fb.h".
> Just "move" and "merge" regs-fb-v4.h and regs-fb.h to one header file, not "add" new definitions.
> If you want to add these definitions, please make new patch for this.
>
Will do it in the suggested way,
> Also, "#define FIMD_V8_xxx" is ugly.
> I think that there is better way.
> Please, find other way.
>
>
I used FIMD_V8_xxx instead of EXYNOS5_FIMD_*, because in future,
there is a possibility that version 8 FIMD can be used in other
application processors also.
Thanks for reviewing the patch.
Best Wishes,
Leela Krishna.
>> --
>> 1.7.0.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/3] Move FIMD register headers to include/video/
From: Leela Krishna Amudala @ 2012-07-30 11:17 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: linux-arm-kernel, linux-samsung-soc, dri-devel, linux-fbdev,
ben-linux, inki.dae, kgene.kim, joshi, Jingoo Han,
Marek Szyprowski
In-Reply-To: <50164A8B.3070907@samsung.com>
Hello Sylwester,
On Mon, Jul 30, 2012 at 2:19 PM, Sylwester Nawrocki
<s.nawrocki@samsung.com> wrote:
>
> Hi,
>
> On 07/30/2012 10:45 AM, Leela Krishna Amudala wrote:
> > Moved the contents of regs-fb-v4.h and regs-fb.h from arch side
> > to include/video/samsung_fimd.h
> >
> > Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> > ---
> > arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 159 -------
> > arch/arm/plat-samsung/include/plat/regs-fb.h | 403 -----------------
> > include/video/samsung_fimd.h | 533 +++++++++++++++++++++++
> > 3 files changed, 533 insertions(+), 562 deletions(-)
> > delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> > delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h
> > create mode 100644 include/video/samsung_fimd.h
>
> Thanks for taking care if this. However you might need to split this
> patch in two, so there is no build and git bisection breakage. In the
> first patch a new header file would be added, then the patch updating
> users of the FIMD headers would be applied, and finally the regs-fb*.h
> files would be removed.
>
> Also it helps to use -M option to git format-patch when creating patches
> that mainly move files.
>
Will do it in the suggested way,
Thanks for reviewing the patch.
> --
>
> Regards,
> Sylwester
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [RFC][PATCH v3 1/3] runtime interpreted power sequences
From: Simon Glass @ 2012-07-30 11:00 UTC (permalink / raw)
To: Alexandre Courbot
Cc: Stephen Warren, Thierry Reding, Grant Likely, Rob Herring,
Greg Kroah-Hartman, Mark Brown, Arnd Bergmann,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <1343390750-3642-2-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Hi,
On Fri, Jul 27, 2012 at 1:05 PM, Alexandre Courbot <acourbot@nvidia.com> wrote:
> Some device drivers (panel backlights especially) need to follow precise
> sequences for powering on and off, involving gpios, regulators, PWMs
> with a precise powering order and delays to respect between each steps.
> These sequences are board-specific, and do not belong to a particular
> driver - therefore they have been performed by board-specific hook
> functions to far.
>
> With the advent of the device tree and of ARM kernels that are not
> board-tied, we cannot rely on these board-specific hooks anymore but
> need a way to implement these sequences in a portable manner. This patch
> introduces a simple interpreter that can execute such power sequences
> encoded either as platform data or within the device tree.
This all looks very reasonable to me, just a few comments.
>
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
> ---
> Documentation/power/power_seq.txt | 120 +++++++++++++++
> drivers/base/Kconfig | 4 +
> drivers/base/Makefile | 1 +
> drivers/base/power_seq.c | 300 ++++++++++++++++++++++++++++++++++++++
> include/linux/power_seq.h | 139 ++++++++++++++++++
> 5 files changed, 564 insertions(+)
> create mode 100644 Documentation/power/power_seq.txt
> create mode 100644 drivers/base/power_seq.c
> create mode 100644 include/linux/power_seq.h
>
> diff --git a/Documentation/power/power_seq.txt b/Documentation/power/power_seq.txt
> new file mode 100644
> index 0000000..aa2ceb5
> --- /dev/null
> +++ b/Documentation/power/power_seq.txt
> @@ -0,0 +1,120 @@
> +Runtime Interpreted Power Sequences
> +-----------------------------------
> +
> +Problem
> +-------
> +One very common board-dependent code is the out-of-driver code that is used to
> +turn a device on or off. For instance, SoC boards very commonly use a GPIO
> +(abstracted to a regulator or not) to control the power supply of a backlight,
> +disabling it when the backlight is not used in order to save power. The GPIO
> +that should be used, however, as well as the exact power sequence that may
> +involve different resources, is board-dependent and thus unknown of the driver.
> +
> +This has been addressed so far by using hooks in the device's platform data that
> +are called whenever the state of the device might reflect a power change. This
> +approach, however, introduces board-dependant code into the kernel and is not
> +compatible with the device tree.
> +
> +The Runtime Interpreted Power Sequences (or power sequences for short) aim at
> +turning this code into platform data or device tree nodes. Power sequences are
> +described using a simple format and run by a simple interpreter whenever needed.
> +This allows to remove the callback mechanism and makes the kernel less
> +board-dependant.
> +
> +Sequences Format
> +----------------
> +Power sequences are a series of sequential steps during which an action is
> +performed on a resource. The supported resources so far are:
> +- GPIOs
> +- Regulators
> +- PWMs
> +
> +Each step designates a resource and the following parameters:
> +- Whether the step should enable or disable the resource,
> +- Delay to wait before performing the action,
> +- Delay to wait after performing the action.
> +
> +Both new resources and parameters can be introduced, but the goal is of course
> +to keep things as simple and compact as possible.
> +
> +The platform data is a simple array of platform_power_seq_step instances, each
> +instance describing a step. The type as well as one of id or gpio members
> +(depending on the type) must be specified. The last step must be of type
> +POWER_SEQ_STOP. Regulator and PWM resources are identified by name. GPIO are
> +identified by number. For example, the following sequence will turn on the
> +"power" regulator of the device, wait 10ms, and set GPIO number 110 to 1:
For the delay, I think milliseconds is reasonable. I suppose there is
no reasonable need for microseconds?
> +
> +struct platform_power_seq_step power_on_seq[] = {
> + {
> + .type = POWER_SEQ_REGULATOR,
> + .id = "power",
> + .params = {
> + .enable = 1,
> + .post_delay = 10,
> + },
> + },
> + {
> + .type = POWER_SEQ_GPIO,
> + .gpio = 110,
> + .params = {
> + .enable = 1,
> + },
> + },
> + {
> + .type = POWER_SEQ_STOP,
> + },
> +};
> +
> +Usage by Drivers and Resources Management
> +-----------------------------------------
> +Power sequences make use of resources that must be properly allocated and
> +managed. The power_seq_build() function takes care of resolving the resources as
> +they are met in the sequence and to allocate them if needed:
> +
> +power_seq *power_seq_build(struct device *dev, power_seq_resources *ress,
> + platform_power_seq *pseq);
> +
> +You will need an instance of power_seq_resources to keep track of the resources
> +that are already allocated. On success, the function returns a devm allocated
> +resolved sequence that is ready to be passed to power_seq_run(). In case of
> +failure, and error code is returned.
> +
> +A resolved power sequence returned by power_seq_build can be run by
> +power_run_run():
> +
> +int power_seq_run(struct device *dev, power_seq *seq);
> +
> +It returns 0 if the sequence has successfully been run, or an error code if a
> +problem occured.
> +
> +Finally, some resources that cannot be allocated through devm need to be freed
> +manually. Therefore, be sure to call power_seq_free_resources() in your device
> +remove function:
> +
> +void power_seq_free_resources(power_seq_resources *ress);
> +
> +Device tree
> +-----------
> +All the same, power sequences can be encoded as device tree nodes. The following
> +properties and nodes are equivalent to the platform data defined previously:
> +
> + power-supply = <&mydevice_reg>;
> + enable-gpio = <&gpio 6 0>;
> +
> + power-on-sequence {
> + regulator@0 {
> + id = "power";
Is there a reason not to put the phandle here, like:
id = <&mydevice_reg>;
(or maybe 'device' instead of id?)
> + enable;
> + post-delay = <10>;
> + };
> + gpio@1 {
> + id = "enable-gpio";
> + enable;
> + };
> + };
> +
> +Note that first, the phandles of the regulator and gpio used in the sequences
> +are defined as properties. Then the sequence references them through the id
> +property of every step. The name of sub-properties defines the type of the step.
> +Valid names are "regulator", "gpio" and "pwm". Steps must be numbered
> +sequentially.
For the regulator and gpio types I think you only have an enable. For
the pwm, what is the intended binding? Is that documented elsewhere?
Also it might be worth mentioning how you get a struct power_seq from
an fdt node, and perhaps given an example of a device which has an
attached node, so we can see how it is referenced from the device
(of_parse_power_seq I think). Do put the sequence inside the device
node or reference it with a phandle?
Finally, should you use typedefs?
Regards,
Simon
^ permalink raw reply
* [PATCH] Fix newport con crashes
From: Thomas Bogendoerfer @ 2012-07-30 10:54 UTC (permalink / raw)
To: linux-mips, linux-fbdev; +Cc: ralf, FlorianSchandinat
Because of commit e84de0c61905030a0fe66b7210b6f1bb7c3e1eab
[MIPS: GIO bus support for SGI IP22/28] newport con is now taking over
console from dummy con, therefore it's necessary to resize the VC to
the correct size to avoid crashes and garbage on console
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
drivers/video/console/newport_con.c | 11 +++++++++--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c
index 6d15966..b05afd0 100644
--- a/drivers/video/console/newport_con.c
+++ b/drivers/video/console/newport_con.c
@@ -327,9 +327,16 @@ out_unmap:
static void newport_init(struct vc_data *vc, int init)
{
- vc->vc_cols = newport_xsize / 8;
- vc->vc_rows = newport_ysize / 16;
+ int cols, rows;
+
+ cols = newport_xsize / 8;
+ rows = newport_ysize / 16;
vc->vc_can_do_color = 1;
+ if (init) {
+ vc->vc_cols = cols;
+ vc->vc_rows = rows;
+ } else
+ vc_resize(vc, cols, rows);
}
static void newport_deinit(struct vc_data *c)
^ permalink raw reply related
* Re: [PATCH 1/3] Move FIMD register headers to include/video/
From: Sylwester Nawrocki @ 2012-07-30 9:09 UTC (permalink / raw)
To: Jingoo Han
Cc: 'Leela Krishna Amudala', linux-arm-kernel,
linux-samsung-soc, dri-devel, linux-fbdev, ben-linux, inki.dae,
kgene.kim, joshi, 'Marek Szyprowski'
In-Reply-To: <000001cd6e30$da849520$8f8dbf60$%han@samsung.com>
Hi,
On 07/30/2012 10:53 AM, Jingoo Han wrote:
>> +/*FIMD V8 REG OFFSET */
>> +#define FIMD_V8_VIDTCON0 (0x20010)
>> +#define FIMD_V8_VIDTCON1 (0x20014)
>> +#define FIMD_V8_VIDTCON2 (0x20018)
>> +#define FIMD_V8_VIDTCON3 (0x2001C)
>> +#define FIMD_V8_VIDCON1 (0x20004)
>
>
> CC'ed Marek.
>
> To Leela Krishna Amudala,
>
> Don't add these definitions for FIMD_V8_xxx registers, which are
> not related to current "regs-fb-v4.h and regs-fb.h".
> Just "move" and "merge" regs-fb-v4.h and regs-fb.h to one header
> file, not "add" new definitions.
> If you want to add these definitions, please make new patch for this.
Good point.
> Also, "#define FIMD_V8_xxx" is ugly.
> I think that there is better way.
> Please, find other way.
Instead of just telling that something is wrong and you don't like it,
perhaps it would be kind to give at least a slight suggestion of what
would have been good enough to your taste...respecting someone else's
time and effort.
So what would you like to see there instead, EXYNOS5_FIMD_* ?
BTW, your e-mails are badly word wrapped, I had to manually correct it.
--
Regards,
Sylwester
^ permalink raw reply
* [PATCH 3/3] driver: Include the modified FIMD header file
From: Leela Krishna Amudala @ 2012-07-30 8:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc
Cc: dri-devel, linux-fbdev, ben-linux, inki.dae, kgene.kim, joshi,
jg1.han
In-Reply-To: <1343637905-17764-1-git-send-email-l.krishna@samsung.com>
The fimd register headers have been moved to include/video/
hence, modifying the driver files accordingly.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +-
drivers/video/s3c-fb.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 29fdbfe..8da90f9 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -20,7 +20,7 @@
#include <linux/pm_runtime.h>
#include <drm/exynos_drm.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include "exynos_drm_drv.h"
#include "exynos_drm_fbdev.h"
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 69bf9d0..1226fdd 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -26,7 +26,7 @@
#include <linux/pm_runtime.h>
#include <mach/map.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <plat/fb.h>
/* This driver will export a number of framebuffer interfaces depending
--
1.7.0.4
^ permalink raw reply related
* [PATCH 2/3] arm: samsung: Include the modified FIMD header file
From: Leela Krishna Amudala @ 2012-07-30 8:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc
Cc: dri-devel, linux-fbdev, ben-linux, inki.dae, kgene.kim, joshi,
jg1.han
In-Reply-To: <1343637905-17764-1-git-send-email-l.krishna@samsung.com>
The fimd register headers have been moved to include/video/
hence, modifying the machine files accordingly.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/mach-exynos/mach-nuri.c | 2 +-
arch/arm/mach-exynos/mach-origen.c | 2 +-
arch/arm/mach-exynos/mach-smdk4x12.c | 2 +-
arch/arm/mach-exynos/mach-smdkv310.c | 2 +-
arch/arm/mach-exynos/mach-universal_c210.c | 2 +-
arch/arm/mach-exynos/setup-fimd0.c | 2 +-
arch/arm/mach-s3c24xx/mach-smdk2416.c | 2 +-
arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-hmt.c | 2 +-
arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-ncp.c | 2 +-
arch/arm/mach-s3c64xx/mach-real6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-smartq5.c | 2 +-
arch/arm/mach-s3c64xx/mach-smartq7.c | 2 +-
arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +-
arch/arm/mach-s5p64x0/mach-smdk6440.c | 2 +-
arch/arm/mach-s5p64x0/mach-smdk6450.c | 2 +-
arch/arm/mach-s5pc100/mach-smdkc100.c | 2 +-
arch/arm/mach-s5pv210/mach-aquila.c | 2 +-
arch/arm/mach-s5pv210/mach-goni.c | 2 +-
arch/arm/mach-s5pv210/mach-smdkv210.c | 2 +-
22 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index f98a83a..573a0c4 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -39,7 +39,7 @@
#include <asm/mach-types.h>
#include <plat/adc.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <plat/regs-serial.h>
#include <plat/cpu.h>
#include <plat/devs.h>
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 5a12dc2..c69707e 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -31,7 +31,7 @@
#include <video/platform_lcd.h>
#include <plat/regs-serial.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/sdhci.h>
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index b26beb1..8a8acff 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -35,7 +35,7 @@
#include <plat/iic.h>
#include <plat/keypad.h>
#include <plat/mfc.h>
-#include <plat/regs-fb.h>
+#include <video/samsung_fimd.h>
#include <plat/regs-serial.h>
#include <plat/sdhci.h>
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 3cfa688..c2df6e8 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -28,7 +28,7 @@
#include <video/platform_lcd.h>
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 4d1f40d..e6fb471 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -39,7 +39,7 @@
#include <plat/fb.h>
#include <plat/mfc.h>
#include <plat/sdhci.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <plat/fimc-core.h>
#include <plat/s5p-time.h>
#include <plat/camport.h>
diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c
index 07a6dbe..53c4c51 100644
--- a/arch/arm/mach-exynos/setup-fimd0.c
+++ b/arch/arm/mach-exynos/setup-fimd0.c
@@ -14,7 +14,7 @@
#include <linux/gpio.h>
#include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <mach/map.h>
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index c3100a0..c8d5f51 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -52,7 +52,7 @@
#include <plat/udc.h>
#include <linux/platform_data/s3c-hsudc.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <plat/fb.h>
#include <plat/common-smdk.h>
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index ffa29dd..27e3087 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -44,7 +44,7 @@
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/fb.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <plat/clock.h>
#include <plat/devs.h>
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 09cd812..66e8c69 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -57,7 +57,7 @@
#include <mach/regs-gpio-memport.h>
#include <plat/regs-serial.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <plat/fb.h>
#include <plat/sdhci.h>
#include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 6890881..ab78c5e 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -41,7 +41,7 @@
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include "common.h"
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 5539a25..4b9a9ff 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -41,7 +41,7 @@
#include <plat/nand.h>
#include <plat/regs-serial.h>
#include <plat/ts.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <video/platform_lcd.h>
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index cad2e05..d4c8af0 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -43,7 +43,7 @@
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include "common.h"
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 326b216..05f05d2 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -42,7 +42,7 @@
#include <plat/nand.h>
#include <plat/regs-serial.h>
#include <plat/ts.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <video/platform_lcd.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index d6266d8..aa225ff 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -28,7 +28,7 @@
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include "common.h"
#include "mach-smartq.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 0957d2a..6e9c070 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -28,7 +28,7 @@
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include "common.h"
#include "mach-smartq.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 0fe4f15..1803192 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -72,7 +72,7 @@
#include <plat/ts.h>
#include <plat/keypad.h>
#include <plat/backlight.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include "common.h"
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 92fefad..0db0bdd 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -52,7 +52,7 @@
#include <plat/s5p-time.h>
#include <plat/backlight.h>
#include <plat/fb.h>
-#include <plat/regs-fb.h>
+#include <video/smasung_fimd.h>
#include <plat/sdhci.h>
#include "common.h"
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index e2335ec..c641d33 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -52,7 +52,7 @@
#include <plat/s5p-time.h>
#include <plat/backlight.h>
#include <plat/fb.h>
-#include <plat/regs-fb.h>
+#include <video/samsung_fimd.h>
#include <plat/sdhci.h>
#include "common.h"
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 0c3ae38..e4df3d0 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -51,7 +51,7 @@
#include <plat/ts.h>
#include <plat/audio.h>
#include <plat/backlight.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include "common.h"
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 78028df..8cbe4ac 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -39,7 +39,7 @@
#include <plat/fimc-core.h>
#include <plat/sdhci.h>
#include <plat/s5p-time.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include "common.h"
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 822a559..e799a02 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -49,7 +49,7 @@
#include <plat/clock.h>
#include <plat/s5p-time.h>
#include <plat/mfc.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <plat/camport.h>
#include <media/v4l2-mediabus.h>
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 918b23d..3c569e5 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -46,7 +46,7 @@
#include <plat/fb.h>
#include <plat/s5p-time.h>
#include <plat/backlight.h>
-#include <plat/regs-fb-v4.h>
+#include <video/samsung_fimd.h>
#include <plat/mfc.h>
#include <plat/clock.h>
--
1.7.0.4
^ permalink raw reply related
* [PATCH 1/3] Move FIMD register headers to include/video/
From: Leela Krishna Amudala @ 2012-07-30 8:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc
Cc: dri-devel, linux-fbdev, ben-linux, inki.dae, kgene.kim, joshi,
jg1.han
In-Reply-To: <1343637905-17764-1-git-send-email-l.krishna@samsung.com>
Moved the contents of regs-fb-v4.h and regs-fb.h from arch side
to include/video/samsung_fimd.h
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
---
arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 159 -------
arch/arm/plat-samsung/include/plat/regs-fb.h | 403 -----------------
include/video/samsung_fimd.h | 533 +++++++++++++++++++++++
3 files changed, 533 insertions(+), 562 deletions(-)
delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h
create mode 100644 include/video/samsung_fimd.h
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
deleted file mode 100644
index 4c3647f..0000000
--- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C64XX - new-style framebuffer register definitions
- *
- * This is the register set for the new style framebuffer interface
- * found from the S3C2443 onwards and specifically the S3C64XX series
- * S3C6400 and S3C6410.
- *
- * The file contains the cpu specific items which change between whichever
- * architecture is selected. See <plat/regs-fb.h> for the core definitions
- * that are the same.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* include the core definitions here, in case we really do need to
- * override them at a later date.
-*/
-
-#include <plat/regs-fb.h>
-
-#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
-#define VIDCON1_FSTATUS_EVEN (1 << 15)
-
-/* Video timing controls */
-#define VIDTCON0 (0x10)
-#define VIDTCON1 (0x14)
-#define VIDTCON2 (0x18)
-
-/* Window position controls */
-
-#define WINCON(_win) (0x20 + ((_win) * 4))
-
-/* OSD1 and OSD4 do not have register D */
-
-#define VIDOSD_BASE (0x40)
-
-#define VIDINTCON0 (0x130)
-
-/* WINCONx */
-
-#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
-#define WINCONx_CSCWIDTH_SHIFT (26)
-#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
-#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
-
-#define WINCONx_ENLOCAL (1 << 22)
-#define WINCONx_BUFSTATUS (1 << 21)
-#define WINCONx_BUFSEL (1 << 20)
-#define WINCONx_BUFAUTOEN (1 << 19)
-#define WINCONx_YCbCr (1 << 13)
-
-#define WINCON1_LOCALSEL_CAMIF (1 << 23)
-
-#define WINCON2_LOCALSEL_CAMIF (1 << 23)
-#define WINCON2_BLD_PIX (1 << 6)
-
-#define WINCON2_ALPHA_SEL (1 << 1)
-#define WINCON2_BPPMODE_MASK (0xf << 2)
-#define WINCON2_BPPMODE_SHIFT (2)
-#define WINCON2_BPPMODE_1BPP (0x0 << 2)
-#define WINCON2_BPPMODE_2BPP (0x1 << 2)
-#define WINCON2_BPPMODE_4BPP (0x2 << 2)
-#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
-#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
-#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
-#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
-#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
-#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
-#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
-#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
-#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
-#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
-#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
-
-#define WINCON3_BLD_PIX (1 << 6)
-
-#define WINCON3_ALPHA_SEL (1 << 1)
-#define WINCON3_BPPMODE_MASK (0xf << 2)
-#define WINCON3_BPPMODE_SHIFT (2)
-#define WINCON3_BPPMODE_1BPP (0x0 << 2)
-#define WINCON3_BPPMODE_2BPP (0x1 << 2)
-#define WINCON3_BPPMODE_4BPP (0x2 << 2)
-#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
-#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
-#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
-#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
-#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
-#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
-#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
-#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
-#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
-#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
-
-#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
-
-#define DITHMODE (0x170)
-#define WINxMAP(_win) (0x180 + ((_win) * 4))
-
-
-#define DITHMODE_R_POS_MASK (0x3 << 5)
-#define DITHMODE_R_POS_SHIFT (5)
-#define DITHMODE_R_POS_8BIT (0x0 << 5)
-#define DITHMODE_R_POS_6BIT (0x1 << 5)
-#define DITHMODE_R_POS_5BIT (0x2 << 5)
-
-#define DITHMODE_G_POS_MASK (0x3 << 3)
-#define DITHMODE_G_POS_SHIFT (3)
-#define DITHMODE_G_POS_8BIT (0x0 << 3)
-#define DITHMODE_G_POS_6BIT (0x1 << 3)
-#define DITHMODE_G_POS_5BIT (0x2 << 3)
-
-#define DITHMODE_B_POS_MASK (0x3 << 1)
-#define DITHMODE_B_POS_SHIFT (1)
-#define DITHMODE_B_POS_8BIT (0x0 << 1)
-#define DITHMODE_B_POS_6BIT (0x1 << 1)
-#define DITHMODE_B_POS_5BIT (0x2 << 1)
-
-#define DITHMODE_DITH_EN (1 << 0)
-
-#define WPALCON (0x1A0)
-
-/* Palette control */
-/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
- * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
-#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
-#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
-#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
-
-
-/* Notes on per-window bpp settings
- *
- * Value Win0 Win1 Win2 Win3 Win 4
- * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
- * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
- * 0010 4(P) 4(P) 4(P) 4(P) -none-
- * 0011 8(P) 8(P) -none- -none- -none-
- * 0100 -none- 8(A232) 8(A232) -none- -none-
- * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
- * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
- * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
- * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
- * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
- * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
- * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
- * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
- * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
- * 1110 -none- -none- -none- -none- -none-
- * 1111 -none- -none- -none- -none- -none-
-*/
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
deleted file mode 100644
index 9a78012..0000000
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/regs-fb.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C Platform - new-style framebuffer register definitions
- *
- * This is the register set for the new style framebuffer interface
- * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
- * S3C64XX series such as the S3C6400 and S3C6410.
- *
- * The file does not contain the cpu specific items which are based on
- * whichever architecture is selected, it only contains the core of the
- * register set. See <mach/regs-fb.h> to get the specifics.
- *
- * Note, we changed to using regs-fb.h as it avoids any clashes with
- * the original regs-lcd.h so out of the way of regs-lcd.h as well as
- * indicating the newer block is much more than just an LCD interface.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* Please do not include this file directly, use <mach/regs-fb.h> to
- * ensure all the localised SoC support is included as necessary.
-*/
-
-/* VIDCON0 */
-
-#define VIDCON0 (0x00)
-#define VIDCON0_INTERLACE (1 << 29)
-#define VIDCON0_VIDOUT_MASK (0x3 << 26)
-#define VIDCON0_VIDOUT_SHIFT (26)
-#define VIDCON0_VIDOUT_RGB (0x0 << 26)
-#define VIDCON0_VIDOUT_TV (0x1 << 26)
-#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
-#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
-
-#define VIDCON0_L1_DATA_MASK (0x7 << 23)
-#define VIDCON0_L1_DATA_SHIFT (23)
-#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
-#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
-#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
-#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
-#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
-#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
-
-#define VIDCON0_L0_DATA_MASK (0x7 << 20)
-#define VIDCON0_L0_DATA_SHIFT (20)
-#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
-#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
-#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
-#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
-#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
-#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
-
-#define VIDCON0_PNRMODE_MASK (0x3 << 17)
-#define VIDCON0_PNRMODE_SHIFT (17)
-#define VIDCON0_PNRMODE_RGB (0x0 << 17)
-#define VIDCON0_PNRMODE_BGR (0x1 << 17)
-#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
-#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
-
-#define VIDCON0_CLKVALUP (1 << 16)
-#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
-#define VIDCON0_CLKVAL_F_SHIFT (6)
-#define VIDCON0_CLKVAL_F_LIMIT (0xff)
-#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
-#define VIDCON0_VLCKFREE (1 << 5)
-#define VIDCON0_CLKDIR (1 << 4)
-
-#define VIDCON0_CLKSEL_MASK (0x3 << 2)
-#define VIDCON0_CLKSEL_SHIFT (2)
-#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
-#define VIDCON0_CLKSEL_LCD (0x1 << 2)
-#define VIDCON0_CLKSEL_27M (0x3 << 2)
-
-#define VIDCON0_ENVID (1 << 1)
-#define VIDCON0_ENVID_F (1 << 0)
-
-#define VIDCON1 (0x04)
-#define VIDCON1_LINECNT_MASK (0x7ff << 16)
-#define VIDCON1_LINECNT_SHIFT (16)
-#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
-#define VIDCON1_VSTATUS_MASK (0x3 << 13)
-#define VIDCON1_VSTATUS_SHIFT (13)
-#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
-#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
-#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
-#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
-#define VIDCON1_VCLK_MASK (0x3 << 9)
-#define VIDCON1_VCLK_HOLD (0x0 << 9)
-#define VIDCON1_VCLK_RUN (0x1 << 9)
-
-#define VIDCON1_INV_VCLK (1 << 7)
-#define VIDCON1_INV_HSYNC (1 << 6)
-#define VIDCON1_INV_VSYNC (1 << 5)
-#define VIDCON1_INV_VDEN (1 << 4)
-
-/* VIDCON2 */
-
-#define VIDCON2 (0x08)
-#define VIDCON2_EN601 (1 << 23)
-#define VIDCON2_TVFMTSEL_SW (1 << 14)
-
-#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
-#define VIDCON2_TVFMTSEL1_SHIFT (12)
-#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
-#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
-#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
-
-#define VIDCON2_ORGYCbCr (1 << 8)
-#define VIDCON2_YUVORDCrCb (1 << 7)
-
-/* PRTCON (S3C6410, S5PC100)
- * Might not be present in the S3C6410 documentation,
- * but tests prove it's there almost for sure; shouldn't hurt in any case.
- */
-#define PRTCON (0x0c)
-#define PRTCON_PROTECT (1 << 11)
-
-/* VIDTCON0 */
-
-#define VIDTCON0_VBPDE_MASK (0xff << 24)
-#define VIDTCON0_VBPDE_SHIFT (24)
-#define VIDTCON0_VBPDE_LIMIT (0xff)
-#define VIDTCON0_VBPDE(_x) ((_x) << 24)
-
-#define VIDTCON0_VBPD_MASK (0xff << 16)
-#define VIDTCON0_VBPD_SHIFT (16)
-#define VIDTCON0_VBPD_LIMIT (0xff)
-#define VIDTCON0_VBPD(_x) ((_x) << 16)
-
-#define VIDTCON0_VFPD_MASK (0xff << 8)
-#define VIDTCON0_VFPD_SHIFT (8)
-#define VIDTCON0_VFPD_LIMIT (0xff)
-#define VIDTCON0_VFPD(_x) ((_x) << 8)
-
-#define VIDTCON0_VSPW_MASK (0xff << 0)
-#define VIDTCON0_VSPW_SHIFT (0)
-#define VIDTCON0_VSPW_LIMIT (0xff)
-#define VIDTCON0_VSPW(_x) ((_x) << 0)
-
-/* VIDTCON1 */
-
-#define VIDTCON1_VFPDE_MASK (0xff << 24)
-#define VIDTCON1_VFPDE_SHIFT (24)
-#define VIDTCON1_VFPDE_LIMIT (0xff)
-#define VIDTCON1_VFPDE(_x) ((_x) << 24)
-
-#define VIDTCON1_HBPD_MASK (0xff << 16)
-#define VIDTCON1_HBPD_SHIFT (16)
-#define VIDTCON1_HBPD_LIMIT (0xff)
-#define VIDTCON1_HBPD(_x) ((_x) << 16)
-
-#define VIDTCON1_HFPD_MASK (0xff << 8)
-#define VIDTCON1_HFPD_SHIFT (8)
-#define VIDTCON1_HFPD_LIMIT (0xff)
-#define VIDTCON1_HFPD(_x) ((_x) << 8)
-
-#define VIDTCON1_HSPW_MASK (0xff << 0)
-#define VIDTCON1_HSPW_SHIFT (0)
-#define VIDTCON1_HSPW_LIMIT (0xff)
-#define VIDTCON1_HSPW(_x) ((_x) << 0)
-
-#define VIDTCON2 (0x18)
-#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
-#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
-#define VIDTCON2_LINEVAL_SHIFT (11)
-#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
-#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
-
-#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
-#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
-#define VIDTCON2_HOZVAL_SHIFT (0)
-#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
-#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
-
-/* WINCONx */
-
-
-#define WINCONx_BITSWP (1 << 18)
-#define WINCONx_BYTSWP (1 << 17)
-#define WINCONx_HAWSWP (1 << 16)
-#define WINCONx_WSWP (1 << 15)
-#define WINCONx_BURSTLEN_MASK (0x3 << 9)
-#define WINCONx_BURSTLEN_SHIFT (9)
-#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
-#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
-#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
-
-#define WINCONx_ENWIN (1 << 0)
-#define WINCON0_BPPMODE_MASK (0xf << 2)
-#define WINCON0_BPPMODE_SHIFT (2)
-#define WINCON0_BPPMODE_1BPP (0x0 << 2)
-#define WINCON0_BPPMODE_2BPP (0x1 << 2)
-#define WINCON0_BPPMODE_4BPP (0x2 << 2)
-#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
-#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
-#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
-#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
-#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
-
-#define WINCON1_BLD_PIX (1 << 6)
-
-#define WINCON1_ALPHA_SEL (1 << 1)
-#define WINCON1_BPPMODE_MASK (0xf << 2)
-#define WINCON1_BPPMODE_SHIFT (2)
-#define WINCON1_BPPMODE_1BPP (0x0 << 2)
-#define WINCON1_BPPMODE_2BPP (0x1 << 2)
-#define WINCON1_BPPMODE_4BPP (0x2 << 2)
-#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
-#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
-#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
-#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
-#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
-#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
-#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
-#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
-#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
-#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
-#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
-#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
-
-/* S5PV210 */
-#define SHADOWCON (0x34)
-#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
-/* DMA channels (all windows) */
-#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
-/* Local input channels (windows 0-2) */
-#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
-
-#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
-#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
-#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
-#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
-#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
-
-#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
-#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
-#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
-#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
-#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
-
-#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
-#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
-#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
-#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
-#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
-
-#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
-#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
-#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
-#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
-#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
-
-/* For VIDOSD[1..4]C */
-#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
-#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
-#define VIDISD14C_ALPHA0_G_SHIFT (16)
-#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
-#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
-#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
-#define VIDISD14C_ALPHA0_B_SHIFT (12)
-#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
-#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
-#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
-#define VIDISD14C_ALPHA1_R_SHIFT (8)
-#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
-#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
-#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
-#define VIDISD14C_ALPHA1_G_SHIFT (4)
-#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
-#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
-#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
-#define VIDISD14C_ALPHA1_B_SHIFT (0)
-#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
-#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
-
-/* Video buffer addresses */
-#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
-#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
-#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
-#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
-#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
-
-#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
-#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
-#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
-#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
-#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
-
-#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
-#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
-#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
-#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
-#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
-
-/* Interrupt controls and status */
-
-#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
-#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
-#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
-#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
-
-#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
-#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
-#define VIDINTCON0_INT_I80IFDONE (1 << 17)
-
-#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
-#define VIDINTCON0_FRAMESEL0_SHIFT (15)
-#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
-#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
-#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
-#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
-
-#define VIDINTCON0_FRAMESEL1 (1 << 13)
-#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
-#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
-#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
-#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
-#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
-
-#define VIDINTCON0_INT_FRAME (1 << 12)
-#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
-#define VIDINTCON0_FIFIOSEL_SHIFT (5)
-#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
-
-#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
-#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
-#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
-#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
-#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
-#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
-#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
-
-#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
-#define VIDINTCON0_INT_FIFO_SHIFT (0)
-#define VIDINTCON0_INT_ENABLE (1 << 0)
-
-#define VIDINTCON1 (0x134)
-#define VIDINTCON1_INT_I180 (1 << 2)
-#define VIDINTCON1_INT_FRAME (1 << 1)
-#define VIDINTCON1_INT_FIFO (1 << 0)
-
-/* Window colour-key control registers */
-#define WKEYCON (0x140) /* 6410,V210 */
-
-#define WKEYCON0 (0x00)
-#define WKEYCON1 (0x04)
-
-#define WxKEYCON0_KEYBL_EN (1 << 26)
-#define WxKEYCON0_KEYEN_F (1 << 25)
-#define WxKEYCON0_DIRCON (1 << 24)
-#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
-#define WxKEYCON0_COMPKEY_SHIFT (0)
-#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
-#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
-#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
-#define WxKEYCON1_COLVAL_SHIFT (0)
-#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
-#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
-
-
-/* Window blanking (MAP) */
-
-#define WINxMAP_MAP (1 << 24)
-#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
-#define WINxMAP_MAP_COLOUR_SHIFT (0)
-#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
-#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
-
-#define WPALCON_PAL_UPDATE (1 << 9)
-#define WPALCON_W1PAL_MASK (0x7 << 3)
-#define WPALCON_W1PAL_SHIFT (3)
-#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
-#define WPALCON_W1PAL_24BPP (0x1 << 3)
-#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
-#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
-#define WPALCON_W1PAL_18BPP (0x4 << 3)
-#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
-#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
-
-#define WPALCON_W0PAL_MASK (0x7 << 0)
-#define WPALCON_W0PAL_SHIFT (0)
-#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
-#define WPALCON_W0PAL_24BPP (0x1 << 0)
-#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
-#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
-#define WPALCON_W0PAL_18BPP (0x4 << 0)
-#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
-#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
-
-/* Blending equation control */
-#define BLENDCON (0x260)
-#define BLENDCON_NEW_MASK (1 << 0)
-#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
-#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
-
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
new file mode 100644
index 0000000..1b5ff4c
--- /dev/null
+++ b/include/video/samsung_fimd.h
@@ -0,0 +1,533 @@
+/* include/video/samsung_fimd.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - new-style fimd and framebuffer register definitions
+ *
+ * This is the register set for the fimd and new style framebuffer interface
+ * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
+ * S3C64XX series such as the S3C6400 and S3C6410.
+ *
+ * The file does not contain the cpu specific items which are based on
+ * whichever architecture is selected, it only contains the core of the
+ * register set. See <mach/regs-fb.h> to get the specifics.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* VIDCON0 */
+
+#define VIDCON0 (0x00)
+#define VIDCON0_INTERLACE (1 << 29)
+#define VIDCON0_VIDOUT_MASK (0x3 << 26)
+#define VIDCON0_VIDOUT_SHIFT (26)
+#define VIDCON0_VIDOUT_RGB (0x0 << 26)
+#define VIDCON0_VIDOUT_TV (0x1 << 26)
+#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
+#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
+
+#define VIDCON0_L1_DATA_MASK (0x7 << 23)
+#define VIDCON0_L1_DATA_SHIFT (23)
+#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
+#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
+#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
+#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
+#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
+#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
+
+#define VIDCON0_L0_DATA_MASK (0x7 << 20)
+#define VIDCON0_L0_DATA_SHIFT (20)
+#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
+#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
+#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
+#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
+#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
+#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
+
+#define VIDCON0_PNRMODE_MASK (0x3 << 17)
+#define VIDCON0_PNRMODE_SHIFT (17)
+#define VIDCON0_PNRMODE_RGB (0x0 << 17)
+#define VIDCON0_PNRMODE_BGR (0x1 << 17)
+#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
+#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
+
+#define VIDCON0_CLKVALUP (1 << 16)
+#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
+#define VIDCON0_CLKVAL_F_SHIFT (6)
+#define VIDCON0_CLKVAL_F_LIMIT (0xff)
+#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
+#define VIDCON0_VLCKFREE (1 << 5)
+#define VIDCON0_CLKDIR (1 << 4)
+
+#define VIDCON0_CLKSEL_MASK (0x3 << 2)
+#define VIDCON0_CLKSEL_SHIFT (2)
+#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
+#define VIDCON0_CLKSEL_LCD (0x1 << 2)
+#define VIDCON0_CLKSEL_27M (0x3 << 2)
+
+#define VIDCON0_ENVID (1 << 1)
+#define VIDCON0_ENVID_F (1 << 0)
+
+#define VIDCON1 (0x04)
+#define VIDCON1_LINECNT_MASK (0x7ff << 16)
+#define VIDCON1_LINECNT_SHIFT (16)
+#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
+#define VIDCON1_VSTATUS_MASK (0x3 << 13)
+#define VIDCON1_VSTATUS_SHIFT (13)
+#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
+#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
+#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
+#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
+#define VIDCON1_VCLK_MASK (0x3 << 9)
+#define VIDCON1_VCLK_HOLD (0x0 << 9)
+#define VIDCON1_VCLK_RUN (0x1 << 9)
+
+#define VIDCON1_INV_VCLK (1 << 7)
+#define VIDCON1_INV_HSYNC (1 << 6)
+#define VIDCON1_INV_VSYNC (1 << 5)
+#define VIDCON1_INV_VDEN (1 << 4)
+
+/* VIDCON2 */
+
+#define VIDCON2 (0x08)
+#define VIDCON2_EN601 (1 << 23)
+#define VIDCON2_TVFMTSEL_SW (1 << 14)
+
+#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
+#define VIDCON2_TVFMTSEL1_SHIFT (12)
+#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
+#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
+#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
+
+#define VIDCON2_ORGYCbCr (1 << 8)
+#define VIDCON2_YUVORDCrCb (1 << 7)
+
+/* PRTCON (S3C6410, S5PC100)
+ * Might not be present in the S3C6410 documentation,
+ * but tests prove it's there almost for sure; shouldn't hurt in any case.
+ */
+#define PRTCON (0x0c)
+#define PRTCON_PROTECT (1 << 11)
+
+/* VIDTCON0 */
+
+#define VIDTCON0_VBPDE_MASK (0xff << 24)
+#define VIDTCON0_VBPDE_SHIFT (24)
+#define VIDTCON0_VBPDE_LIMIT (0xff)
+#define VIDTCON0_VBPDE(_x) ((_x) << 24)
+
+#define VIDTCON0_VBPD_MASK (0xff << 16)
+#define VIDTCON0_VBPD_SHIFT (16)
+#define VIDTCON0_VBPD_LIMIT (0xff)
+#define VIDTCON0_VBPD(_x) ((_x) << 16)
+
+#define VIDTCON0_VFPD_MASK (0xff << 8)
+#define VIDTCON0_VFPD_SHIFT (8)
+#define VIDTCON0_VFPD_LIMIT (0xff)
+#define VIDTCON0_VFPD(_x) ((_x) << 8)
+
+#define VIDTCON0_VSPW_MASK (0xff << 0)
+#define VIDTCON0_VSPW_SHIFT (0)
+#define VIDTCON0_VSPW_LIMIT (0xff)
+#define VIDTCON0_VSPW(_x) ((_x) << 0)
+
+/* VIDTCON1 */
+
+#define VIDTCON1_VFPDE_MASK (0xff << 24)
+#define VIDTCON1_VFPDE_SHIFT (24)
+#define VIDTCON1_VFPDE_LIMIT (0xff)
+#define VIDTCON1_VFPDE(_x) ((_x) << 24)
+
+#define VIDTCON1_HBPD_MASK (0xff << 16)
+#define VIDTCON1_HBPD_SHIFT (16)
+#define VIDTCON1_HBPD_LIMIT (0xff)
+#define VIDTCON1_HBPD(_x) ((_x) << 16)
+
+#define VIDTCON1_HFPD_MASK (0xff << 8)
+#define VIDTCON1_HFPD_SHIFT (8)
+#define VIDTCON1_HFPD_LIMIT (0xff)
+#define VIDTCON1_HFPD(_x) ((_x) << 8)
+
+#define VIDTCON1_HSPW_MASK (0xff << 0)
+#define VIDTCON1_HSPW_SHIFT (0)
+#define VIDTCON1_HSPW_LIMIT (0xff)
+#define VIDTCON1_HSPW(_x) ((_x) << 0)
+
+#define VIDTCON2 (0x18)
+#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
+#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
+#define VIDTCON2_LINEVAL_SHIFT (11)
+#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
+#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
+
+#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
+#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
+#define VIDTCON2_HOZVAL_SHIFT (0)
+#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
+#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
+
+/* WINCONx */
+
+
+#define WINCONx_BITSWP (1 << 18)
+#define WINCONx_BYTSWP (1 << 17)
+#define WINCONx_HAWSWP (1 << 16)
+#define WINCONx_WSWP (1 << 15)
+#define WINCONx_BURSTLEN_MASK (0x3 << 9)
+#define WINCONx_BURSTLEN_SHIFT (9)
+#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
+#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
+#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
+
+#define WINCONx_ENWIN (1 << 0)
+#define WINCON0_BPPMODE_MASK (0xf << 2)
+#define WINCON0_BPPMODE_SHIFT (2)
+#define WINCON0_BPPMODE_1BPP (0x0 << 2)
+#define WINCON0_BPPMODE_2BPP (0x1 << 2)
+#define WINCON0_BPPMODE_4BPP (0x2 << 2)
+#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
+#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
+#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
+#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
+#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
+
+#define WINCON1_BLD_PIX (1 << 6)
+
+#define WINCON1_ALPHA_SEL (1 << 1)
+#define WINCON1_BPPMODE_MASK (0xf << 2)
+#define WINCON1_BPPMODE_SHIFT (2)
+#define WINCON1_BPPMODE_1BPP (0x0 << 2)
+#define WINCON1_BPPMODE_2BPP (0x1 << 2)
+#define WINCON1_BPPMODE_4BPP (0x2 << 2)
+#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
+#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
+#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
+#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
+#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
+#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
+#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
+#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
+#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
+#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
+#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
+#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
+
+/* S5PV210 */
+#define SHADOWCON (0x34)
+#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
+/* DMA channels (all windows) */
+#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
+/* Local input channels (windows 0-2) */
+#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
+
+#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
+#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
+#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
+#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
+#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
+
+#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
+#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
+#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
+#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
+#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
+
+#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
+#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
+#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
+#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
+#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
+
+#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
+#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
+#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
+#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
+#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
+
+/* For VIDOSD[1..4]C */
+#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
+#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
+#define VIDISD14C_ALPHA0_G_SHIFT (16)
+#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
+#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
+#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
+#define VIDISD14C_ALPHA0_B_SHIFT (12)
+#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
+#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
+#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
+#define VIDISD14C_ALPHA1_R_SHIFT (8)
+#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
+#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
+#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
+#define VIDISD14C_ALPHA1_G_SHIFT (4)
+#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
+#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
+#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
+#define VIDISD14C_ALPHA1_B_SHIFT (0)
+#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
+#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
+
+/* Video buffer addresses */
+#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
+#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
+#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
+#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
+#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
+
+#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
+#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
+#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
+#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
+#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
+
+#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
+#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
+#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
+#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
+#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
+
+/* Interrupt controls and status */
+
+#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
+#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
+#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
+#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
+
+#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
+#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
+#define VIDINTCON0_INT_I80IFDONE (1 << 17)
+
+#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
+#define VIDINTCON0_FRAMESEL0_SHIFT (15)
+#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
+#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
+#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
+#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
+
+#define VIDINTCON0_FRAMESEL1 (1 << 13)
+#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
+#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
+#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
+#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
+#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
+
+#define VIDINTCON0_INT_FRAME (1 << 12)
+#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
+#define VIDINTCON0_FIFIOSEL_SHIFT (5)
+#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
+
+#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
+#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
+#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
+#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
+#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
+#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
+#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
+
+#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
+#define VIDINTCON0_INT_FIFO_SHIFT (0)
+#define VIDINTCON0_INT_ENABLE (1 << 0)
+
+#define VIDINTCON1 (0x134)
+#define VIDINTCON1_INT_I180 (1 << 2)
+#define VIDINTCON1_INT_FRAME (1 << 1)
+#define VIDINTCON1_INT_FIFO (1 << 0)
+
+/* Window colour-key control registers */
+#define WKEYCON (0x140) /* 6410,V210 */
+
+#define WKEYCON0 (0x00)
+#define WKEYCON1 (0x04)
+
+#define WxKEYCON0_KEYBL_EN (1 << 26)
+#define WxKEYCON0_KEYEN_F (1 << 25)
+#define WxKEYCON0_DIRCON (1 << 24)
+#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
+#define WxKEYCON0_COMPKEY_SHIFT (0)
+#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
+#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
+#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
+#define WxKEYCON1_COLVAL_SHIFT (0)
+#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
+#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
+
+
+/* Window blanking (MAP) */
+
+#define WINxMAP_MAP (1 << 24)
+#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
+#define WINxMAP_MAP_COLOUR_SHIFT (0)
+#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
+#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
+
+#define WPALCON_PAL_UPDATE (1 << 9)
+#define WPALCON_W1PAL_MASK (0x7 << 3)
+#define WPALCON_W1PAL_SHIFT (3)
+#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
+#define WPALCON_W1PAL_24BPP (0x1 << 3)
+#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
+#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
+#define WPALCON_W1PAL_18BPP (0x4 << 3)
+#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
+#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
+
+#define WPALCON_W0PAL_MASK (0x7 << 0)
+#define WPALCON_W0PAL_SHIFT (0)
+#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
+#define WPALCON_W0PAL_24BPP (0x1 << 0)
+#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
+#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
+#define WPALCON_W0PAL_18BPP (0x4 << 0)
+#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
+#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
+
+/* Blending equation control */
+#define BLENDCON (0x260)
+#define BLENDCON_NEW_MASK (1 << 0)
+#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
+#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
+
+#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
+#define VIDCON1_FSTATUS_EVEN (1 << 15)
+
+/* Video timing controls */
+#define VIDTCON0 (0x10)
+#define VIDTCON1 (0x14)
+#define VIDTCON2 (0x18)
+
+/* Window position controls */
+
+#define WINCON(_win) (0x20 + ((_win) * 4))
+
+/* OSD1 and OSD4 do not have register D */
+
+#define VIDOSD_BASE (0x40)
+
+#define VIDINTCON0 (0x130)
+
+/* WINCONx */
+
+#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
+#define WINCONx_CSCWIDTH_SHIFT (26)
+#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
+#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
+
+#define WINCONx_ENLOCAL (1 << 22)
+#define WINCONx_BUFSTATUS (1 << 21)
+#define WINCONx_BUFSEL (1 << 20)
+#define WINCONx_BUFAUTOEN (1 << 19)
+#define WINCONx_YCbCr (1 << 13)
+
+#define WINCON1_LOCALSEL_CAMIF (1 << 23)
+
+#define WINCON2_LOCALSEL_CAMIF (1 << 23)
+#define WINCON2_BLD_PIX (1 << 6)
+
+#define WINCON2_ALPHA_SEL (1 << 1)
+#define WINCON2_BPPMODE_MASK (0xf << 2)
+#define WINCON2_BPPMODE_SHIFT (2)
+#define WINCON2_BPPMODE_1BPP (0x0 << 2)
+#define WINCON2_BPPMODE_2BPP (0x1 << 2)
+#define WINCON2_BPPMODE_4BPP (0x2 << 2)
+#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
+#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
+#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
+#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
+#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
+#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
+#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
+#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
+#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
+#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
+#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
+
+#define WINCON3_BLD_PIX (1 << 6)
+
+#define WINCON3_ALPHA_SEL (1 << 1)
+#define WINCON3_BPPMODE_MASK (0xf << 2)
+#define WINCON3_BPPMODE_SHIFT (2)
+#define WINCON3_BPPMODE_1BPP (0x0 << 2)
+#define WINCON3_BPPMODE_2BPP (0x1 << 2)
+#define WINCON3_BPPMODE_4BPP (0x2 << 2)
+#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
+#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
+#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
+#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
+#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
+#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
+#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
+#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
+#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
+#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
+
+#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
+
+#define DITHMODE (0x170)
+#define WINxMAP(_win) (0x180 + ((_win) * 4))
+
+
+#define DITHMODE_R_POS_MASK (0x3 << 5)
+#define DITHMODE_R_POS_SHIFT (5)
+#define DITHMODE_R_POS_8BIT (0x0 << 5)
+#define DITHMODE_R_POS_6BIT (0x1 << 5)
+#define DITHMODE_R_POS_5BIT (0x2 << 5)
+
+#define DITHMODE_G_POS_MASK (0x3 << 3)
+#define DITHMODE_G_POS_SHIFT (3)
+#define DITHMODE_G_POS_8BIT (0x0 << 3)
+#define DITHMODE_G_POS_6BIT (0x1 << 3)
+#define DITHMODE_G_POS_5BIT (0x2 << 3)
+
+#define DITHMODE_B_POS_MASK (0x3 << 1)
+#define DITHMODE_B_POS_SHIFT (1)
+#define DITHMODE_B_POS_8BIT (0x0 << 1)
+#define DITHMODE_B_POS_6BIT (0x1 << 1)
+#define DITHMODE_B_POS_5BIT (0x2 << 1)
+
+#define DITHMODE_DITH_EN (1 << 0)
+
+#define WPALCON (0x1A0)
+
+/* Palette control */
+/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
+ * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
+#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
+#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
+#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
+
+
+/* Notes on per-window bpp settings
+ *
+ * Value Win0 Win1 Win2 Win3 Win 4
+ * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
+ * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
+ * 0010 4(P) 4(P) 4(P) 4(P) -none-
+ * 0011 8(P) 8(P) -none- -none- -none-
+ * 0100 -none- 8(A232) 8(A232) -none- -none-
+ * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
+ * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
+ * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
+ * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
+ * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
+ * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
+ * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
+ * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
+ * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
+ * 1110 -none- -none- -none- -none- -none-
+ * 1111 -none- -none- -none- -none- -none-
+*/
+
+/*FIMD V8 REG OFFSET */
+#define FIMD_V8_VIDTCON0 (0x20010)
+#define FIMD_V8_VIDTCON1 (0x20014)
+#define FIMD_V8_VIDTCON2 (0x20018)
+#define FIMD_V8_VIDTCON3 (0x2001C)
+#define FIMD_V8_VIDCON1 (0x20004)
--
1.7.0.4
^ permalink raw reply related
* [PATCH 0/3] ARM: SAMSUNG: Move FIMD headers to include/video/
From: Leela Krishna Amudala @ 2012-07-30 8:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc
Cc: dri-devel, linux-fbdev, ben-linux, inki.dae, kgene.kim, joshi,
jg1.han
This patchset moves the contents of regs-fb-v4.h and regs-fb.h from arch side
to include/video/samsung_fimd.h
This patchset is created and rebased against master branch of torvalds tree.
Tested on smdk5250 board, build tested for other boards.
Leela Krishna Amudala (3):
Move FIMD register headers to include/video/
arm: samsung: Include the modified FIMD header file
driver: Include the modified FIMD header file
arch/arm/mach-exynos/mach-nuri.c | 2 +-
arch/arm/mach-exynos/mach-origen.c | 2 +-
arch/arm/mach-exynos/mach-smdk4x12.c | 2 +-
arch/arm/mach-exynos/mach-smdkv310.c | 2 +-
arch/arm/mach-exynos/mach-universal_c210.c | 2 +-
arch/arm/mach-exynos/setup-fimd0.c | 2 +-
arch/arm/mach-s3c24xx/mach-smdk2416.c | 2 +-
arch/arm/mach-s3c64xx/mach-anw6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-crag6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-hmt.c | 2 +-
arch/arm/mach-s3c64xx/mach-mini6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-ncp.c | 2 +-
arch/arm/mach-s3c64xx/mach-real6410.c | 2 +-
arch/arm/mach-s3c64xx/mach-smartq5.c | 2 +-
arch/arm/mach-s3c64xx/mach-smartq7.c | 2 +-
arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +-
arch/arm/mach-s5p64x0/mach-smdk6440.c | 2 +-
arch/arm/mach-s5p64x0/mach-smdk6450.c | 2 +-
arch/arm/mach-s5pc100/mach-smdkc100.c | 2 +-
arch/arm/mach-s5pv210/mach-aquila.c | 2 +-
arch/arm/mach-s5pv210/mach-goni.c | 2 +-
arch/arm/mach-s5pv210/mach-smdkv210.c | 2 +-
arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 159 -------
arch/arm/plat-samsung/include/plat/regs-fb.h | 403 -----------------
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +-
drivers/video/s3c-fb.c | 2 +-
include/video/samsung_fimd.h | 533 +++++++++++++++++++++++
27 files changed, 557 insertions(+), 586 deletions(-)
delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h
create mode 100644 include/video/samsung_fimd.h
^ permalink raw reply
* Re: [PATCH 1/3] Move FIMD register headers to include/video/
From: Jingoo Han @ 2012-07-30 8:53 UTC (permalink / raw)
To: 'Leela Krishna Amudala', linux-arm-kernel,
linux-samsung-soc
Cc: dri-devel, linux-fbdev, ben-linux, inki.dae, kgene.kim, joshi,
'Marek Szyprowski', 'Jingoo Han'
In-Reply-To: <1343637905-17764-2-git-send-email-l.krishna@samsung.com>
On Monday, July 30, 2012 5:45 PM, Leela Krishna Amudala wrote:
>
> Moved the contents of regs-fb-v4.h and regs-fb.h from arch side
> to include/video/samsung_fimd.h
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 159 -------
> arch/arm/plat-samsung/include/plat/regs-fb.h | 403 -----------------
> include/video/samsung_fimd.h | 533 +++++++++++++++++++++++
> 3 files changed, 533 insertions(+), 562 deletions(-)
> delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h
> create mode 100644 include/video/samsung_fimd.h
>
> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-
> fb-v4.h
> deleted file mode 100644
> index 4c3647f..0000000
> --- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> +++ /dev/null
> @@ -1,159 +0,0 @@
> -/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> - *
> - * Copyright 2008 Openmoko, Inc.
> - * Copyright 2008 Simtec Electronics
> - * http://armlinux.simtec.co.uk/
> - * Ben Dooks <ben@simtec.co.uk>
> - *
> - * S3C64XX - new-style framebuffer register definitions
> - *
> - * This is the register set for the new style framebuffer interface
> - * found from the S3C2443 onwards and specifically the S3C64XX series
> - * S3C6400 and S3C6410.
> - *
> - * The file contains the cpu specific items which change between whichever
> - * architecture is selected. See <plat/regs-fb.h> for the core definitions
> - * that are the same.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> -*/
> -
> -/* include the core definitions here, in case we really do need to
> - * override them at a later date.
> -*/
> -
> -#include <plat/regs-fb.h>
> -
> -#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
> -#define VIDCON1_FSTATUS_EVEN (1 << 15)
> -
> -/* Video timing controls */
> -#define VIDTCON0 (0x10)
> -#define VIDTCON1 (0x14)
> -#define VIDTCON2 (0x18)
> -
> -/* Window position controls */
> -
> -#define WINCON(_win) (0x20 + ((_win) * 4))
> -
> -/* OSD1 and OSD4 do not have register D */
> -
> -#define VIDOSD_BASE (0x40)
> -
> -#define VIDINTCON0 (0x130)
> -
> -/* WINCONx */
> -
> -#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> -#define WINCONx_CSCWIDTH_SHIFT (26)
> -#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> -#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
> -
> -#define WINCONx_ENLOCAL (1 << 22)
> -#define WINCONx_BUFSTATUS (1 << 21)
> -#define WINCONx_BUFSEL (1 << 20)
> -#define WINCONx_BUFAUTOEN (1 << 19)
> -#define WINCONx_YCbCr (1 << 13)
> -
> -#define WINCON1_LOCALSEL_CAMIF (1 << 23)
> -
> -#define WINCON2_LOCALSEL_CAMIF (1 << 23)
> -#define WINCON2_BLD_PIX (1 << 6)
> -
> -#define WINCON2_ALPHA_SEL (1 << 1)
> -#define WINCON2_BPPMODE_MASK (0xf << 2)
> -#define WINCON2_BPPMODE_SHIFT (2)
> -#define WINCON2_BPPMODE_1BPP (0x0 << 2)
> -#define WINCON2_BPPMODE_2BPP (0x1 << 2)
> -#define WINCON2_BPPMODE_4BPP (0x2 << 2)
> -#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
> -#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
> -#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
> -#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
> -#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
> -#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
> -#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
> -#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
> -#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
> -#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
> -#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
> -
> -#define WINCON3_BLD_PIX (1 << 6)
> -
> -#define WINCON3_ALPHA_SEL (1 << 1)
> -#define WINCON3_BPPMODE_MASK (0xf << 2)
> -#define WINCON3_BPPMODE_SHIFT (2)
> -#define WINCON3_BPPMODE_1BPP (0x0 << 2)
> -#define WINCON3_BPPMODE_2BPP (0x1 << 2)
> -#define WINCON3_BPPMODE_4BPP (0x2 << 2)
> -#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
> -#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
> -#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
> -#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
> -#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
> -#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
> -#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
> -#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
> -#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
> -#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
> -
> -#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
> -#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
> -#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
> -
> -#define DITHMODE (0x170)
> -#define WINxMAP(_win) (0x180 + ((_win) * 4))
> -
> -
> -#define DITHMODE_R_POS_MASK (0x3 << 5)
> -#define DITHMODE_R_POS_SHIFT (5)
> -#define DITHMODE_R_POS_8BIT (0x0 << 5)
> -#define DITHMODE_R_POS_6BIT (0x1 << 5)
> -#define DITHMODE_R_POS_5BIT (0x2 << 5)
> -
> -#define DITHMODE_G_POS_MASK (0x3 << 3)
> -#define DITHMODE_G_POS_SHIFT (3)
> -#define DITHMODE_G_POS_8BIT (0x0 << 3)
> -#define DITHMODE_G_POS_6BIT (0x1 << 3)
> -#define DITHMODE_G_POS_5BIT (0x2 << 3)
> -
> -#define DITHMODE_B_POS_MASK (0x3 << 1)
> -#define DITHMODE_B_POS_SHIFT (1)
> -#define DITHMODE_B_POS_8BIT (0x0 << 1)
> -#define DITHMODE_B_POS_6BIT (0x1 << 1)
> -#define DITHMODE_B_POS_5BIT (0x2 << 1)
> -
> -#define DITHMODE_DITH_EN (1 << 0)
> -
> -#define WPALCON (0x1A0)
> -
> -/* Palette control */
> -/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
> - * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
> -#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
> -#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
> -#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
> -
> -
> -/* Notes on per-window bpp settings
> - *
> - * Value Win0 Win1 Win2 Win3 Win 4
> - * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
> - * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
> - * 0010 4(P) 4(P) 4(P) 4(P) -none-
> - * 0011 8(P) 8(P) -none- -none- -none-
> - * 0100 -none- 8(A232) 8(A232) -none- -none-
> - * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
> - * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
> - * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
> - * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
> - * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
> - * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
> - * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
> - * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
> - * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
> - * 1110 -none- -none- -none- -none- -none-
> - * 1111 -none- -none- -none- -none- -none-
> -*/
> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
> deleted file mode 100644
> index 9a78012..0000000
> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> +++ /dev/null
> @@ -1,403 +0,0 @@
> -/* arch/arm/plat-samsung/include/plat/regs-fb.h
> - *
> - * Copyright 2008 Openmoko, Inc.
> - * Copyright 2008 Simtec Electronics
> - * http://armlinux.simtec.co.uk/
> - * Ben Dooks <ben@simtec.co.uk>
> - *
> - * S3C Platform - new-style framebuffer register definitions
> - *
> - * This is the register set for the new style framebuffer interface
> - * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
> - * S3C64XX series such as the S3C6400 and S3C6410.
> - *
> - * The file does not contain the cpu specific items which are based on
> - * whichever architecture is selected, it only contains the core of the
> - * register set. See <mach/regs-fb.h> to get the specifics.
> - *
> - * Note, we changed to using regs-fb.h as it avoids any clashes with
> - * the original regs-lcd.h so out of the way of regs-lcd.h as well as
> - * indicating the newer block is much more than just an LCD interface.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> -*/
> -
> -/* Please do not include this file directly, use <mach/regs-fb.h> to
> - * ensure all the localised SoC support is included as necessary.
> -*/
> -
> -/* VIDCON0 */
> -
> -#define VIDCON0 (0x00)
> -#define VIDCON0_INTERLACE (1 << 29)
> -#define VIDCON0_VIDOUT_MASK (0x3 << 26)
> -#define VIDCON0_VIDOUT_SHIFT (26)
> -#define VIDCON0_VIDOUT_RGB (0x0 << 26)
> -#define VIDCON0_VIDOUT_TV (0x1 << 26)
> -#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> -#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> -
> -#define VIDCON0_L1_DATA_MASK (0x7 << 23)
> -#define VIDCON0_L1_DATA_SHIFT (23)
> -#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
> -#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
> -#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
> -#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
> -#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
> -#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
> -
> -#define VIDCON0_L0_DATA_MASK (0x7 << 20)
> -#define VIDCON0_L0_DATA_SHIFT (20)
> -#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
> -#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
> -#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
> -#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
> -#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
> -#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
> -
> -#define VIDCON0_PNRMODE_MASK (0x3 << 17)
> -#define VIDCON0_PNRMODE_SHIFT (17)
> -#define VIDCON0_PNRMODE_RGB (0x0 << 17)
> -#define VIDCON0_PNRMODE_BGR (0x1 << 17)
> -#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
> -#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
> -
> -#define VIDCON0_CLKVALUP (1 << 16)
> -#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
> -#define VIDCON0_CLKVAL_F_SHIFT (6)
> -#define VIDCON0_CLKVAL_F_LIMIT (0xff)
> -#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
> -#define VIDCON0_VLCKFREE (1 << 5)
> -#define VIDCON0_CLKDIR (1 << 4)
> -
> -#define VIDCON0_CLKSEL_MASK (0x3 << 2)
> -#define VIDCON0_CLKSEL_SHIFT (2)
> -#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
> -#define VIDCON0_CLKSEL_LCD (0x1 << 2)
> -#define VIDCON0_CLKSEL_27M (0x3 << 2)
> -
> -#define VIDCON0_ENVID (1 << 1)
> -#define VIDCON0_ENVID_F (1 << 0)
> -
> -#define VIDCON1 (0x04)
> -#define VIDCON1_LINECNT_MASK (0x7ff << 16)
> -#define VIDCON1_LINECNT_SHIFT (16)
> -#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
> -#define VIDCON1_VSTATUS_MASK (0x3 << 13)
> -#define VIDCON1_VSTATUS_SHIFT (13)
> -#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
> -#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
> -#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
> -#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
> -#define VIDCON1_VCLK_MASK (0x3 << 9)
> -#define VIDCON1_VCLK_HOLD (0x0 << 9)
> -#define VIDCON1_VCLK_RUN (0x1 << 9)
> -
> -#define VIDCON1_INV_VCLK (1 << 7)
> -#define VIDCON1_INV_HSYNC (1 << 6)
> -#define VIDCON1_INV_VSYNC (1 << 5)
> -#define VIDCON1_INV_VDEN (1 << 4)
> -
> -/* VIDCON2 */
> -
> -#define VIDCON2 (0x08)
> -#define VIDCON2_EN601 (1 << 23)
> -#define VIDCON2_TVFMTSEL_SW (1 << 14)
> -
> -#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> -#define VIDCON2_TVFMTSEL1_SHIFT (12)
> -#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> -#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> -#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> -
> -#define VIDCON2_ORGYCbCr (1 << 8)
> -#define VIDCON2_YUVORDCrCb (1 << 7)
> -
> -/* PRTCON (S3C6410, S5PC100)
> - * Might not be present in the S3C6410 documentation,
> - * but tests prove it's there almost for sure; shouldn't hurt in any case.
> - */
> -#define PRTCON (0x0c)
> -#define PRTCON_PROTECT (1 << 11)
> -
> -/* VIDTCON0 */
> -
> -#define VIDTCON0_VBPDE_MASK (0xff << 24)
> -#define VIDTCON0_VBPDE_SHIFT (24)
> -#define VIDTCON0_VBPDE_LIMIT (0xff)
> -#define VIDTCON0_VBPDE(_x) ((_x) << 24)
> -
> -#define VIDTCON0_VBPD_MASK (0xff << 16)
> -#define VIDTCON0_VBPD_SHIFT (16)
> -#define VIDTCON0_VBPD_LIMIT (0xff)
> -#define VIDTCON0_VBPD(_x) ((_x) << 16)
> -
> -#define VIDTCON0_VFPD_MASK (0xff << 8)
> -#define VIDTCON0_VFPD_SHIFT (8)
> -#define VIDTCON0_VFPD_LIMIT (0xff)
> -#define VIDTCON0_VFPD(_x) ((_x) << 8)
> -
> -#define VIDTCON0_VSPW_MASK (0xff << 0)
> -#define VIDTCON0_VSPW_SHIFT (0)
> -#define VIDTCON0_VSPW_LIMIT (0xff)
> -#define VIDTCON0_VSPW(_x) ((_x) << 0)
> -
> -/* VIDTCON1 */
> -
> -#define VIDTCON1_VFPDE_MASK (0xff << 24)
> -#define VIDTCON1_VFPDE_SHIFT (24)
> -#define VIDTCON1_VFPDE_LIMIT (0xff)
> -#define VIDTCON1_VFPDE(_x) ((_x) << 24)
> -
> -#define VIDTCON1_HBPD_MASK (0xff << 16)
> -#define VIDTCON1_HBPD_SHIFT (16)
> -#define VIDTCON1_HBPD_LIMIT (0xff)
> -#define VIDTCON1_HBPD(_x) ((_x) << 16)
> -
> -#define VIDTCON1_HFPD_MASK (0xff << 8)
> -#define VIDTCON1_HFPD_SHIFT (8)
> -#define VIDTCON1_HFPD_LIMIT (0xff)
> -#define VIDTCON1_HFPD(_x) ((_x) << 8)
> -
> -#define VIDTCON1_HSPW_MASK (0xff << 0)
> -#define VIDTCON1_HSPW_SHIFT (0)
> -#define VIDTCON1_HSPW_LIMIT (0xff)
> -#define VIDTCON1_HSPW(_x) ((_x) << 0)
> -
> -#define VIDTCON2 (0x18)
> -#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
> -#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
> -#define VIDTCON2_LINEVAL_SHIFT (11)
> -#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
> -#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
> -
> -#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
> -#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
> -#define VIDTCON2_HOZVAL_SHIFT (0)
> -#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
> -#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
> -
> -/* WINCONx */
> -
> -
> -#define WINCONx_BITSWP (1 << 18)
> -#define WINCONx_BYTSWP (1 << 17)
> -#define WINCONx_HAWSWP (1 << 16)
> -#define WINCONx_WSWP (1 << 15)
> -#define WINCONx_BURSTLEN_MASK (0x3 << 9)
> -#define WINCONx_BURSTLEN_SHIFT (9)
> -#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> -#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
> -#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
> -
> -#define WINCONx_ENWIN (1 << 0)
> -#define WINCON0_BPPMODE_MASK (0xf << 2)
> -#define WINCON0_BPPMODE_SHIFT (2)
> -#define WINCON0_BPPMODE_1BPP (0x0 << 2)
> -#define WINCON0_BPPMODE_2BPP (0x1 << 2)
> -#define WINCON0_BPPMODE_4BPP (0x2 << 2)
> -#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
> -#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
> -#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
> -#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
> -#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
> -
> -#define WINCON1_BLD_PIX (1 << 6)
> -
> -#define WINCON1_ALPHA_SEL (1 << 1)
> -#define WINCON1_BPPMODE_MASK (0xf << 2)
> -#define WINCON1_BPPMODE_SHIFT (2)
> -#define WINCON1_BPPMODE_1BPP (0x0 << 2)
> -#define WINCON1_BPPMODE_2BPP (0x1 << 2)
> -#define WINCON1_BPPMODE_4BPP (0x2 << 2)
> -#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
> -#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
> -#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
> -#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
> -#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
> -#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
> -#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
> -#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
> -#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
> -#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
> -#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
> -#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
> -
> -/* S5PV210 */
> -#define SHADOWCON (0x34)
> -#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
> -/* DMA channels (all windows) */
> -#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
> -/* Local input channels (windows 0-2) */
> -#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
> -
> -#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
> -#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
> -#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
> -#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
> -#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
> -
> -#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
> -#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
> -#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
> -#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
> -#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
> -
> -#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
> -#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
> -#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
> -#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
> -#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
> -
> -#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
> -#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
> -#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
> -#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
> -#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
> -
> -/* For VIDOSD[1..4]C */
> -#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
> -#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
> -#define VIDISD14C_ALPHA0_G_SHIFT (16)
> -#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
> -#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
> -#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
> -#define VIDISD14C_ALPHA0_B_SHIFT (12)
> -#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
> -#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
> -#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
> -#define VIDISD14C_ALPHA1_R_SHIFT (8)
> -#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
> -#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
> -#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
> -#define VIDISD14C_ALPHA1_G_SHIFT (4)
> -#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
> -#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
> -#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
> -#define VIDISD14C_ALPHA1_B_SHIFT (0)
> -#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
> -#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
> -
> -/* Video buffer addresses */
> -#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
> -#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
> -#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
> -#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
> -#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
> -
> -#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
> -#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
> -#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
> -#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
> -#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
> -
> -#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
> -#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
> -#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
> -#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
> -#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
> -
> -/* Interrupt controls and status */
> -
> -#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
> -#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
> -#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
> -#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
> -
> -#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
> -#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
> -#define VIDINTCON0_INT_I80IFDONE (1 << 17)
> -
> -#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
> -#define VIDINTCON0_FRAMESEL0_SHIFT (15)
> -#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
> -#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
> -#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
> -#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
> -
> -#define VIDINTCON0_FRAMESEL1 (1 << 13)
> -#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
> -#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
> -#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
> -#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
> -#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
> -
> -#define VIDINTCON0_INT_FRAME (1 << 12)
> -#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
> -#define VIDINTCON0_FIFIOSEL_SHIFT (5)
> -#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
> -#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
> -
> -#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
> -#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
> -#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
> -#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
> -#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
> -#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
> -#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
> -
> -#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
> -#define VIDINTCON0_INT_FIFO_SHIFT (0)
> -#define VIDINTCON0_INT_ENABLE (1 << 0)
> -
> -#define VIDINTCON1 (0x134)
> -#define VIDINTCON1_INT_I180 (1 << 2)
> -#define VIDINTCON1_INT_FRAME (1 << 1)
> -#define VIDINTCON1_INT_FIFO (1 << 0)
> -
> -/* Window colour-key control registers */
> -#define WKEYCON (0x140) /* 6410,V210 */
> -
> -#define WKEYCON0 (0x00)
> -#define WKEYCON1 (0x04)
> -
> -#define WxKEYCON0_KEYBL_EN (1 << 26)
> -#define WxKEYCON0_KEYEN_F (1 << 25)
> -#define WxKEYCON0_DIRCON (1 << 24)
> -#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
> -#define WxKEYCON0_COMPKEY_SHIFT (0)
> -#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
> -#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
> -#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
> -#define WxKEYCON1_COLVAL_SHIFT (0)
> -#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
> -#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
> -
> -
> -/* Window blanking (MAP) */
> -
> -#define WINxMAP_MAP (1 << 24)
> -#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
> -#define WINxMAP_MAP_COLOUR_SHIFT (0)
> -#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
> -#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
> -
> -#define WPALCON_PAL_UPDATE (1 << 9)
> -#define WPALCON_W1PAL_MASK (0x7 << 3)
> -#define WPALCON_W1PAL_SHIFT (3)
> -#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
> -#define WPALCON_W1PAL_24BPP (0x1 << 3)
> -#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
> -#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
> -#define WPALCON_W1PAL_18BPP (0x4 << 3)
> -#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
> -#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
> -
> -#define WPALCON_W0PAL_MASK (0x7 << 0)
> -#define WPALCON_W0PAL_SHIFT (0)
> -#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
> -#define WPALCON_W0PAL_24BPP (0x1 << 0)
> -#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
> -#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
> -#define WPALCON_W0PAL_18BPP (0x4 << 0)
> -#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> -#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
> -
> -/* Blending equation control */
> -#define BLENDCON (0x260)
> -#define BLENDCON_NEW_MASK (1 << 0)
> -#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> -#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
> -
> diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
> new file mode 100644
> index 0000000..1b5ff4c
> --- /dev/null
> +++ b/include/video/samsung_fimd.h
> @@ -0,0 +1,533 @@
> +/* include/video/samsung_fimd.h
> + *
> + * Copyright 2008 Openmoko, Inc.
> + * Copyright 2008 Simtec Electronics
> + * http://armlinux.simtec.co.uk/
> + * Ben Dooks <ben@simtec.co.uk>
> + *
> + * S3C Platform - new-style fimd and framebuffer register definitions
> + *
> + * This is the register set for the fimd and new style framebuffer interface
> + * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
> + * S3C64XX series such as the S3C6400 and S3C6410.
> + *
> + * The file does not contain the cpu specific items which are based on
> + * whichever architecture is selected, it only contains the core of the
> + * register set. See <mach/regs-fb.h> to get the specifics.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +/* VIDCON0 */
> +
> +#define VIDCON0 (0x00)
> +#define VIDCON0_INTERLACE (1 << 29)
> +#define VIDCON0_VIDOUT_MASK (0x3 << 26)
> +#define VIDCON0_VIDOUT_SHIFT (26)
> +#define VIDCON0_VIDOUT_RGB (0x0 << 26)
> +#define VIDCON0_VIDOUT_TV (0x1 << 26)
> +#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
> +#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
> +
> +#define VIDCON0_L1_DATA_MASK (0x7 << 23)
> +#define VIDCON0_L1_DATA_SHIFT (23)
> +#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
> +#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
> +#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
> +#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
> +#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
> +#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
> +
> +#define VIDCON0_L0_DATA_MASK (0x7 << 20)
> +#define VIDCON0_L0_DATA_SHIFT (20)
> +#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
> +#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
> +#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
> +#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
> +#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
> +#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
> +
> +#define VIDCON0_PNRMODE_MASK (0x3 << 17)
> +#define VIDCON0_PNRMODE_SHIFT (17)
> +#define VIDCON0_PNRMODE_RGB (0x0 << 17)
> +#define VIDCON0_PNRMODE_BGR (0x1 << 17)
> +#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
> +#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
> +
> +#define VIDCON0_CLKVALUP (1 << 16)
> +#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
> +#define VIDCON0_CLKVAL_F_SHIFT (6)
> +#define VIDCON0_CLKVAL_F_LIMIT (0xff)
> +#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
> +#define VIDCON0_VLCKFREE (1 << 5)
> +#define VIDCON0_CLKDIR (1 << 4)
> +
> +#define VIDCON0_CLKSEL_MASK (0x3 << 2)
> +#define VIDCON0_CLKSEL_SHIFT (2)
> +#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
> +#define VIDCON0_CLKSEL_LCD (0x1 << 2)
> +#define VIDCON0_CLKSEL_27M (0x3 << 2)
> +
> +#define VIDCON0_ENVID (1 << 1)
> +#define VIDCON0_ENVID_F (1 << 0)
> +
> +#define VIDCON1 (0x04)
> +#define VIDCON1_LINECNT_MASK (0x7ff << 16)
> +#define VIDCON1_LINECNT_SHIFT (16)
> +#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
> +#define VIDCON1_VSTATUS_MASK (0x3 << 13)
> +#define VIDCON1_VSTATUS_SHIFT (13)
> +#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
> +#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
> +#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
> +#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
> +#define VIDCON1_VCLK_MASK (0x3 << 9)
> +#define VIDCON1_VCLK_HOLD (0x0 << 9)
> +#define VIDCON1_VCLK_RUN (0x1 << 9)
> +
> +#define VIDCON1_INV_VCLK (1 << 7)
> +#define VIDCON1_INV_HSYNC (1 << 6)
> +#define VIDCON1_INV_VSYNC (1 << 5)
> +#define VIDCON1_INV_VDEN (1 << 4)
> +
> +/* VIDCON2 */
> +
> +#define VIDCON2 (0x08)
> +#define VIDCON2_EN601 (1 << 23)
> +#define VIDCON2_TVFMTSEL_SW (1 << 14)
> +
> +#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
> +#define VIDCON2_TVFMTSEL1_SHIFT (12)
> +#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
> +#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
> +#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
> +
> +#define VIDCON2_ORGYCbCr (1 << 8)
> +#define VIDCON2_YUVORDCrCb (1 << 7)
> +
> +/* PRTCON (S3C6410, S5PC100)
> + * Might not be present in the S3C6410 documentation,
> + * but tests prove it's there almost for sure; shouldn't hurt in any case.
> + */
> +#define PRTCON (0x0c)
> +#define PRTCON_PROTECT (1 << 11)
> +
> +/* VIDTCON0 */
> +
> +#define VIDTCON0_VBPDE_MASK (0xff << 24)
> +#define VIDTCON0_VBPDE_SHIFT (24)
> +#define VIDTCON0_VBPDE_LIMIT (0xff)
> +#define VIDTCON0_VBPDE(_x) ((_x) << 24)
> +
> +#define VIDTCON0_VBPD_MASK (0xff << 16)
> +#define VIDTCON0_VBPD_SHIFT (16)
> +#define VIDTCON0_VBPD_LIMIT (0xff)
> +#define VIDTCON0_VBPD(_x) ((_x) << 16)
> +
> +#define VIDTCON0_VFPD_MASK (0xff << 8)
> +#define VIDTCON0_VFPD_SHIFT (8)
> +#define VIDTCON0_VFPD_LIMIT (0xff)
> +#define VIDTCON0_VFPD(_x) ((_x) << 8)
> +
> +#define VIDTCON0_VSPW_MASK (0xff << 0)
> +#define VIDTCON0_VSPW_SHIFT (0)
> +#define VIDTCON0_VSPW_LIMIT (0xff)
> +#define VIDTCON0_VSPW(_x) ((_x) << 0)
> +
> +/* VIDTCON1 */
> +
> +#define VIDTCON1_VFPDE_MASK (0xff << 24)
> +#define VIDTCON1_VFPDE_SHIFT (24)
> +#define VIDTCON1_VFPDE_LIMIT (0xff)
> +#define VIDTCON1_VFPDE(_x) ((_x) << 24)
> +
> +#define VIDTCON1_HBPD_MASK (0xff << 16)
> +#define VIDTCON1_HBPD_SHIFT (16)
> +#define VIDTCON1_HBPD_LIMIT (0xff)
> +#define VIDTCON1_HBPD(_x) ((_x) << 16)
> +
> +#define VIDTCON1_HFPD_MASK (0xff << 8)
> +#define VIDTCON1_HFPD_SHIFT (8)
> +#define VIDTCON1_HFPD_LIMIT (0xff)
> +#define VIDTCON1_HFPD(_x) ((_x) << 8)
> +
> +#define VIDTCON1_HSPW_MASK (0xff << 0)
> +#define VIDTCON1_HSPW_SHIFT (0)
> +#define VIDTCON1_HSPW_LIMIT (0xff)
> +#define VIDTCON1_HSPW(_x) ((_x) << 0)
> +
> +#define VIDTCON2 (0x18)
> +#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
> +#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
> +#define VIDTCON2_LINEVAL_SHIFT (11)
> +#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
> +#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
> +
> +#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
> +#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
> +#define VIDTCON2_HOZVAL_SHIFT (0)
> +#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
> +#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
> +
> +/* WINCONx */
> +
> +
> +#define WINCONx_BITSWP (1 << 18)
> +#define WINCONx_BYTSWP (1 << 17)
> +#define WINCONx_HAWSWP (1 << 16)
> +#define WINCONx_WSWP (1 << 15)
> +#define WINCONx_BURSTLEN_MASK (0x3 << 9)
> +#define WINCONx_BURSTLEN_SHIFT (9)
> +#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
> +#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
> +#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
> +
> +#define WINCONx_ENWIN (1 << 0)
> +#define WINCON0_BPPMODE_MASK (0xf << 2)
> +#define WINCON0_BPPMODE_SHIFT (2)
> +#define WINCON0_BPPMODE_1BPP (0x0 << 2)
> +#define WINCON0_BPPMODE_2BPP (0x1 << 2)
> +#define WINCON0_BPPMODE_4BPP (0x2 << 2)
> +#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
> +#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
> +#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
> +#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
> +#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
> +
> +#define WINCON1_BLD_PIX (1 << 6)
> +
> +#define WINCON1_ALPHA_SEL (1 << 1)
> +#define WINCON1_BPPMODE_MASK (0xf << 2)
> +#define WINCON1_BPPMODE_SHIFT (2)
> +#define WINCON1_BPPMODE_1BPP (0x0 << 2)
> +#define WINCON1_BPPMODE_2BPP (0x1 << 2)
> +#define WINCON1_BPPMODE_4BPP (0x2 << 2)
> +#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
> +#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
> +#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
> +#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
> +#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
> +#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
> +#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
> +#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
> +#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
> +#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
> +#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
> +#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
> +
> +/* S5PV210 */
> +#define SHADOWCON (0x34)
> +#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
> +/* DMA channels (all windows) */
> +#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
> +/* Local input channels (windows 0-2) */
> +#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
> +
> +#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
> +#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
> +#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
> +#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
> +#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
> +
> +#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
> +#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
> +#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
> +#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
> +#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
> +
> +#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
> +#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
> +#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
> +#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
> +#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
> +
> +#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
> +#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
> +#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
> +#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
> +#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
> +
> +/* For VIDOSD[1..4]C */
> +#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
> +#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
> +#define VIDISD14C_ALPHA0_G_SHIFT (16)
> +#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
> +#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
> +#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
> +#define VIDISD14C_ALPHA0_B_SHIFT (12)
> +#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
> +#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
> +#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
> +#define VIDISD14C_ALPHA1_R_SHIFT (8)
> +#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
> +#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
> +#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
> +#define VIDISD14C_ALPHA1_G_SHIFT (4)
> +#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
> +#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
> +#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
> +#define VIDISD14C_ALPHA1_B_SHIFT (0)
> +#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
> +#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
> +
> +/* Video buffer addresses */
> +#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
> +#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
> +#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
> +#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
> +#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
> +
> +#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
> +#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
> +#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
> +#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
> +#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
> +
> +#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
> +#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
> +#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
> +#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
> +#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
> +
> +/* Interrupt controls and status */
> +
> +#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
> +#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
> +#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
> +#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
> +
> +#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
> +#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
> +#define VIDINTCON0_INT_I80IFDONE (1 << 17)
> +
> +#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
> +#define VIDINTCON0_FRAMESEL0_SHIFT (15)
> +#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
> +#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
> +#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
> +#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
> +
> +#define VIDINTCON0_FRAMESEL1 (1 << 13)
> +#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
> +#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
> +#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
> +#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
> +#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
> +
> +#define VIDINTCON0_INT_FRAME (1 << 12)
> +#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
> +#define VIDINTCON0_FIFIOSEL_SHIFT (5)
> +#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
> +#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
> +
> +#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
> +#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
> +#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
> +#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
> +#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
> +#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
> +#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
> +
> +#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
> +#define VIDINTCON0_INT_FIFO_SHIFT (0)
> +#define VIDINTCON0_INT_ENABLE (1 << 0)
> +
> +#define VIDINTCON1 (0x134)
> +#define VIDINTCON1_INT_I180 (1 << 2)
> +#define VIDINTCON1_INT_FRAME (1 << 1)
> +#define VIDINTCON1_INT_FIFO (1 << 0)
> +
> +/* Window colour-key control registers */
> +#define WKEYCON (0x140) /* 6410,V210 */
> +
> +#define WKEYCON0 (0x00)
> +#define WKEYCON1 (0x04)
> +
> +#define WxKEYCON0_KEYBL_EN (1 << 26)
> +#define WxKEYCON0_KEYEN_F (1 << 25)
> +#define WxKEYCON0_DIRCON (1 << 24)
> +#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
> +#define WxKEYCON0_COMPKEY_SHIFT (0)
> +#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
> +#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
> +#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
> +#define WxKEYCON1_COLVAL_SHIFT (0)
> +#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
> +#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
> +
> +
> +/* Window blanking (MAP) */
> +
> +#define WINxMAP_MAP (1 << 24)
> +#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
> +#define WINxMAP_MAP_COLOUR_SHIFT (0)
> +#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
> +#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
> +
> +#define WPALCON_PAL_UPDATE (1 << 9)
> +#define WPALCON_W1PAL_MASK (0x7 << 3)
> +#define WPALCON_W1PAL_SHIFT (3)
> +#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
> +#define WPALCON_W1PAL_24BPP (0x1 << 3)
> +#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
> +#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
> +#define WPALCON_W1PAL_18BPP (0x4 << 3)
> +#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
> +#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
> +
> +#define WPALCON_W0PAL_MASK (0x7 << 0)
> +#define WPALCON_W0PAL_SHIFT (0)
> +#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
> +#define WPALCON_W0PAL_24BPP (0x1 << 0)
> +#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
> +#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
> +#define WPALCON_W0PAL_18BPP (0x4 << 0)
> +#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
> +#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
> +
> +/* Blending equation control */
> +#define BLENDCON (0x260)
> +#define BLENDCON_NEW_MASK (1 << 0)
> +#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
> +#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
> +
> +#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
> +#define VIDCON1_FSTATUS_EVEN (1 << 15)
> +
> +/* Video timing controls */
> +#define VIDTCON0 (0x10)
> +#define VIDTCON1 (0x14)
> +#define VIDTCON2 (0x18)
> +
> +/* Window position controls */
> +
> +#define WINCON(_win) (0x20 + ((_win) * 4))
> +
> +/* OSD1 and OSD4 do not have register D */
> +
> +#define VIDOSD_BASE (0x40)
> +
> +#define VIDINTCON0 (0x130)
> +
> +/* WINCONx */
> +
> +#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
> +#define WINCONx_CSCWIDTH_SHIFT (26)
> +#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
> +#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
> +
> +#define WINCONx_ENLOCAL (1 << 22)
> +#define WINCONx_BUFSTATUS (1 << 21)
> +#define WINCONx_BUFSEL (1 << 20)
> +#define WINCONx_BUFAUTOEN (1 << 19)
> +#define WINCONx_YCbCr (1 << 13)
> +
> +#define WINCON1_LOCALSEL_CAMIF (1 << 23)
> +
> +#define WINCON2_LOCALSEL_CAMIF (1 << 23)
> +#define WINCON2_BLD_PIX (1 << 6)
> +
> +#define WINCON2_ALPHA_SEL (1 << 1)
> +#define WINCON2_BPPMODE_MASK (0xf << 2)
> +#define WINCON2_BPPMODE_SHIFT (2)
> +#define WINCON2_BPPMODE_1BPP (0x0 << 2)
> +#define WINCON2_BPPMODE_2BPP (0x1 << 2)
> +#define WINCON2_BPPMODE_4BPP (0x2 << 2)
> +#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
> +#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
> +#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
> +#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
> +#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
> +#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
> +#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
> +#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
> +#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
> +#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
> +#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
> +
> +#define WINCON3_BLD_PIX (1 << 6)
> +
> +#define WINCON3_ALPHA_SEL (1 << 1)
> +#define WINCON3_BPPMODE_MASK (0xf << 2)
> +#define WINCON3_BPPMODE_SHIFT (2)
> +#define WINCON3_BPPMODE_1BPP (0x0 << 2)
> +#define WINCON3_BPPMODE_2BPP (0x1 << 2)
> +#define WINCON3_BPPMODE_4BPP (0x2 << 2)
> +#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
> +#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
> +#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
> +#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
> +#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
> +#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
> +#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
> +#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
> +#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
> +#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
> +
> +#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
> +#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
> +#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
> +
> +#define DITHMODE (0x170)
> +#define WINxMAP(_win) (0x180 + ((_win) * 4))
> +
> +
> +#define DITHMODE_R_POS_MASK (0x3 << 5)
> +#define DITHMODE_R_POS_SHIFT (5)
> +#define DITHMODE_R_POS_8BIT (0x0 << 5)
> +#define DITHMODE_R_POS_6BIT (0x1 << 5)
> +#define DITHMODE_R_POS_5BIT (0x2 << 5)
> +
> +#define DITHMODE_G_POS_MASK (0x3 << 3)
> +#define DITHMODE_G_POS_SHIFT (3)
> +#define DITHMODE_G_POS_8BIT (0x0 << 3)
> +#define DITHMODE_G_POS_6BIT (0x1 << 3)
> +#define DITHMODE_G_POS_5BIT (0x2 << 3)
> +
> +#define DITHMODE_B_POS_MASK (0x3 << 1)
> +#define DITHMODE_B_POS_SHIFT (1)
> +#define DITHMODE_B_POS_8BIT (0x0 << 1)
> +#define DITHMODE_B_POS_6BIT (0x1 << 1)
> +#define DITHMODE_B_POS_5BIT (0x2 << 1)
> +
> +#define DITHMODE_DITH_EN (1 << 0)
> +
> +#define WPALCON (0x1A0)
> +
> +/* Palette control */
> +/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
> + * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
> +#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
> +#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
> +#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
> +
> +
> +/* Notes on per-window bpp settings
> + *
> + * Value Win0 Win1 Win2 Win3 Win 4
> + * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
> + * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
> + * 0010 4(P) 4(P) 4(P) 4(P) -none-
> + * 0011 8(P) 8(P) -none- -none- -none-
> + * 0100 -none- 8(A232) 8(A232) -none- -none-
> + * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
> + * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
> + * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
> + * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
> + * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
> + * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
> + * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
> + * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
> + * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
> + * 1110 -none- -none- -none- -none- -none-
> + * 1111 -none- -none- -none- -none- -none-
> +*/
> +
> +/*FIMD V8 REG OFFSET */
> +#define FIMD_V8_VIDTCON0 (0x20010)
> +#define FIMD_V8_VIDTCON1 (0x20014)
> +#define FIMD_V8_VIDTCON2 (0x20018)
> +#define FIMD_V8_VIDTCON3 (0x2001C)
> +#define FIMD_V8_VIDCON1 (0x20004)
CC'ed Marek.
To Leela Krishna Amudala,
Don't add these definitions for FIMD_V8_xxx registers, which are not related to current "regs-fb-v4.h and regs-fb.h".
Just "move" and "merge" regs-fb-v4.h and regs-fb.h to one header file, not "add" new definitions.
If you want to add these definitions, please make new patch for this.
Also, "#define FIMD_V8_xxx" is ugly.
I think that there is better way.
Please, find other way.
> --
> 1.7.0.4
^ permalink raw reply
* Re: [PATCH 1/3] Move FIMD register headers to include/video/
From: Sylwester Nawrocki @ 2012-07-30 8:49 UTC (permalink / raw)
To: Leela Krishna Amudala
Cc: linux-arm-kernel, linux-samsung-soc, dri-devel, linux-fbdev,
ben-linux, inki.dae, kgene.kim, joshi, jg1.han
In-Reply-To: <1343637905-17764-2-git-send-email-l.krishna@samsung.com>
Hi,
On 07/30/2012 10:45 AM, Leela Krishna Amudala wrote:
> Moved the contents of regs-fb-v4.h and regs-fb.h from arch side
> to include/video/samsung_fimd.h
>
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> ---
> arch/arm/plat-samsung/include/plat/regs-fb-v4.h | 159 -------
> arch/arm/plat-samsung/include/plat/regs-fb.h | 403 -----------------
> include/video/samsung_fimd.h | 533 +++++++++++++++++++++++
> 3 files changed, 533 insertions(+), 562 deletions(-)
> delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb-v4.h
> delete mode 100644 arch/arm/plat-samsung/include/plat/regs-fb.h
> create mode 100644 include/video/samsung_fimd.h
Thanks for taking care if this. However you might need to split this
patch in two, so there is no build and git bisection breakage. In the
first patch a new header file would be added, then the patch updating
users of the FIMD headers would be applied, and finally the regs-fb*.h
files would be removed.
Also it helps to use -M option to git format-patch when creating patches
that mainly move files.
--
Regards,
Sylwester
^ permalink raw reply
* RE: [PATCH v2 3/4] media: videobuf2-dma-contig: use dma_mmap_coherent if available
From: Marek Szyprowski @ 2012-07-30 7:43 UTC (permalink / raw)
To: 'Hideki EIRAKU', 'Russell King',
'Pawel Osciak', 'Kyungmin Park',
'Mauro Carvalho Chehab',
'Florian Tobias Schandinat', 'Jaroslav Kysela',
'Takashi Iwai'
Cc: linux-arm-kernel, linux-kernel, linux-media, linux-fbdev,
alsa-devel, 'Katsuya MATSUBARA'
In-Reply-To: <1343301191-26001-4-git-send-email-hdk@igel.co.jp>
Hello,
On Thursday, July 26, 2012 1:13 PM Hideki EIRAKU wrote:
> Previously the vb2_dma_contig_mmap() function was using a dma_addr_t as a
> physical address. The two addressses are not necessarily the same.
> For example, when using the IOMMU funtion on certain platforms, dma_addr_t
> addresses are not directly mappable physical address.
> dma_mmap_coherent() maps the address correctly.
> It is available on ARM platforms.
>
> Signed-off-by: Hideki EIRAKU <hdk@igel.co.jp>
> ---
> drivers/media/video/videobuf2-dma-contig.c | 18 ++++++++++++++++++
> 1 files changed, 18 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/media/video/videobuf2-dma-contig.c b/drivers/media/video/videobuf2-dma-
> contig.c
> index 4b71326..4dc85ab 100644
> --- a/drivers/media/video/videobuf2-dma-contig.c
> +++ b/drivers/media/video/videobuf2-dma-contig.c
> @@ -101,14 +101,32 @@ static unsigned int vb2_dma_contig_num_users(void *buf_priv)
> static int vb2_dma_contig_mmap(void *buf_priv, struct vm_area_struct *vma)
> {
> struct vb2_dc_buf *buf = buf_priv;
> +#ifdef ARCH_HAS_DMA_MMAP_COHERENT
> + int ret;
> +#endif
>
> if (!buf) {
> printk(KERN_ERR "No buffer to map\n");
> return -EINVAL;
> }
>
> +#ifdef ARCH_HAS_DMA_MMAP_COHERENT
> + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
The above line is not needed. It is up to dma_mmap_coherent() / dma_mmap_attrs() to set page
protection bits which match requested type of dma buffer mapping.
> + ret = dma_mmap_coherent(buf->conf->dev, vma, buf->vaddr, buf->dma_addr,
> + buf->size);
> + if (ret) {
> + pr_err("Remapping memory failed, error: %d\n", ret);
> + return ret;
> + }
> + vma->vm_flags |= VM_DONTEXPAND | VM_RESERVED;
> + vma->vm_private_data = &buf->handler;
> + vma->vm_ops = &vb2_common_vm_ops;
> + vma->vm_ops->open(vma);
> + return 0;
> +#else
> return vb2_mmap_pfn_range(vma, buf->dma_addr, buf->size,
> &vb2_common_vm_ops, &buf->handler);
> +#endif
> }
>
> static void *vb2_dma_contig_get_userptr(void *alloc_ctx, unsigned long vaddr,
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
^ permalink raw reply
* Re: [PATCH] video: exynos_dp: adjust voltage swing and pre-emphasis during Link Training
From: Florian Tobias Schandinat @ 2012-07-30 6:33 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <001101cd656a$5ea25c90$1be715b0$%han@samsung.com>
Hi,
On 07/30/2012 04:08 AM, Jingoo Han wrote:
> On Thursday, July 19, 2012 1:53 PM, Jingoo Han wrote:
>>
>> This patch adds adjustement for voltage swing and pre-emphasis during
>> Link Training procedure. According to the DP specification, unless all
>> the LANEx_CR_DONE bits are set, the transmitter must read
>> the ADJUST_REQUEST_LANEx_x, increase the voltage swing according to
>> the request, and update the TRAINING_LANEx_SET bytes to match the new
>> voltage swing setting.
>>
>> Refer to the DP specification v1.1a, Section 3.5.1.3 Link Training.
>>
>> Signed-off-by: Jingoo Han <jg1.han@samsung.com>
>
>
> Hi Florian,
>
> Could you accept this patch for 3.6-rc1?
I rather consider it for -rc2 or -rc3. You could have made my life easier by
(1) sending it earlier, not just half a week before the merge window
opened. For some reason a lot of patches ended up hitting my Inbox in
that timeframe which is bad timing for things that should go in this
merge window as I usually wait a week before applying to give others the
chance to comment on it and I should have my final tree ready the day
the merge window opens.
(2) reducing it to the bare minimum changes required or splitting it up
and not doing a bunch of unrelated changes
> This patch was already verified and tested with different 2 kinds of eDP LCD panels.
I'm not saying that your patch is wrong. I think it is important, but
given its size I don't feel comfortable with just looking at the code
but feel that it should be longer in -next than 2 days.
Best regards,
Florian Tobias Schandinat
> Thank you.
>
> Best regards,
> Jingoo Han
>
>
>> ---
>> drivers/video/exynos/exynos_dp_core.c | 282 +++++++++++++++++----------------
>> drivers/video/exynos/exynos_dp_core.h | 2 +-
>> 2 files changed, 144 insertions(+), 140 deletions(-)
>>
>> diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c
>> index c6c016a..9c0140f 100644
>> --- a/drivers/video/exynos/exynos_dp_core.c
>> +++ b/drivers/video/exynos/exynos_dp_core.c
>> @@ -260,7 +260,7 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
>>
>> static void exynos_dp_link_start(struct exynos_dp_device *dp)
>> {
>> - u8 buf[5];
>> + u8 buf[4];
>> int lane;
>> int lane_count;
>>
>> @@ -295,10 +295,10 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp)
>> exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
>>
>> /* Set RX training pattern */
>> - buf[0] = DPCD_SCRAMBLING_DISABLED |
>> - DPCD_TRAINING_PATTERN_1;
>> exynos_dp_write_byte_to_dpcd(dp,
>> - DPCD_ADDR_TRAINING_PATTERN_SET, buf[0]);
>> + DPCD_ADDR_TRAINING_PATTERN_SET,
>> + DPCD_SCRAMBLING_DISABLED |
>> + DPCD_TRAINING_PATTERN_1);
>>
>> for (lane = 0; lane < lane_count; lane++)
>> buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
>> @@ -308,7 +308,7 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp)
>> lane_count, buf);
>> }
>>
>> -static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
>> +static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
>> {
>> int shift = (lane & 1) * 4;
>> u8 link_value = link_status[lane>>1];
>> @@ -316,7 +316,7 @@ static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
>> return (link_value >> shift) & 0xf;
>> }
>>
>> -static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
>> +static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
>> {
>> int lane;
>> u8 lane_status;
>> @@ -329,22 +329,23 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
>> return 0;
>> }
>>
>> -static int exynos_dp_channel_eq_ok(u8 link_status[6], int lane_count)
>> +static int exynos_dp_channel_eq_ok(u8 link_align[3], int lane_count)
>> {
>> int lane;
>> u8 lane_align;
>> u8 lane_status;
>>
>> - lane_align = link_status[2];
>> + lane_align = link_align[2];
>> if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) = 0)
>> return -EINVAL;
>>
>> for (lane = 0; lane < lane_count; lane++) {
>> - lane_status = exynos_dp_get_lane_status(link_status, lane);
>> + lane_status = exynos_dp_get_lane_status(link_align, lane);
>> lane_status &= DPCD_CHANNEL_EQ_BITS;
>> if (lane_status != DPCD_CHANNEL_EQ_BITS)
>> return -EINVAL;
>> }
>> +
>> return 0;
>> }
>>
>> @@ -417,69 +418,17 @@ static unsigned int exynos_dp_get_lane_link_training(
>>
>> static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
>> {
>> - if (dp->link_train.link_rate = LINK_RATE_2_70GBPS) {
>> - /* set to reduced bit rate */
>> - dp->link_train.link_rate = LINK_RATE_1_62GBPS;
>> - dev_err(dp->dev, "set to bandwidth %.2x\n",
>> - dp->link_train.link_rate);
>> - dp->link_train.lt_state = START;
>> - } else {
>> - exynos_dp_training_pattern_dis(dp);
>> - /* set enhanced mode if available */
>> - exynos_dp_set_enhanced_mode(dp);
>> - dp->link_train.lt_state = FAILED;
>> - }
>> -}
>> -
>> -static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp,
>> - u8 adjust_request[2])
>> -{
>> - int lane;
>> - int lane_count;
>> - u8 voltage_swing;
>> - u8 pre_emphasis;
>> - u8 training_lane;
>> + exynos_dp_training_pattern_dis(dp);
>> + exynos_dp_set_enhanced_mode(dp);
>>
>> - lane_count = dp->link_train.lane_count;
>> - for (lane = 0; lane < lane_count; lane++) {
>> - voltage_swing = exynos_dp_get_adjust_request_voltage(
>> - adjust_request, lane);
>> - pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
>> - adjust_request, lane);
>> - training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
>> - DPCD_PRE_EMPHASIS_SET(pre_emphasis);
>> -
>> - if (voltage_swing = VOLTAGE_LEVEL_3 ||
>> - pre_emphasis = PRE_EMPHASIS_LEVEL_3) {
>> - training_lane |= DPCD_MAX_SWING_REACHED;
>> - training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
>> - }
>> - dp->link_train.training_lane[lane] = training_lane;
>> - }
>> -}
>> -
>> -static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp,
>> - u8 voltage_swing)
>> -{
>> - int lane;
>> - int lane_count;
>> -
>> - lane_count = dp->link_train.lane_count;
>> - for (lane = 0; lane < lane_count; lane++) {
>> - if (voltage_swing = VOLTAGE_LEVEL_3 ||
>> - dp->link_train.cr_loop[lane] = MAX_CR_LOOP)
>> - return -EINVAL;
>> - }
>> - return 0;
>> + dp->link_train.lt_state = FAILED;
>> }
>>
>> static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>> {
>> - u8 data;
>> - u8 link_status[6];
>> + u8 link_status[2];
>> int lane;
>> int lane_count;
>> - u8 buf[5];
>>
>> u8 adjust_request[2];
>> u8 voltage_swing;
>> @@ -488,98 +437,152 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>>
>> usleep_range(100, 101);
>>
>> - exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
>> - 6, link_status);
>> lane_count = dp->link_train.lane_count;
>>
>> + exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
>> + 2, link_status);
>> +
>> if (exynos_dp_clock_recovery_ok(link_status, lane_count) = 0) {
>> /* set training pattern 2 for EQ */
>> exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
>>
>> - adjust_request[0] = link_status[4];
>> - adjust_request[1] = link_status[5];
>> + for (lane = 0; lane < lane_count; lane++) {
>> + exynos_dp_read_bytes_from_dpcd(dp,
>> + DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
>> + 2, adjust_request);
>> + voltage_swing = exynos_dp_get_adjust_request_voltage(
>> + adjust_request, lane);
>> + pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
>> + adjust_request, lane);
>> + training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
>> + DPCD_PRE_EMPHASIS_SET(pre_emphasis);
>>
>> - exynos_dp_get_adjust_train(dp, adjust_request);
>> + if (voltage_swing = VOLTAGE_LEVEL_3)
>> + training_lane |= DPCD_MAX_SWING_REACHED;
>> + if (pre_emphasis = PRE_EMPHASIS_LEVEL_3)
>> + training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
>>
>> - buf[0] = DPCD_SCRAMBLING_DISABLED |
>> - DPCD_TRAINING_PATTERN_2;
>> - exynos_dp_write_byte_to_dpcd(dp,
>> - DPCD_ADDR_TRAINING_PATTERN_SET,
>> - buf[0]);
>> + dp->link_train.training_lane[lane] = training_lane;
>>
>> - for (lane = 0; lane < lane_count; lane++) {
>> exynos_dp_set_lane_link_training(dp,
>> dp->link_train.training_lane[lane],
>> lane);
>> - buf[lane] = dp->link_train.training_lane[lane];
>> - exynos_dp_write_byte_to_dpcd(dp,
>> - DPCD_ADDR_TRAINING_LANE0_SET + lane,
>> - buf[lane]);
>> }
>> - dp->link_train.lt_state = EQUALIZER_TRAINING;
>> - } else {
>> - exynos_dp_read_byte_from_dpcd(dp,
>> - DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
>> - &data);
>> - adjust_request[0] = data;
>>
>> - exynos_dp_read_byte_from_dpcd(dp,
>> - DPCD_ADDR_ADJUST_REQUEST_LANE2_3,
>> - &data);
>> - adjust_request[1] = data;
>> + exynos_dp_write_byte_to_dpcd(dp,
>> + DPCD_ADDR_TRAINING_PATTERN_SET,
>> + DPCD_SCRAMBLING_DISABLED |
>> + DPCD_TRAINING_PATTERN_2);
>> +
>> + exynos_dp_write_bytes_to_dpcd(dp,
>> + DPCD_ADDR_TRAINING_LANE0_SET,
>> + lane_count,
>> + dp->link_train.training_lane);
>>
>> + dev_info(dp->dev, "Link Training Clock Recovery success\n");
>> + dp->link_train.lt_state = EQUALIZER_TRAINING;
>> + } else {
>> for (lane = 0; lane < lane_count; lane++) {
>> training_lane = exynos_dp_get_lane_link_training(
>> dp, lane);
>> + exynos_dp_read_bytes_from_dpcd(dp,
>> + DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
>> + 2, adjust_request);
>> voltage_swing = exynos_dp_get_adjust_request_voltage(
>> adjust_request, lane);
>> pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
>> adjust_request, lane);
>> - if ((DPCD_VOLTAGE_SWING_GET(training_lane) = voltage_swing) &&
>> - (DPCD_PRE_EMPHASIS_GET(training_lane) = pre_emphasis))
>> - dp->link_train.cr_loop[lane]++;
>> - dp->link_train.training_lane[lane] = training_lane;
>> - }
>>
>> - if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) {
>> - exynos_dp_reduce_link_rate(dp);
>> - } else {
>> - exynos_dp_get_adjust_train(dp, adjust_request);
>> + if (voltage_swing = VOLTAGE_LEVEL_3 ||
>> + pre_emphasis = PRE_EMPHASIS_LEVEL_3) {
>> + dev_err(dp->dev, "voltage or pre emphasis reached max level\n");
>> + goto reduce_link_rate;
>> + }
>>
>> - for (lane = 0; lane < lane_count; lane++) {
>> - exynos_dp_set_lane_link_training(dp,
>> - dp->link_train.training_lane[lane],
>> - lane);
>> - buf[lane] = dp->link_train.training_lane[lane];
>> - exynos_dp_write_byte_to_dpcd(dp,
>> - DPCD_ADDR_TRAINING_LANE0_SET + lane,
>> - buf[lane]);
>> + if ((DPCD_VOLTAGE_SWING_GET(training_lane) =
>> + voltage_swing) &&
>> + (DPCD_PRE_EMPHASIS_GET(training_lane) =
>> + pre_emphasis)) {
>> + dp->link_train.cr_loop[lane]++;
>> + if (dp->link_train.cr_loop[lane] = MAX_CR_LOOP) {
>> + dev_err(dp->dev, "CR Max loop\n");
>> + goto reduce_link_rate;
>> + }
>> }
>> +
>> + training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
>> + DPCD_PRE_EMPHASIS_SET(pre_emphasis);
>> +
>> + if (voltage_swing = VOLTAGE_LEVEL_3)
>> + training_lane |= DPCD_MAX_SWING_REACHED;
>> + if (pre_emphasis = PRE_EMPHASIS_LEVEL_3)
>> + training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
>> +
>> + dp->link_train.training_lane[lane] = training_lane;
>> +
>> + exynos_dp_set_lane_link_training(dp,
>> + dp->link_train.training_lane[lane], lane);
>> }
>> +
>> + exynos_dp_write_bytes_to_dpcd(dp,
>> + DPCD_ADDR_TRAINING_LANE0_SET,
>> + lane_count,
>> + dp->link_train.training_lane);
>> }
>>
>> return 0;
>> +
>> +reduce_link_rate:
>> + exynos_dp_reduce_link_rate(dp);
>> + return -EIO;
>> }
>>
>> static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>> {
>> - u8 link_status[6];
>> + u8 link_status[2];
>> + u8 link_align[3];
>> int lane;
>> int lane_count;
>> - u8 buf[5];
>> u32 reg;
>>
>> u8 adjust_request[2];
>> + u8 voltage_swing;
>> + u8 pre_emphasis;
>> + u8 training_lane;
>>
>> usleep_range(400, 401);
>>
>> - exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
>> - 6, link_status);
>> lane_count = dp->link_train.lane_count;
>>
>> + exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
>> + 2, link_status);
>> +
>> if (exynos_dp_clock_recovery_ok(link_status, lane_count) = 0) {
>> - adjust_request[0] = link_status[4];
>> - adjust_request[1] = link_status[5];
>> + link_align[0] = link_status[0];
>> + link_align[1] = link_status[1];
>> +
>> + exynos_dp_read_byte_from_dpcd(dp,
>> + DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED,
>> + &link_align[2]);
>> +
>> + for (lane = 0; lane < lane_count; lane++) {
>> + exynos_dp_read_bytes_from_dpcd(dp,
>> + DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
>> + 2, adjust_request);
>> + voltage_swing = exynos_dp_get_adjust_request_voltage(
>> + adjust_request, lane);
>> + pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
>> + adjust_request, lane);
>> + training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
>> + DPCD_PRE_EMPHASIS_SET(pre_emphasis);
>> +
>> + if (voltage_swing = VOLTAGE_LEVEL_3)
>> + training_lane |= DPCD_MAX_SWING_REACHED;
>> + if (pre_emphasis = PRE_EMPHASIS_LEVEL_3)
>> + training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
>> +
>> + dp->link_train.training_lane[lane] = training_lane;
>> + }
>>
>> if (exynos_dp_channel_eq_ok(link_status, lane_count) = 0) {
>> /* traing pattern Set to Normal */
>> @@ -596,39 +599,42 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
>> dp->link_train.lane_count = reg;
>> dev_dbg(dp->dev, "final lane count = %.2x\n",
>> dp->link_train.lane_count);
>> +
>> /* set enhanced mode if available */
>> exynos_dp_set_enhanced_mode(dp);
>> -
>> dp->link_train.lt_state = FINISHED;
>> } else {
>> /* not all locked */
>> dp->link_train.eq_loop++;
>>
>> if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
>> - exynos_dp_reduce_link_rate(dp);
>> - } else {
>> - exynos_dp_get_adjust_train(dp, adjust_request);
>> -
>> - for (lane = 0; lane < lane_count; lane++) {
>> - exynos_dp_set_lane_link_training(dp,
>> - dp->link_train.training_lane[lane],
>> - lane);
>> - buf[lane] = dp->link_train.training_lane[lane];
>> - exynos_dp_write_byte_to_dpcd(dp,
>> - DPCD_ADDR_TRAINING_LANE0_SET + lane,
>> - buf[lane]);
>> - }
>> + dev_err(dp->dev, "EQ Max loop\n");
>> + goto reduce_link_rate;
>> }
>> +
>> + for (lane = 0; lane < lane_count; lane++)
>> + exynos_dp_set_lane_link_training(dp,
>> + dp->link_train.training_lane[lane],
>> + lane);
>> +
>> + exynos_dp_write_bytes_to_dpcd(dp,
>> + DPCD_ADDR_TRAINING_LANE0_SET,
>> + lane_count,
>> + dp->link_train.training_lane);
>> }
>> } else {
>> - exynos_dp_reduce_link_rate(dp);
>> + goto reduce_link_rate;
>> }
>>
>> return 0;
>> +
>> +reduce_link_rate:
>> + exynos_dp_reduce_link_rate(dp);
>> + return -EIO;
>> }
>>
>> static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
>> - u8 *bandwidth)
>> + u8 *bandwidth)
>> {
>> u8 data;
>>
>> @@ -641,7 +647,7 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
>> }
>>
>> static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
>> - u8 *lane_count)
>> + u8 *lane_count)
>> {
>> u8 data;
>>
>> @@ -693,13 +699,7 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
>> static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
>> {
>> int retval = 0;
>> - int training_finished;
>> -
>> - /* Turn off unnecessary lane */
>> - if (dp->link_train.lane_count = 1)
>> - exynos_dp_set_analog_power_down(dp, CH1_BLOCK, 1);
>> -
>> - training_finished = 0;
>> + int training_finished = 0;
>>
>> dp->link_train.lt_state = START;
>>
>> @@ -710,10 +710,14 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
>> exynos_dp_link_start(dp);
>> break;
>> case CLOCK_RECOVERY:
>> - exynos_dp_process_clock_recovery(dp);
>> + retval = exynos_dp_process_clock_recovery(dp);
>> + if (retval)
>> + dev_err(dp->dev, "LT CR failed!\n");
>> break;
>> case EQUALIZER_TRAINING:
>> - exynos_dp_process_equalizer_training(dp);
>> + retval = exynos_dp_process_equalizer_training(dp);
>> + if (retval)
>> + dev_err(dp->dev, "LT EQ failed!\n");
>> break;
>> case FINISHED:
>> training_finished = 1;
>> diff --git a/drivers/video/exynos/exynos_dp_core.h b/drivers/video/exynos/exynos_dp_core.h
>> index 8526e54..44c11e1 100644
>> --- a/drivers/video/exynos/exynos_dp_core.h
>> +++ b/drivers/video/exynos/exynos_dp_core.h
>> @@ -144,7 +144,7 @@ void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
>> #define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
>> #define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
>> #define DPCD_ADDR_LANE0_1_STATUS 0x0202
>> -#define DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED 0x0204
>> +#define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x0204
>> #define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
>> #define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
>> #define DPCD_ADDR_TEST_REQUEST 0x0218
>> --
>> 1.7.1
>
>
>
^ permalink raw reply
* Re: [PATCH] video: exynos_dp: adjust voltage swing and pre-emphasis during Link Training
From: Jingoo Han @ 2012-07-30 4:08 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <001101cd656a$5ea25c90$1be715b0$%han@samsung.com>
On Thursday, July 19, 2012 1:53 PM, Jingoo Han wrote:
>
> This patch adds adjustement for voltage swing and pre-emphasis during
> Link Training procedure. According to the DP specification, unless all
> the LANEx_CR_DONE bits are set, the transmitter must read
> the ADJUST_REQUEST_LANEx_x, increase the voltage swing according to
> the request, and update the TRAINING_LANEx_SET bytes to match the new
> voltage swing setting.
>
> Refer to the DP specification v1.1a, Section 3.5.1.3 Link Training.
>
> Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Hi Florian,
Could you accept this patch for 3.6-rc1?
This patch was already verified and tested with different 2 kinds of eDP LCD panels.
Thank you.
Best regards,
Jingoo Han
> ---
> drivers/video/exynos/exynos_dp_core.c | 282 +++++++++++++++++----------------
> drivers/video/exynos/exynos_dp_core.h | 2 +-
> 2 files changed, 144 insertions(+), 140 deletions(-)
>
> diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c
> index c6c016a..9c0140f 100644
> --- a/drivers/video/exynos/exynos_dp_core.c
> +++ b/drivers/video/exynos/exynos_dp_core.c
> @@ -260,7 +260,7 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
>
> static void exynos_dp_link_start(struct exynos_dp_device *dp)
> {
> - u8 buf[5];
> + u8 buf[4];
> int lane;
> int lane_count;
>
> @@ -295,10 +295,10 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp)
> exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
>
> /* Set RX training pattern */
> - buf[0] = DPCD_SCRAMBLING_DISABLED |
> - DPCD_TRAINING_PATTERN_1;
> exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TRAINING_PATTERN_SET, buf[0]);
> + DPCD_ADDR_TRAINING_PATTERN_SET,
> + DPCD_SCRAMBLING_DISABLED |
> + DPCD_TRAINING_PATTERN_1);
>
> for (lane = 0; lane < lane_count; lane++)
> buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
> @@ -308,7 +308,7 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp)
> lane_count, buf);
> }
>
> -static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
> +static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
> {
> int shift = (lane & 1) * 4;
> u8 link_value = link_status[lane>>1];
> @@ -316,7 +316,7 @@ static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
> return (link_value >> shift) & 0xf;
> }
>
> -static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
> +static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
> {
> int lane;
> u8 lane_status;
> @@ -329,22 +329,23 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
> return 0;
> }
>
> -static int exynos_dp_channel_eq_ok(u8 link_status[6], int lane_count)
> +static int exynos_dp_channel_eq_ok(u8 link_align[3], int lane_count)
> {
> int lane;
> u8 lane_align;
> u8 lane_status;
>
> - lane_align = link_status[2];
> + lane_align = link_align[2];
> if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) = 0)
> return -EINVAL;
>
> for (lane = 0; lane < lane_count; lane++) {
> - lane_status = exynos_dp_get_lane_status(link_status, lane);
> + lane_status = exynos_dp_get_lane_status(link_align, lane);
> lane_status &= DPCD_CHANNEL_EQ_BITS;
> if (lane_status != DPCD_CHANNEL_EQ_BITS)
> return -EINVAL;
> }
> +
> return 0;
> }
>
> @@ -417,69 +418,17 @@ static unsigned int exynos_dp_get_lane_link_training(
>
> static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
> {
> - if (dp->link_train.link_rate = LINK_RATE_2_70GBPS) {
> - /* set to reduced bit rate */
> - dp->link_train.link_rate = LINK_RATE_1_62GBPS;
> - dev_err(dp->dev, "set to bandwidth %.2x\n",
> - dp->link_train.link_rate);
> - dp->link_train.lt_state = START;
> - } else {
> - exynos_dp_training_pattern_dis(dp);
> - /* set enhanced mode if available */
> - exynos_dp_set_enhanced_mode(dp);
> - dp->link_train.lt_state = FAILED;
> - }
> -}
> -
> -static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp,
> - u8 adjust_request[2])
> -{
> - int lane;
> - int lane_count;
> - u8 voltage_swing;
> - u8 pre_emphasis;
> - u8 training_lane;
> + exynos_dp_training_pattern_dis(dp);
> + exynos_dp_set_enhanced_mode(dp);
>
> - lane_count = dp->link_train.lane_count;
> - for (lane = 0; lane < lane_count; lane++) {
> - voltage_swing = exynos_dp_get_adjust_request_voltage(
> - adjust_request, lane);
> - pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
> - adjust_request, lane);
> - training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
> - DPCD_PRE_EMPHASIS_SET(pre_emphasis);
> -
> - if (voltage_swing = VOLTAGE_LEVEL_3 ||
> - pre_emphasis = PRE_EMPHASIS_LEVEL_3) {
> - training_lane |= DPCD_MAX_SWING_REACHED;
> - training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
> - }
> - dp->link_train.training_lane[lane] = training_lane;
> - }
> -}
> -
> -static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp,
> - u8 voltage_swing)
> -{
> - int lane;
> - int lane_count;
> -
> - lane_count = dp->link_train.lane_count;
> - for (lane = 0; lane < lane_count; lane++) {
> - if (voltage_swing = VOLTAGE_LEVEL_3 ||
> - dp->link_train.cr_loop[lane] = MAX_CR_LOOP)
> - return -EINVAL;
> - }
> - return 0;
> + dp->link_train.lt_state = FAILED;
> }
>
> static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
> {
> - u8 data;
> - u8 link_status[6];
> + u8 link_status[2];
> int lane;
> int lane_count;
> - u8 buf[5];
>
> u8 adjust_request[2];
> u8 voltage_swing;
> @@ -488,98 +437,152 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
>
> usleep_range(100, 101);
>
> - exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
> - 6, link_status);
> lane_count = dp->link_train.lane_count;
>
> + exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
> + 2, link_status);
> +
> if (exynos_dp_clock_recovery_ok(link_status, lane_count) = 0) {
> /* set training pattern 2 for EQ */
> exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
>
> - adjust_request[0] = link_status[4];
> - adjust_request[1] = link_status[5];
> + for (lane = 0; lane < lane_count; lane++) {
> + exynos_dp_read_bytes_from_dpcd(dp,
> + DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
> + 2, adjust_request);
> + voltage_swing = exynos_dp_get_adjust_request_voltage(
> + adjust_request, lane);
> + pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
> + adjust_request, lane);
> + training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
> + DPCD_PRE_EMPHASIS_SET(pre_emphasis);
>
> - exynos_dp_get_adjust_train(dp, adjust_request);
> + if (voltage_swing = VOLTAGE_LEVEL_3)
> + training_lane |= DPCD_MAX_SWING_REACHED;
> + if (pre_emphasis = PRE_EMPHASIS_LEVEL_3)
> + training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
>
> - buf[0] = DPCD_SCRAMBLING_DISABLED |
> - DPCD_TRAINING_PATTERN_2;
> - exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TRAINING_PATTERN_SET,
> - buf[0]);
> + dp->link_train.training_lane[lane] = training_lane;
>
> - for (lane = 0; lane < lane_count; lane++) {
> exynos_dp_set_lane_link_training(dp,
> dp->link_train.training_lane[lane],
> lane);
> - buf[lane] = dp->link_train.training_lane[lane];
> - exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TRAINING_LANE0_SET + lane,
> - buf[lane]);
> }
> - dp->link_train.lt_state = EQUALIZER_TRAINING;
> - } else {
> - exynos_dp_read_byte_from_dpcd(dp,
> - DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
> - &data);
> - adjust_request[0] = data;
>
> - exynos_dp_read_byte_from_dpcd(dp,
> - DPCD_ADDR_ADJUST_REQUEST_LANE2_3,
> - &data);
> - adjust_request[1] = data;
> + exynos_dp_write_byte_to_dpcd(dp,
> + DPCD_ADDR_TRAINING_PATTERN_SET,
> + DPCD_SCRAMBLING_DISABLED |
> + DPCD_TRAINING_PATTERN_2);
> +
> + exynos_dp_write_bytes_to_dpcd(dp,
> + DPCD_ADDR_TRAINING_LANE0_SET,
> + lane_count,
> + dp->link_train.training_lane);
>
> + dev_info(dp->dev, "Link Training Clock Recovery success\n");
> + dp->link_train.lt_state = EQUALIZER_TRAINING;
> + } else {
> for (lane = 0; lane < lane_count; lane++) {
> training_lane = exynos_dp_get_lane_link_training(
> dp, lane);
> + exynos_dp_read_bytes_from_dpcd(dp,
> + DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
> + 2, adjust_request);
> voltage_swing = exynos_dp_get_adjust_request_voltage(
> adjust_request, lane);
> pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
> adjust_request, lane);
> - if ((DPCD_VOLTAGE_SWING_GET(training_lane) = voltage_swing) &&
> - (DPCD_PRE_EMPHASIS_GET(training_lane) = pre_emphasis))
> - dp->link_train.cr_loop[lane]++;
> - dp->link_train.training_lane[lane] = training_lane;
> - }
>
> - if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) {
> - exynos_dp_reduce_link_rate(dp);
> - } else {
> - exynos_dp_get_adjust_train(dp, adjust_request);
> + if (voltage_swing = VOLTAGE_LEVEL_3 ||
> + pre_emphasis = PRE_EMPHASIS_LEVEL_3) {
> + dev_err(dp->dev, "voltage or pre emphasis reached max level\n");
> + goto reduce_link_rate;
> + }
>
> - for (lane = 0; lane < lane_count; lane++) {
> - exynos_dp_set_lane_link_training(dp,
> - dp->link_train.training_lane[lane],
> - lane);
> - buf[lane] = dp->link_train.training_lane[lane];
> - exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TRAINING_LANE0_SET + lane,
> - buf[lane]);
> + if ((DPCD_VOLTAGE_SWING_GET(training_lane) =
> + voltage_swing) &&
> + (DPCD_PRE_EMPHASIS_GET(training_lane) =
> + pre_emphasis)) {
> + dp->link_train.cr_loop[lane]++;
> + if (dp->link_train.cr_loop[lane] = MAX_CR_LOOP) {
> + dev_err(dp->dev, "CR Max loop\n");
> + goto reduce_link_rate;
> + }
> }
> +
> + training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
> + DPCD_PRE_EMPHASIS_SET(pre_emphasis);
> +
> + if (voltage_swing = VOLTAGE_LEVEL_3)
> + training_lane |= DPCD_MAX_SWING_REACHED;
> + if (pre_emphasis = PRE_EMPHASIS_LEVEL_3)
> + training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
> +
> + dp->link_train.training_lane[lane] = training_lane;
> +
> + exynos_dp_set_lane_link_training(dp,
> + dp->link_train.training_lane[lane], lane);
> }
> +
> + exynos_dp_write_bytes_to_dpcd(dp,
> + DPCD_ADDR_TRAINING_LANE0_SET,
> + lane_count,
> + dp->link_train.training_lane);
> }
>
> return 0;
> +
> +reduce_link_rate:
> + exynos_dp_reduce_link_rate(dp);
> + return -EIO;
> }
>
> static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
> {
> - u8 link_status[6];
> + u8 link_status[2];
> + u8 link_align[3];
> int lane;
> int lane_count;
> - u8 buf[5];
> u32 reg;
>
> u8 adjust_request[2];
> + u8 voltage_swing;
> + u8 pre_emphasis;
> + u8 training_lane;
>
> usleep_range(400, 401);
>
> - exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
> - 6, link_status);
> lane_count = dp->link_train.lane_count;
>
> + exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
> + 2, link_status);
> +
> if (exynos_dp_clock_recovery_ok(link_status, lane_count) = 0) {
> - adjust_request[0] = link_status[4];
> - adjust_request[1] = link_status[5];
> + link_align[0] = link_status[0];
> + link_align[1] = link_status[1];
> +
> + exynos_dp_read_byte_from_dpcd(dp,
> + DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED,
> + &link_align[2]);
> +
> + for (lane = 0; lane < lane_count; lane++) {
> + exynos_dp_read_bytes_from_dpcd(dp,
> + DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
> + 2, adjust_request);
> + voltage_swing = exynos_dp_get_adjust_request_voltage(
> + adjust_request, lane);
> + pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
> + adjust_request, lane);
> + training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
> + DPCD_PRE_EMPHASIS_SET(pre_emphasis);
> +
> + if (voltage_swing = VOLTAGE_LEVEL_3)
> + training_lane |= DPCD_MAX_SWING_REACHED;
> + if (pre_emphasis = PRE_EMPHASIS_LEVEL_3)
> + training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
> +
> + dp->link_train.training_lane[lane] = training_lane;
> + }
>
> if (exynos_dp_channel_eq_ok(link_status, lane_count) = 0) {
> /* traing pattern Set to Normal */
> @@ -596,39 +599,42 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
> dp->link_train.lane_count = reg;
> dev_dbg(dp->dev, "final lane count = %.2x\n",
> dp->link_train.lane_count);
> +
> /* set enhanced mode if available */
> exynos_dp_set_enhanced_mode(dp);
> -
> dp->link_train.lt_state = FINISHED;
> } else {
> /* not all locked */
> dp->link_train.eq_loop++;
>
> if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
> - exynos_dp_reduce_link_rate(dp);
> - } else {
> - exynos_dp_get_adjust_train(dp, adjust_request);
> -
> - for (lane = 0; lane < lane_count; lane++) {
> - exynos_dp_set_lane_link_training(dp,
> - dp->link_train.training_lane[lane],
> - lane);
> - buf[lane] = dp->link_train.training_lane[lane];
> - exynos_dp_write_byte_to_dpcd(dp,
> - DPCD_ADDR_TRAINING_LANE0_SET + lane,
> - buf[lane]);
> - }
> + dev_err(dp->dev, "EQ Max loop\n");
> + goto reduce_link_rate;
> }
> +
> + for (lane = 0; lane < lane_count; lane++)
> + exynos_dp_set_lane_link_training(dp,
> + dp->link_train.training_lane[lane],
> + lane);
> +
> + exynos_dp_write_bytes_to_dpcd(dp,
> + DPCD_ADDR_TRAINING_LANE0_SET,
> + lane_count,
> + dp->link_train.training_lane);
> }
> } else {
> - exynos_dp_reduce_link_rate(dp);
> + goto reduce_link_rate;
> }
>
> return 0;
> +
> +reduce_link_rate:
> + exynos_dp_reduce_link_rate(dp);
> + return -EIO;
> }
>
> static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
> - u8 *bandwidth)
> + u8 *bandwidth)
> {
> u8 data;
>
> @@ -641,7 +647,7 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
> }
>
> static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
> - u8 *lane_count)
> + u8 *lane_count)
> {
> u8 data;
>
> @@ -693,13 +699,7 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp,
> static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
> {
> int retval = 0;
> - int training_finished;
> -
> - /* Turn off unnecessary lane */
> - if (dp->link_train.lane_count = 1)
> - exynos_dp_set_analog_power_down(dp, CH1_BLOCK, 1);
> -
> - training_finished = 0;
> + int training_finished = 0;
>
> dp->link_train.lt_state = START;
>
> @@ -710,10 +710,14 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
> exynos_dp_link_start(dp);
> break;
> case CLOCK_RECOVERY:
> - exynos_dp_process_clock_recovery(dp);
> + retval = exynos_dp_process_clock_recovery(dp);
> + if (retval)
> + dev_err(dp->dev, "LT CR failed!\n");
> break;
> case EQUALIZER_TRAINING:
> - exynos_dp_process_equalizer_training(dp);
> + retval = exynos_dp_process_equalizer_training(dp);
> + if (retval)
> + dev_err(dp->dev, "LT EQ failed!\n");
> break;
> case FINISHED:
> training_finished = 1;
> diff --git a/drivers/video/exynos/exynos_dp_core.h b/drivers/video/exynos/exynos_dp_core.h
> index 8526e54..44c11e1 100644
> --- a/drivers/video/exynos/exynos_dp_core.h
> +++ b/drivers/video/exynos/exynos_dp_core.h
> @@ -144,7 +144,7 @@ void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
> #define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
> #define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
> #define DPCD_ADDR_LANE0_1_STATUS 0x0202
> -#define DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED 0x0204
> +#define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x0204
> #define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
> #define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
> #define DPCD_ADDR_TEST_REQUEST 0x0218
> --
> 1.7.1
^ permalink raw reply
* Re: Gethering power management/policy hw drivers under drivers/power/? (Re: [RFC][PATCH v3 1/3] runt
From: 함명주 @ 2012-07-30 3:04 UTC (permalink / raw)
To: Anton Vorontsov, Alex Courbot, Jean Pihet
Cc: Greg Kroah-Hartman, David Woodhouse, Stephen Warren,
Thierry Reding, Simon Glass, Grant Likely, Rob Herring,
Mark Brown, Arnd Bergmann,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
Liam Girdwood, Rafael J. Wysocki,
linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20120730024049.GA10442@lizard>
PiBPbiBNb24sIEp1bCAzMCwgMjAxMiBhdCAxMDo1MTo0MkFNICswOTAwLCBBbGV4IENvdXJib3Qg
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bGluZyBkcml2ZXIganVzdCBhcHBlYXJlZCBpbiBkcml2ZXJzL3Bvd2VyL2F2cy4NCj4gPiBTbyBp
ZiBBbnRvbiBhbmQgRGF2aWQgYXJlIG9rIHdpdGggdGhpcywgbWF5YmUgSSBjb3VsZCBwdXQgdGhl
IHBvd2VyDQo+ID4gc2VxdWVuY2VzIGNvZGUgaW4gaXRzIG93biBzdWJkaXJlY3Rvcnkgd2l0aGlu
IGRyaXZlcnMvcG93ZXIuDQo+IA0KPiBXZWxsLCBjdXJyZW50bHkgZHJpdmVycy9wb3dlci8gaXMg
aW5kZWVkIGp1c3QgZm9yIHBvd2VyIHN1cHBseSBjbGFzcw0KPiBzdWJzeXN0ZW0gYW5kIGRyaXZl
cnMuIEJ1dCBpZiB0aGUgdHJlbmQgaXMgdG8gZ2F0aGVyIHBvd2VyIG1hbmFnZW1lbnQNCj4gKCJw
b2xpY3kiKSBzdHVmZiB1bmRlciBvbmUgZGlyZWN0b3J5LCBpLmUuDQo+IA0KPiBkcml2ZXJzLw0K
PiAgIHBvd2VyLw0KPiAgICAgc3VwcGxpZXMvICAgIDwtIGZvcm1lciAicG93ZXIgc3VwcGx5IGNs
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cHVpZGxlLw0KPiAgICAgY3B1ZnJlcS8NCj4gICAgIGRldmZyZXEvDQo+ICAgICBhdnMvDQo+ICAg
ICAuLi4NCj4gDQo+IFRoYXQgd291bGQgcHJvYmFibHkgbWFrZSBzZW5zZSwgd2UgY291bGQgZWFz
aWx5IHNlZSB0aGUgYmlnIHBpY3R1cmUuDQo+IEJ1dCBpZiB3ZSdyZSBub3QgZ29pbmcgdG8gZG8g
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IGRpcmVjdG9yeSB1bmRlciBkcml2ZXJzIChhbmQgbW92ZSBkcml2ZXJzL3Bvd2VyL2F2cy8gdG8N
Cj4gZHJpdmVycy9hdnMpLg0KPiANCj4gQ2MnaW5nIHNvbWUgbW9yZSBwZW9wbGUuLi4NCj4gDQo+
IFRoYW5rcywNCj4gDQo+IHAucy4gSmVhbiwgd2h5IGFtIEkgdGhlIGxhc3QgcGVyc29uIHdobyBk
aXNjb3ZlcnMgZHJpdmVycy9wb3dlci9hdnMvPw0KPiBXb3VsZCBiZSBuaWNlIHRvIENjIG1lIG9u
IHN1Y2ggcGF0Y2hlczsgYnkgbW92aW5nIEFWUyB1bmRlcg0KPiBkcml2ZXJzL3Bvd2VyLyB5b3Ug
ZWZmZWN0aXZlbHkgbm9taW5hdGVkIG1lIGFzIGl0cyBtYWludGFpbmVyLiA6LSkNCj4gDQo+IC0t
IA0KPiBBbnRvbiBWb3JvbnRzb3YNCj4gRW1haWw6IGNib3VhdG1haWxydUBnbWFpbC5jb20NCj4g
DQoNCkhhdmluZyBwb3dlci1zdXBwbGllcyBhdCAvZHJpdmVycy9wb3dlci8gYW5kIG90aGVyIHBv
d2VyLXJlbGF0ZWQgZHJpdmVycyBzcHJlYWQgYXQgL2RyaXZlcnMvIGhhdmUgYmVlbiBidWdnaW5n
IG1lIGFzIHdlbGwuIEknZCBsaWtlIHRvIHNlZSB0aGUgY2hhbmdlIHlvdSd2ZSBzdWdnZXN0ZWQg
dGhvdWdoIEknbSBub3Qgc3VyZSBob3cgc2lnbmlmaWNhbnQgdGhlIHNpZGUtZWZmZWN0IHdpbGwg
YmUgYXQgdGhpcyBwb2ludC4NCg0KR2VuZXJhbGx5IHNwZWFraW5nLCB5ZXMsIEkgYWxzbyB0aGlu
ayB0aGUgcHJvcG9zYWwgaXMgbW9yZSByZWFzb25hYmxlIHRoYW4gdGhlIGN1cnJlbnQgc3RydWN0
dXJlLg0KDQoNCg0KQ2hlZXJzIQ0KTXl1bmdKb28NCg0KDQo
^ permalink raw reply
* Gethering power management/policy hw drivers under drivers/power/? (Re: [RFC][PATCH v3 1/3] runtime
From: Anton Vorontsov @ 2012-07-30 2:40 UTC (permalink / raw)
To: Alex Courbot, Jean Pihet
Cc: Greg Kroah-Hartman, David Woodhouse, Stephen Warren,
Thierry Reding, Simon Glass, Grant Likely, Rob Herring,
Mark Brown, Arnd Bergmann, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-fbdev@vger.kernel.org,
devicetree-discuss@lists.ozlabs.org, Liam Girdwood, MyungJoo Ham,
Rafael J. Wysocki, linux-pm
In-Reply-To: <5015E8AE.8060404@nvidia.com>
On Mon, Jul 30, 2012 at 10:51:42AM +0900, Alex Courbot wrote:
[...]
> On the other hand I have just noticed that the apparently unrelated
> Adaptive Voltage Scaling driver just appeared in drivers/power/avs.
> So if Anton and David are ok with this, maybe I could put the power
> sequences code in its own subdirectory within drivers/power.
Well, currently drivers/power/ is indeed just for power supply class
subsystem and drivers. But if the trend is to gather power management
("policy") stuff under one directory, i.e.
drivers/
power/
supplies/ <- former "power supply class and drivers"
regulators/
idle/
cpuidle/
cpufreq/
devfreq/
avs/
...
That would probably make sense, we could easily see the big picture.
But if we're not going to do this long-term, I would suggest to stick
to just a new directory under drivers (and move drivers/power/avs/ to
drivers/avs).
Cc'ing some more people...
Thanks,
p.s. Jean, why am I the last person who discovers drivers/power/avs/?
Would be nice to Cc me on such patches; by moving AVS under
drivers/power/ you effectively nominated me as its maintainer. :-)
--
Anton Vorontsov
Email: cbouatmailru@gmail.com
^ permalink raw reply
* Re: [RFC][PATCH v3 1/3] runtime interpreted power sequences
From: Alex Courbot @ 2012-07-30 1:51 UTC (permalink / raw)
To: Greg Kroah-Hartman, Anton Vorontsov, David Woodhouse
Cc: Stephen Warren, Thierry Reding, Simon Glass, Grant Likely,
Rob Herring, Mark Brown, Arnd Bergmann,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
In-Reply-To: <20120727181923.GB23564-U8xfFu+wG4EAvxtiuMwx3w@public.gmane.org>
On 07/28/2012 03:19 AM, Greg Kroah-Hartman wrote:
> On Fri, Jul 27, 2012 at 09:05:48PM +0900, Alexandre Courbot wrote:
>> Some device drivers (panel backlights especially) need to follow precise
>> sequences for powering on and off, involving gpios, regulators, PWMs
>> with a precise powering order and delays to respect between each steps.
>> These sequences are board-specific, and do not belong to a particular
>> driver - therefore they have been performed by board-specific hook
>> functions to far.
>>
>> With the advent of the device tree and of ARM kernels that are not
>> board-tied, we cannot rely on these board-specific hooks anymore but
>> need a way to implement these sequences in a portable manner. This patch
>> introduces a simple interpreter that can execute such power sequences
>> encoded either as platform data or within the device tree.
>>
>> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
>> ---
>> Documentation/power/power_seq.txt | 120 +++++++++++++++
>> drivers/base/Kconfig | 4 +
>> drivers/base/Makefile | 1 +
>> drivers/base/power_seq.c | 300 ++++++++++++++++++++++++++++++++++++++
>> include/linux/power_seq.h | 139 ++++++++++++++++++
>
> What's wrong with drivers/power/? I sure don't want to maintain this
> code, and it seems to not be part of the "driver core" infrastructure.
I thought about drivers/power/ initially, but quickly realized it was
only about the power supply class and its drivers - so I felt like it
would be out of place there, as the power sequences have nothing to do
with power supply but instead control gpios, regulators and pwms.
On the other hand I have just noticed that the apparently unrelated
Adaptive Voltage Scaling driver just appeared in drivers/power/avs. So
if Anton and David are ok with this, maybe I could put the power
sequences code in its own subdirectory within drivers/power.
Thanks,
Alex.
^ permalink raw reply
* Re: [PATCH] fbdev: sh_mobile_lcdc: Fix vertical panning step
From: Kuninori Morimoto @ 2012-07-30 1:25 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <1343306215-20868-1-git-send-email-laurent.pinchart@ideasonboard.com>
Hi Laurent
> diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c
> index 8cb653b..699487c 100644
> --- a/drivers/video/sh_mobile_lcdcfb.c
> +++ b/drivers/video/sh_mobile_lcdcfb.c
> @@ -1716,11 +1716,11 @@ sh_mobile_lcdc_overlay_fb_init(struct sh_mobile_lcdc_overlay *ovl)
> info->fix.visual = FB_VISUAL_TRUECOLOR;
>
> switch (ovl->format->fourcc) {
> - case V4L2_PIX_FMT_NV16:
> - case V4L2_PIX_FMT_NV61:
> - info->fix.ypanstep = 2;
> case V4L2_PIX_FMT_NV12:
> case V4L2_PIX_FMT_NV21:
> + info->fix.ypanstep = 2;
> + case V4L2_PIX_FMT_NV16:
> + case V4L2_PIX_FMT_NV61:
> info->fix.xpanstep = 2;
> }
>
> @@ -2215,11 +2215,11 @@ sh_mobile_lcdc_channel_fb_init(struct sh_mobile_lcdc_chan *ch,
> info->fix.visual = FB_VISUAL_TRUECOLOR;
>
> switch (ch->format->fourcc) {
> - case V4L2_PIX_FMT_NV16:
> - case V4L2_PIX_FMT_NV61:
> - info->fix.ypanstep = 2;
> case V4L2_PIX_FMT_NV12:
> case V4L2_PIX_FMT_NV21:
> + info->fix.ypanstep = 2;
> + case V4L2_PIX_FMT_NV16:
> + case V4L2_PIX_FMT_NV61:
> info->fix.xpanstep = 2;
> }
If possible, could you please add comment /* fall through */ ?
current code is a little bit confusing
Best regards
---
Kuninori Morimoto
^ permalink raw reply
* Re: [PATCH v3] video: da8xx-fb: add 24bpp LCD configuration support
From: Florian Tobias Schandinat @ 2012-07-29 21:37 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <1342712266-4381-1-git-send-email-prakash.pm@ti.com>
Hi,
On 07/23/2012 08:26 AM, Manjunathappa, Prakash wrote:
> Hi,
>
> On Thu, Jul 19, 2012 at 21:07:46, Manjunathappa, Prakash wrote:
>> LCD controller on am335x supports 24bpp raster configuration in addition
>> to ones on da850. LCDC also supports 24bpp in unpacked format having
>> ARGB:8888 32bpp format data in DDR, but it doesn't interpret alpha
>> component of the data.
>>
>> Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
>> Cc: Anatolij Gustschin <agust@denx.de>
>> ---
>> Since v2:
>> Fixed additional configurations for 24bpp support.
>> Since v1:
>> Simplified calculation of pseudopalette for FB_VISUAL_TRUECOLOR type.
>>
>> drivers/video/da8xx-fb.c | 127 ++++++++++++++++++++++++++++++++++------------
>> 1 files changed, 94 insertions(+), 33 deletions(-)
>>
>> diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
>> index 47118c7..3d2d0d1 100644
>> --- a/drivers/video/da8xx-fb.c
>> +++ b/drivers/video/da8xx-fb.c
>> @@ -83,6 +83,8 @@
>> #define LCD_V2_LIDD_CLK_EN BIT(1)
>> #define LCD_V2_CORE_CLK_EN BIT(0)
>> #define LCD_V2_LPP_B10 26
>> +#define LCD_V2_TFT_24BPP_MODE BIT(25)
>> +#define LCD_V2_TFT_24BPP_UNPACK BIT(26)
>>
>> /* LCD Raster Timing 2 Register */
>> #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
>> @@ -153,7 +155,7 @@ struct da8xx_fb_par {
>> unsigned int dma_end;
>> struct clk *lcdc_clk;
>> int irq;
>> - unsigned short pseudo_palette[16];
>> + unsigned long pseudo_palette[16];
>
> I am still not convinced as sizes of "unsigned long" and "unsigned int" are not
> guaranteed to be 32bit across platforms and compilers, so planning to retain u32.
Yes, if you want something that is always 32 bit you probably should use
u32, that is at least more obvious.
There are a few guarantees in C like
sizeof(short)<=sizeof(int)<=sizeof(long) and short at least being 16
bits and long at least 32 bits that any standard compliant compiler
should honor. And if you limit it to a specific platform/CPU even more
may be assured. But if you want to highlight that you always want to use
32bit u32 is the best choice.
>
> Florian Tobias Schandinat,
> Can you please comment?
Best regards,
Florian Tobias Schandinat
>
> Here is the history:
> http://marc.info/?l=linux-fbdev&m\x134259216714719&w=2
>
>> unsigned int palette_sz;
>> unsigned int pxl_clk;
>> int blank;
>> @@ -482,6 +484,9 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
>> {
>> u32 reg;
>>
>> + if ((bpp > 16) && (lcd_revision = LCD_VERSION_1))
>> + return -EINVAL;
>> +
>> /* Set the Panel Width */
>> /* Pixels per line = (PPL + 1)*16 */
>> if (lcd_revision = LCD_VERSION_1) {
>> @@ -525,6 +530,12 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
>> reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
>> if (raster_order)
>> reg |= LCD_RASTER_ORDER;
>> +
>> + if (bpp = 24)
>> + reg |= LCD_V2_TFT_24BPP_MODE;
>> + else if (bpp = 32)
>> + reg |= (LCD_V2_TFT_24BPP_MODE | LCD_V2_TFT_24BPP_UNPACK);
>> +
>> lcdc_write(reg, LCD_RASTER_CTRL_REG);
>>
>> switch (bpp) {
>> @@ -532,6 +543,8 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
>> case 2:
>> case 4:
>> case 16:
>> + case 24:
>> + case 32:
>> par->palette_sz = 16 * 2;
>> break;
>>
>> @@ -546,6 +559,8 @@ static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
>> return 0;
>> }
>>
>> +
>> +#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16)
>
> since multiple FB drivers have re-defined this macro, I will move this to common place(linux/fb.h) and
> convert it as inline function.
>
> Thanks,
> Prakash
>
>> static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
> [...]
>
^ permalink raw reply
* Re: [GIT PULL] SH Mobile LCDC and MERAM patches
From: Florian Tobias Schandinat @ 2012-07-29 21:16 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <2980452.38e8VA4mF5@avalon>
On 07/26/2012 05:26 PM, Laurent Pinchart wrote:
> Hi Florian,
>
> On Thursday 26 July 2012 17:14:33 Florian Tobias Schandinat wrote:
>> On 07/24/2012 09:16 AM, Laurent Pinchart wrote:
>>> Hi Florian,
>>>
>>> The following changes since commit
> 6fcdbc0c3a683003a00f383fceac80da1b7852ff:
>>> s3fb: Add Virge/MX (86C260) (2012-07-08 14:03:50 +0000)
>>>
>>> are available in the git repository at:
>>> git://linuxtv.org/pinchartl/fbdev.git for-next
>>
>> Merged. Should I also apply your followup patch
>> "[PATCH] fbdev: sh_mobile_lcdc: Fix vertical panning step"
>> ?
>
> I was planning to send a pull request for that one, but yes, please merge it
> :-)
Applied.
Thanks,
Florian Tobias Schandinat
^ permalink raw reply
* Re: [PATCH] fbdev: Make pixel_to_pat() failure mode more friendly
From: Florian Tobias Schandinat @ 2012-07-29 21:16 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <1343117953.3715.23.camel@pasglop>
On 07/24/2012 08:19 AM, Benjamin Herrenschmidt wrote:
> If we accidentally pass an incorrect bpp value to pixel_to_pat(),
> it panics. This is pretty useless, as we generally have the various
> console locks held at that point, so nothing will be displayed,
> and there is no reason to make this a fatal event.
>
> Let's WARN instead.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Applied.
Thanks,
Florian Tobias Schandinat
> ---
>
> diff --git a/drivers/video/fb_draw.h b/drivers/video/fb_draw.h
> index 04c01fa..624ee11 100644
> --- a/drivers/video/fb_draw.h
> +++ b/drivers/video/fb_draw.h
> @@ -3,6 +3,7 @@
>
> #include <asm/types.h>
> #include <linux/fb.h>
> +#include <linux/bug.h>
>
> /*
> * Compose two values, using a bitmask as decision value
> @@ -41,7 +42,8 @@ pixel_to_pat( u32 bpp, u32 pixel)
> case 32:
> return 0x0000000100000001ul*pixel;
> default:
> - panic("pixel_to_pat(): unsupported pixelformat\n");
> + WARN(1, "pixel_to_pat(): unsupported pixelformat %d\n", bpp);
> + return 0;
> }
> }
> #else
> @@ -66,7 +68,8 @@ pixel_to_pat( u32 bpp, u32 pixel)
> case 32:
> return 0x00000001ul*pixel;
> default:
> - panic("pixel_to_pat(): unsupported pixelformat\n");
> + WARN(1, "pixel_to_pat(): unsupported pixelformat %d\n", bpp);
> + return 0;
> }
> }
> #endif
>
>
>
^ permalink raw reply
* Re: [PATCH] da8xx-fb: do not turn ON LCD backlight unless LCDC is enabled
From: Florian Tobias Schandinat @ 2012-07-29 21:16 UTC (permalink / raw)
To: linux-fbdev
In-Reply-To: <1343103325-7313-1-git-send-email-prakash.pm@ti.com>
On 07/24/2012 04:15 AM, Manjunathappa, Prakash wrote:
> LCD blink is observed during suspend/resume and blank/unblank
> operations as backlight is ON during LCDC disable and enable.
> So make sure to turn OFF backlight before disabling and turn
> it ON after enabling.
>
> Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Applied.
Thanks,
Florian Tobias Schandinat
> ---
> drivers/video/da8xx-fb.c | 9 +++++----
> 1 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
> index 0fb4d7d..1a569ae 100644
> --- a/drivers/video/da8xx-fb.c
> +++ b/drivers/video/da8xx-fb.c
> @@ -1056,10 +1056,10 @@ static int cfb_blank(int blank, struct fb_info *info)
> par->blank = blank;
> switch (blank) {
> case FB_BLANK_UNBLANK:
> + lcd_enable_raster();
> +
> if (par->panel_power_ctrl)
> par->panel_power_ctrl(1);
> -
> - lcd_enable_raster();
> break;
> case FB_BLANK_POWERDOWN:
> if (par->panel_power_ctrl)
> @@ -1417,11 +1417,12 @@ static int fb_resume(struct platform_device *dev)
> struct da8xx_fb_par *par = info->par;
>
> console_lock();
> + clk_enable(par->lcdc_clk);
> + lcd_enable_raster();
> +
> if (par->panel_power_ctrl)
> par->panel_power_ctrl(1);
>
> - clk_enable(par->lcdc_clk);
> - lcd_enable_raster();
> fb_set_suspend(info, 0);
> console_unlock();
>
^ permalink raw reply
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