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* Re: [PATCH v2] ARM: OMAPFB: panel-sony-acx565akm: fix missing mutex unlocks
From: Ivaylo Dimitrov @ 2014-01-11  9:39 UTC (permalink / raw)
  To: Tomi Valkeinen
  Cc: plagnioj, pali.rohar, pavel, linux-omap, linux-fbdev,
	linux-kernel, Ivaylo Dimitrov, Aaro Koskinen
In-Reply-To: <52CFD1ED.7010302@ti.com>

On 10.01.2014 12:56, Tomi Valkeinen wrote:
> On 2014-01-05 15:13, Ivaylo Dimitrov wrote:
>> From: Ivaylo Dimitrov <freemangordon@abv.bg>
>>
>> Commit c37dd677988ca50bc8bc60ab5ab053720583c168 fixes the unbalanced
>> unlock in acx565akm_enable but introduces another problem - if
>> acx565akm_panel_power_on exits early, the mutex is not unlocked. Fix
>> that by unlocking the mutex on early return. Also add mutex protection in
>> acx565akm_panel_power_off and remove an unused variable
>>
>
> I think this is just getting more messy. How about we more or less revert the c37dd677988ca50bc8bc60ab5ab053720583c168 and fix it like this:
>

I am fine with whatever patch you may come with, as long as it fixes the 
issue.

>
> diff --git a/drivers/video/omap2/displays-new/panel-sony-acx565akm.c b/drivers/video/omap2/displays-new/panel-sony-acx565akm.c
> index 714ee92dfb9f..8e97d06921ff 100644
> --- a/drivers/video/omap2/displays-new/panel-sony-acx565akm.c
> +++ b/drivers/video/omap2/displays-new/panel-sony-acx565akm.c

The patch does not apply cleanly on top of rc7, however I applied it by 
hand. So far it seems it fixes the issue brought by 
c37dd677988ca50bc8bc60ab5ab053720583c168, though I didn't test if 
mutex_lock/mutex_unlock are complementary in every code path (at least 
not explicitly, I guess maemo is doing it for us anyway :) ).

So, shall I send a patch incorporating your code changes, or you will do it?

Regards,
Ivo


^ permalink raw reply

* [PATCH v5] video: add OpenCores VGA/LCD framebuffer driver
From: Stefan Kristiansson @ 2014-01-10 20:13 UTC (permalink / raw)
  To: linux-kernel, linux-fbdev; +Cc: tomi.valkeinen, plagnioj, Stefan Kristiansson

This adds support for the VGA/LCD core available from OpenCores:
http://opencores.org/project,vga_lcd

The driver have been tested together with both OpenRISC and
ARM (socfpga) processors.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
---
Changes in v2:
- Add Microblaze as an example user and fix a typo in Xilinx Zynq

Changes in v3:
- Use devm_kzalloc instead of kzalloc
- Remove superflous MODULE #ifdef

Changes in v4:
- Remove 'default n' in Kconfig
- Simplify ioremap/request_mem_region by using devm_ioremap_resource
- Remove release_mem_region

Changes in v5:
- Remove static structs to support multiple devices
---
 drivers/video/Kconfig  |  16 ++
 drivers/video/Makefile |   1 +
 drivers/video/ocfb.c   | 440 +++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 457 insertions(+)
 create mode 100644 drivers/video/ocfb.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 84b685f..8e41a1e 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -979,6 +979,22 @@ config FB_PVR2
 	  (<file:drivers/video/pvr2fb.c>). Please see the file
 	  <file:Documentation/fb/pvr2fb.txt>.
 
+config FB_OPENCORES
+	tristate "OpenCores VGA/LCD core 2.0 framebuffer support"
+	depends on FB
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	help
+	  This enables support for the OpenCores VGA/LCD core.
+
+	  The OpenCores VGA/LCD core is typically used together with
+	  softcore CPUs (e.g. OpenRISC or Microblaze) or hard processor
+	  systems (e.g. Altera socfpga or Xilinx Zynq) on FPGAs.
+
+	  The source code and specification for the core is available at
+	  <http://opencores.org/project,vga_lcd>
+
 config FB_S1D13XXX
 	tristate "Epson S1D13XXX framebuffer support"
 	depends on FB
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index e8bae8d..ae17ddf 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -150,6 +150,7 @@ obj-$(CONFIG_FB_NUC900)           += nuc900fb.o
 obj-$(CONFIG_FB_JZ4740)		  += jz4740_fb.o
 obj-$(CONFIG_FB_PUV3_UNIGFX)      += fb-puv3.o
 obj-$(CONFIG_FB_HYPERV)		  += hyperv_fb.o
+obj-$(CONFIG_FB_OPENCORES)	  += ocfb.o
 
 # Platform or fallback drivers go here
 obj-$(CONFIG_FB_UVESA)            += uvesafb.o
diff --git a/drivers/video/ocfb.c b/drivers/video/ocfb.c
new file mode 100644
index 0000000..28faa3e
--- /dev/null
+++ b/drivers/video/ocfb.c
@@ -0,0 +1,440 @@
+/*
+ * OpenCores VGA/LCD 2.0 core frame buffer driver
+ *
+ * Copyright (C) 2013 Stefan Kristiansson, stefan.kristiansson@saunalahti.fi
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/mm.h>
+#include <linux/dma-mapping.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+
+/* OCFB register defines */
+#define OCFB_CTRL	0x000
+#define OCFB_STAT	0x004
+#define OCFB_HTIM	0x008
+#define OCFB_VTIM	0x00c
+#define OCFB_HVLEN	0x010
+#define OCFB_VBARA	0x014
+#define OCFB_PALETTE	0x800
+
+#define OCFB_CTRL_VEN	0x00000001 /* Video Enable */
+#define OCFB_CTRL_HIE	0x00000002 /* HSync Interrupt Enable */
+#define OCFB_CTRL_PC	0x00000800 /* 8-bit Pseudo Color Enable*/
+#define OCFB_CTRL_CD8	0x00000000 /* Color Depth 8 */
+#define OCFB_CTRL_CD16	0x00000200 /* Color Depth 16 */
+#define OCFB_CTRL_CD24	0x00000400 /* Color Depth 24 */
+#define OCFB_CTRL_CD32	0x00000600 /* Color Depth 32 */
+#define OCFB_CTRL_VBL1	0x00000000 /* Burst Length 1 */
+#define OCFB_CTRL_VBL2	0x00000080 /* Burst Length 2 */
+#define OCFB_CTRL_VBL4	0x00000100 /* Burst Length 4 */
+#define OCFB_CTRL_VBL8	0x00000180 /* Burst Length 8 */
+
+#define PALETTE_SIZE	256
+
+#define OCFB_NAME	"OC VGA/LCD"
+
+static char *mode_option;
+
+static const struct fb_videomode default_mode = {
+	/* 640x480 @ 60 Hz, 31.5 kHz hsync */
+	NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
+	0, FB_VMODE_NONINTERLACED
+};
+
+struct ocfb_dev {
+	struct fb_info info;
+	void __iomem *regs;
+	/* flag indicating whether the regs are little endian accessed */
+	int little_endian;
+	/* Physical and virtual addresses of framebuffer */
+	phys_addr_t fb_phys;
+	void __iomem *fb_virt;
+	u32 pseudo_palette[PALETTE_SIZE];
+};
+
+#ifndef MODULE
+static int __init ocfb_setup(char *options)
+{
+	char *curr_opt;
+
+	if (!options || !*options)
+		return 0;
+
+	while ((curr_opt = strsep(&options, ",")) != NULL) {
+		if (!*curr_opt)
+			continue;
+		mode_option = curr_opt;
+	}
+
+	return 0;
+}
+#endif
+
+static inline u32 ocfb_readreg(struct ocfb_dev *fbdev, loff_t offset)
+{
+	if (fbdev->little_endian)
+		return ioread32(fbdev->regs + offset);
+	else
+		return ioread32be(fbdev->regs + offset);
+}
+
+static void ocfb_writereg(struct ocfb_dev *fbdev, loff_t offset, u32 data)
+{
+	if (fbdev->little_endian)
+		iowrite32(data, fbdev->regs + offset);
+	else
+		iowrite32be(data, fbdev->regs + offset);
+}
+
+static int ocfb_setupfb(struct ocfb_dev *fbdev)
+{
+	unsigned long bpp_config;
+	struct fb_var_screeninfo *var = &fbdev->info.var;
+	struct device *dev = fbdev->info.device;
+	u32 hlen;
+	u32 vlen;
+
+	/* Disable display */
+	ocfb_writereg(fbdev, OCFB_CTRL, 0);
+
+	/* Register framebuffer address */
+	fbdev->little_endian = 0;
+	ocfb_writereg(fbdev, OCFB_VBARA, fbdev->fb_phys);
+
+	/* Detect endianess */
+	if (ocfb_readreg(fbdev, OCFB_VBARA) != fbdev->fb_phys) {
+		fbdev->little_endian = 1;
+		ocfb_writereg(fbdev, OCFB_VBARA, fbdev->fb_phys);
+	}
+
+	/* Horizontal timings */
+	ocfb_writereg(fbdev, OCFB_HTIM, (var->hsync_len - 1) << 24 |
+		      (var->right_margin - 1) << 16 | (var->xres - 1));
+
+	/* Vertical timings */
+	ocfb_writereg(fbdev, OCFB_VTIM, (var->vsync_len - 1) << 24 |
+		      (var->lower_margin - 1) << 16 | (var->yres - 1));
+
+	/* Total length of frame */
+	hlen = var->left_margin + var->right_margin + var->hsync_len +
+		var->xres;
+
+	vlen = var->upper_margin + var->lower_margin + var->vsync_len +
+		var->yres;
+
+	ocfb_writereg(fbdev, OCFB_HVLEN, (hlen - 1) << 16 | (vlen - 1));
+
+	bpp_config = OCFB_CTRL_CD8;
+	switch (var->bits_per_pixel) {
+	case 8:
+		if (!var->grayscale)
+			bpp_config |= OCFB_CTRL_PC;  /* enable palette */
+		break;
+
+	case 16:
+		bpp_config |= OCFB_CTRL_CD16;
+		break;
+
+	case 24:
+		bpp_config |= OCFB_CTRL_CD24;
+		break;
+
+	case 32:
+		bpp_config |= OCFB_CTRL_CD32;
+		break;
+
+	default:
+		dev_err(dev, "no bpp specified\n");
+		break;
+	}
+
+	/* maximum (8) VBL (video memory burst length) */
+	bpp_config |= OCFB_CTRL_VBL8;
+
+	/* Enable output */
+	ocfb_writereg(fbdev, OCFB_CTRL, (OCFB_CTRL_VEN | bpp_config));
+
+	return 0;
+}
+
+static int ocfb_setcolreg(unsigned regno, unsigned red, unsigned green,
+			  unsigned blue, unsigned transp,
+			  struct fb_info *info)
+{
+	struct ocfb_dev *fbdev = (struct ocfb_dev *)info->par;
+	u32 color;
+
+	if (regno >= info->cmap.len) {
+		dev_err(info->device, "regno >= cmap.len\n");
+		return 1;
+	}
+
+	if (info->var.grayscale) {
+		/* grayscale = 0.30*R + 0.59*G + 0.11*B */
+		red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+	}
+
+	red >>= (16 - info->var.red.length);
+	green >>= (16 - info->var.green.length);
+	blue >>= (16 - info->var.blue.length);
+	transp >>= (16 - info->var.transp.length);
+
+	if (info->var.bits_per_pixel = 8 && !info->var.grayscale) {
+		regno <<= 2;
+		color = (red << 16) | (green << 8) | blue;
+		ocfb_writereg(fbdev, OCFB_PALETTE + regno, color);
+	} else {
+		((u32 *)(info->pseudo_palette))[regno] +			(red << info->var.red.offset) |
+			(green << info->var.green.offset) |
+			(blue << info->var.blue.offset) |
+			(transp << info->var.transp.offset);
+	}
+
+	return 0;
+}
+
+static int ocfb_init_fix(struct ocfb_dev *fbdev)
+{
+	struct fb_var_screeninfo *var = &fbdev->info.var;
+	struct fb_fix_screeninfo *fix = &fbdev->info.fix;
+
+	strcpy(fix->id, OCFB_NAME);
+
+	fix->line_length = var->xres * var->bits_per_pixel/8;
+	fix->smem_len = fix->line_length * var->yres;
+	fix->type = FB_TYPE_PACKED_PIXELS;
+
+	if (var->bits_per_pixel = 8 && !var->grayscale)
+		fix->visual = FB_VISUAL_PSEUDOCOLOR;
+	else
+		fix->visual = FB_VISUAL_TRUECOLOR;
+
+	return 0;
+}
+
+static int ocfb_init_var(struct ocfb_dev *fbdev)
+{
+	struct fb_var_screeninfo *var = &fbdev->info.var;
+
+	var->accel_flags = FB_ACCEL_NONE;
+	var->activate = FB_ACTIVATE_NOW;
+	var->xres_virtual = var->xres;
+	var->yres_virtual = var->yres;
+
+	switch (var->bits_per_pixel) {
+	case 8:
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		var->red.offset = 0;
+		var->red.length = 8;
+		var->green.offset = 0;
+		var->green.length = 8;
+		var->blue.offset = 0;
+		var->blue.length = 8;
+		break;
+
+	case 16:
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		var->red.offset = 11;
+		var->red.length = 5;
+		var->green.offset = 5;
+		var->green.length = 6;
+		var->blue.offset = 0;
+		var->blue.length  = 5;
+		break;
+
+	case 24:
+		var->transp.offset = 0;
+		var->transp.length = 0;
+		var->red.offset = 16;
+		var->red.length = 8;
+		var->green.offset = 8;
+		var->green.length = 8;
+		var->blue.offset = 0;
+		var->blue.length = 8;
+		break;
+
+	case 32:
+		var->transp.offset = 24;
+		var->transp.length = 8;
+		var->red.offset = 16;
+		var->red.length = 8;
+		var->green.offset = 8;
+		var->green.length = 8;
+		var->blue.offset = 0;
+		var->blue.length = 8;
+		break;
+	}
+
+	return 0;
+}
+
+static struct fb_ops ocfb_ops = {
+	.owner		= THIS_MODULE,
+	.fb_setcolreg	= ocfb_setcolreg,
+	.fb_fillrect	= cfb_fillrect,
+	.fb_copyarea	= cfb_copyarea,
+	.fb_imageblit	= cfb_imageblit,
+};
+
+static int ocfb_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct ocfb_dev *fbdev;
+	struct resource *res;
+	int fbsize;
+
+	fbdev = devm_kzalloc(&pdev->dev, sizeof(*fbdev), GFP_KERNEL);
+	if (!fbdev)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, fbdev);
+
+	fbdev->info.fbops = &ocfb_ops;
+	fbdev->info.device = &pdev->dev;
+	fbdev->info.par = fbdev;
+
+	/* Video mode setup */
+	if (!fb_find_mode(&fbdev->info.var, &fbdev->info, mode_option,
+			  NULL, 0, &default_mode, 16)) {
+		dev_err(&pdev->dev, "No valid video modes found\n");
+		return -EINVAL;
+	}
+	ocfb_init_var(fbdev);
+	ocfb_init_fix(fbdev);
+
+	/* Request I/O resource */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "I/O resource request failed\n");
+		return -ENXIO;
+	}
+	res->flags &= ~IORESOURCE_CACHEABLE;
+	fbdev->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(fbdev->regs))
+		return PTR_ERR(fbdev->regs);
+
+	/* Allocate framebuffer memory */
+	fbsize = fbdev->info.fix.smem_len;
+	fbdev->fb_virt = dma_alloc_coherent(&pdev->dev, PAGE_ALIGN(fbsize),
+					    &fbdev->fb_phys, GFP_KERNEL);
+	if (!fbdev->fb_virt) {
+		dev_err(&pdev->dev,
+			"Frame buffer memory allocation failed\n");
+		return -ENOMEM;
+	}
+	fbdev->info.fix.smem_start = fbdev->fb_phys;
+	fbdev->info.screen_base = (void __iomem *)fbdev->fb_virt;
+	fbdev->info.pseudo_palette = fbdev->pseudo_palette;
+
+	/* Clear framebuffer */
+	memset_io((void __iomem *)fbdev->fb_virt, 0, fbsize);
+
+	/* Setup and enable the framebuffer */
+	ocfb_setupfb(fbdev);
+
+	if (fbdev->little_endian)
+		fbdev->info.flags |= FBINFO_FOREIGN_ENDIAN;
+
+	/* Allocate color map */
+	ret = fb_alloc_cmap(&fbdev->info.cmap, PALETTE_SIZE, 0);
+	if (ret) {
+		dev_err(&pdev->dev, "Color map allocation failed\n");
+		goto err_dma_free;
+	}
+
+	/* Register framebuffer */
+	ret = register_framebuffer(&fbdev->info);
+	if (ret) {
+		dev_err(&pdev->dev, "Framebuffer registration failed\n");
+		goto err_dealloc_cmap;
+	}
+
+	return 0;
+
+err_dealloc_cmap:
+	fb_dealloc_cmap(&fbdev->info.cmap);
+
+err_dma_free:
+	dma_free_coherent(&pdev->dev, PAGE_ALIGN(fbsize), fbdev->fb_virt,
+			  fbdev->fb_phys);
+
+	return ret;
+}
+
+static int ocfb_remove(struct platform_device *pdev)
+{
+	struct ocfb_dev *fbdev = platform_get_drvdata(pdev);
+
+	unregister_framebuffer(&fbdev->info);
+	fb_dealloc_cmap(&fbdev->info.cmap);
+	dma_free_coherent(&pdev->dev, PAGE_ALIGN(fbdev->info.fix.smem_len),
+			  fbdev->fb_virt, fbdev->fb_phys);
+
+	/* Disable display */
+	ocfb_writereg(fbdev, OCFB_CTRL, 0);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static struct of_device_id ocfb_match[] = {
+	{ .compatible = "opencores,ocfb", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, ocfb_match);
+
+static struct platform_driver ocfb_driver = {
+	.probe  = ocfb_probe,
+	.remove	= ocfb_remove,
+	.driver = {
+		.name = "ocfb_fb",
+		.of_match_table = ocfb_match,
+	}
+};
+
+/*
+ * Init and exit routines
+ */
+static int __init ocfb_init(void)
+{
+#ifndef MODULE
+	char *option = NULL;
+
+	if (fb_get_options("ocfb", &option))
+		return -ENODEV;
+	ocfb_setup(option);
+#endif
+	return platform_driver_register(&ocfb_driver);
+}
+
+static void __exit ocfb_exit(void)
+{
+	platform_driver_unregister(&ocfb_driver);
+}
+
+module_init(ocfb_init);
+module_exit(ocfb_exit);
+
+MODULE_AUTHOR("Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>");
+MODULE_DESCRIPTION("OpenCores VGA/LCD 2.0 frame buffer driver");
+MODULE_LICENSE("GPL v2");
+module_param(mode_option, charp, 0);
+MODULE_PARM_DESC(mode_option, "Video mode ('<xres>x<yres>[-<bpp>][@refresh]')");
-- 
1.8.3.2


^ permalink raw reply related

* Re: [Intel-gfx] [PATCH] fbcon: Avoid corrupting active workqueue entries
From: Daniel Vetter @ 2014-01-10 17:25 UTC (permalink / raw)
  To: Chris Wilson
  Cc: linux-fbdev, intel-gfx, dri-devel, Tomi Valkeinen, stable,
	Jean-Christophe Plagniol-Villard
In-Reply-To: <1387290459-26440-1-git-send-email-chris@chris-wilson.co.uk>

On Tue, Dec 17, 2013 at 02:27:39PM +0000, Chris Wilson wrote:
> We attempt to reschedule an active work which can itself corrupt the
> workqueue lists, and we may then free the work item whilst the task is
> still pending. Both of these may lead to a system deadlock and an
> unresponsive machine without any outputs for a panic to even be shown.
> 
> [    7.372961] WARNING: at kernel/workqueue.c:1365 __queue_work+0x216/0x292()
> [    7.372964] Modules linked in: coretemp arc4 kvm_intel kvm iwldvm crc32c_intel mac80211 ghash_clmulni_intel cryptd joydev hid_lenovo_tpkbd lib80211 iTCO_wdt iwlwifi iTCO_vendor_support i915(+) btusb snd_hda_codec_hdmi bluetooth evdev snd_hda_intel usbhid snd_hda_codec pcspkr hid cfg80211 microcode snd_hwdep i2c_i801 snd_pcm drm_kms_helper lpc_ich drm mfd_core snd_page_alloc rfkill snd_timer snd soundcore mei_me i2c_algo_bit video mei acpi_cpufreq mperf i2c_core button processor ext4 crc16 jbd2 mbcache sg sd_mod crc_t10dif ahci libahci libata scsi_mod thermal fan ehci_pci ehci_hcd thermal_sys usbcore usb_common
> [    7.373068] CPU: 0 PID: 660 Comm: ps Not tainted 3.10.9+ #55
> [    7.373071] Hardware name:                  /D33217CK, BIOS GKPPT10H.86A.0025.2012.1011.1534 10/11/2012
> [    7.373075]  ffffffff81596a1e ffff88045f203d38 ffffffff813eaef6 ffff88045f203d78
> [    7.373083]  ffffffff81041027 ffff88045f203d78 0000000000000000 ffff88045f217f00
> [    7.373091]  ffff88044a89c800 ffff88042b473aa0 0000000000000000 ffff88045f203d88
> [    7.373098] Call Trace:
> [    7.373101]  <IRQ>  [<ffffffff813eaef6>] dump_stack+0x19/0x1b
> [    7.373115]  [<ffffffff81041027>] warn_slowpath_common+0x62/0x7b
> [    7.373121]  [<ffffffff81041055>] warn_slowpath_null+0x15/0x17
> [    7.373127]  [<ffffffff8105aa82>] __queue_work+0x216/0x292
> [    7.373133]  [<ffffffff8105ab65>] queue_work_on+0x4c/0x7c
> [    7.373140]  [<ffffffff8123cebb>] ? fbcon_add_cursor_timer+0xfb/0xfb
> [    7.373146]  [<ffffffff8123cee1>] cursor_timer_handler+0x26/0x42
> [    7.373153]  [<ffffffff8104ee1f>] call_timer_fn+0xcc/0x1ea
> [    7.373160]  [<ffffffff8104ed53>] ? detach_if_pending+0x7a/0x7a
> [    7.373166]  [<ffffffff8123cebb>] ? fbcon_add_cursor_timer+0xfb/0xfb
> [    7.373172]  [<ffffffff8104f27b>] run_timer_softirq+0x19c/0x1e4
> [    7.373178]  [<ffffffff8104874e>] ? __do_softirq+0x9e/0x2a7
> [    7.373183]  [<ffffffff810487e9>] __do_softirq+0x139/0x2a7
> [    7.373189]  [<ffffffff81048a7a>] irq_exit+0x56/0x9b
> [    7.373196]  [<ffffffff8102af31>] smp_apic_timer_interrupt+0x77/0x85
> [    7.373203]  [<ffffffff813f5ff2>] apic_timer_interrupt+0x72/0x80
> [    7.373206]  <EOI>  [<ffffffff8113ea70>] ? spin_lock+0x9/0xb
> [    7.373217]  [<ffffffff8120d8c1>] ? do_raw_spin_trylock+0x42/0x42
> [    7.373223]  [<ffffffff813ef2e0>] ? _raw_spin_unlock+0x23/0x36
> [    7.373229]  [<ffffffff8113ea7b>] spin_unlock+0x9/0xb
> [    7.373235]  [<ffffffff8113fd25>] dput+0xd9/0xf8
> [    7.373241]  [<ffffffff8113685e>] path_put+0x13/0x20
> [    7.373247]  [<ffffffff8113a6f3>] do_last+0x925/0xa0d
> [    7.373253]  [<ffffffff81137fa4>] ? inode_permission+0x40/0x42
> [    7.373259]  [<ffffffff8113a89c>] path_openat+0xc1/0x325
> [    7.373265]  [<ffffffff8113ae0c>] do_filp_open+0x33/0x81
> [    7.373271]  [<ffffffff811455bd>] ? __alloc_fd+0x169/0x17b
> [    7.373279]  [<ffffffff8112d78f>] do_sys_open+0x67/0xf4
> [    7.373285]  [<ffffffff8112d839>] SyS_open+0x1d/0x1f
> [    7.373290]  [<ffffffff813f5369>] system_call_fastpath+0x16/0x1b
> [    7.373294] ---[ end trace 78bba0b9776072a9 ]---
> [    7.538936] fbcon: inteldrmfb (fb0) is primary device
> [    7.539446] Console: switching consoles 2-6 to frame buffer device
> [    7.539463] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
> [    7.539468] i915 0000:00:02.0: registered panic notifier
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?idr765
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: linux-fbdev@vger.kernel.org
> Cc: dri-devel@lists.freedesktop.org
> Cc: stable@vger.kernel.org
> ---
>  drivers/video/console/fbcon.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c
> index cd8a8027f8ae..f474976f6b34 100644
> --- a/drivers/video/console/fbcon.c
> +++ b/drivers/video/console/fbcon.c
> @@ -397,6 +397,8 @@ static void fb_flashcursor(struct work_struct *work)
>  	ops->cursor(vc, info, mode, softback_lines, get_color(vc, info, c, 1),
>  		    get_color(vc, info, c, 0));
>  	console_unlock();
> +
> +	mod_timer(&ops->cursor_timer, jiffies + HZ/5);
>  }
>  
>  static void cursor_timer_handler(unsigned long dev_addr)
> @@ -405,7 +407,6 @@ static void cursor_timer_handler(unsigned long dev_addr)
>  	struct fbcon_ops *ops = info->fbcon_par;
>  
>  	queue_work(system_power_efficient_wq, &info->queue);
> -	mod_timer(&ops->cursor_timer, jiffies + HZ/5);
>  }
>  
>  static void fbcon_add_cursor_timer(struct fb_info *info)
> @@ -417,6 +418,8 @@ static void fbcon_add_cursor_timer(struct fb_info *info)
>  	    !fbcon_cursor_noblink) {
>  		if (!info->queue.func)
>  			INIT_WORK(&info->queue, fb_flashcursor);
> +		else
> +			flush_work(&info->queue);
>  
>  		init_timer(&ops->cursor_timer);
>  		ops->cursor_timer.function = cursor_timer_handler;
> @@ -433,6 +436,7 @@ static void fbcon_del_cursor_timer(struct fb_info *info)
>  
>  	if (info->queue.func = fb_flashcursor &&
>  	    ops->flags & FBCON_FLAGS_CURSOR_TIMER) {
> +		flush_work(&info->queue);
>  		del_timer_sync(&ops->cursor_timer);

I think this is still racy - we'd need to loop the flush work and
del_timer until they're both dead, otherwise it could get re-armed.
Probably better to convert this to a delayed_work and just use
cancel_delayed_work_sync.
-Daniel

>  		ops->flags &= ~FBCON_FLAGS_CURSOR_TIMER;
>  	}
> -- 
> 1.8.5.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply

* Re: [PATCH v4] video: add OpenCores VGA/LCD framebuffer driver
From: Stefan Kristiansson @ 2014-01-10 16:16 UTC (permalink / raw)
  To: Tomi Valkeinen; +Cc: linux-kernel, linux-fbdev, plagnioj
In-Reply-To: <52CFE2BB.8090004@ti.com>

On Fri, Jan 10, 2014 at 02:08:27PM +0200, Tomi Valkeinen wrote:
> Hi,
> 
> On 2013-11-29 17:45, Stefan Kristiansson wrote:
> > This adds support for the VGA/LCD core available from OpenCores:
> > http://opencores.org/project,vga_lcd
> > 
> > The driver have been tested together with both OpenRISC and
> > ARM (socfpga) processors.
> > 
> > Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> 
> If I'm not mistaken, this driver has been designed so that there can
> only be one VGA/LCD core device on the system.
> 
> It would be better to get rid of those static structs, and have the
> driver data per device as it should. That way the driver works even with
> multiple VGA/LCD cores (although the video mode module option is a bit
> odd in that case).
> 

You're right, it's a completely realistic scenario with several
VGA/LCD cores in the system, so the one device only restriction is bad.
And looking closer at the static structs, I see that the ocfb_var and ocfb_fix
doesn't surve any purpose at all, so they can just be removed.
And the information in ocfb_par can easily be obtained directly from ocfb_dev
instead, so by setting info.par to point at that, the ocfb_par struct can also
be removed completely.
Thanks, that suggestion makes the implementation cleaner as well.

I'll post an updated patch with the changes.

Stefan

^ permalink raw reply

* Re: [PATCHv5][ 1/5] fbdev: Add the lacking FB_SYNC_* for matching the DISPLAY_FLAGS_*
From: Russell King - ARM Linux @ 2014-01-10 12:46 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <52CFE994.8070701@ti.com>

On Fri, Jan 10, 2014 at 02:37:40PM +0200, Tomi Valkeinen wrote:
> I don't think this is better than the previous version where
> FB_SYNC_DE_HIGH_ACT and FB_SYNC_PIXDAT_HIGH_ACT were in
> include/uapi/linux/fb.h. Now those flag defines are not visible to the
> userspace, but the actual flags are still visible from the var->sync field.
> 
> It's true what Russell replied to the previous version, that the
> userspace has no idea how to handle those new flags. But then again, for
> LCDs, the userspace has no idea how to handle, say, hsync polarity either.
> 
> In any case, splitting the FB_SYNC_ defines into uapi and
> kernel-internal header files, but still giving the kernel-internal
> values to userspace is surely wrong.

The difference between the sync states and these other flags is that
the sync states are part of the mode definition - as per the CEA-861
documentation.

However, that does not extend to LCD panels, which generally need to
have one set of timings, with the various control signals at certain
polarities - and those control signal polarities are a property of
the panel itself, not of the displayed mode.  So, if you know that
you have LCD panel X, and it needs control signals with a certain
polarity, that is how you configure the hardware _irrespective_ of
what userspace says that the sync states should be.

The sync states specified by userspace should of course be used for
the sync pulses being sent to a VGA display or HDMI sink.

-- 
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up.  Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".

^ permalink raw reply

* Re: [PATCHv5][ 1/5] fbdev: Add the lacking FB_SYNC_* for matching the DISPLAY_FLAGS_*
From: Tomi Valkeinen @ 2014-01-10 12:37 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1383915693-9422-1-git-send-email-denis@eukrea.com>

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On 2013-11-08 15:01, Denis Carikli wrote:
> Without that fix, drivers using the fb_videomode_from_videomode
>   function will not be able to get certain information because
>   some DISPLAY_FLAGS_* have no corresponding FB_SYNC_*.

> diff --git a/include/linux/fb.h b/include/linux/fb.h
> index ffac70a..cf2ad5d 100644
> --- a/include/linux/fb.h
> +++ b/include/linux/fb.h
> @@ -45,6 +45,9 @@ struct device_node;
>  #define FB_SIGNAL_SYNC_ON_GREEN	8
>  #define FB_SIGNAL_SERRATION_ON	16
>  
> +#define FB_SYNC_DE_HIGH_ACT     64      /* data enable active high flag */
> +#define FB_SYNC_PIXDAT_HIGH_ACT 128     /* drive data on positive edge */
> +
>  #define FB_MISC_PRIM_COLOR	1
>  #define FB_MISC_1ST_DETAIL	2	/* First Detailed Timing is preferred */
>  struct fb_chroma {

I don't think this is better than the previous version where
FB_SYNC_DE_HIGH_ACT and FB_SYNC_PIXDAT_HIGH_ACT were in
include/uapi/linux/fb.h. Now those flag defines are not visible to the
userspace, but the actual flags are still visible from the var->sync field.

It's true what Russell replied to the previous version, that the
userspace has no idea how to handle those new flags. But then again, for
LCDs, the userspace has no idea how to handle, say, hsync polarity either.

In any case, splitting the FB_SYNC_ defines into uapi and
kernel-internal header files, but still giving the kernel-internal
values to userspace is surely wrong.

 Tomi



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* Re: [PATCH v4] video: add OpenCores VGA/LCD framebuffer driver
From: Tomi Valkeinen @ 2014-01-10 12:08 UTC (permalink / raw)
  To: Stefan Kristiansson, linux-kernel, linux-fbdev; +Cc: plagnioj
In-Reply-To: <1385739911-6541-1-git-send-email-stefan.kristiansson@saunalahti.fi>

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Hi,

On 2013-11-29 17:45, Stefan Kristiansson wrote:
> This adds support for the VGA/LCD core available from OpenCores:
> http://opencores.org/project,vga_lcd
> 
> The driver have been tested together with both OpenRISC and
> ARM (socfpga) processors.
> 
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

If I'm not mistaken, this driver has been designed so that there can
only be one VGA/LCD core device on the system.

It would be better to get rid of those static structs, and have the
driver data per device as it should. That way the driver works even with
multiple VGA/LCD cores (although the video mode module option is a bit
odd in that case).

 Tomi



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* Re: [PATCH] video/logo: Remove MIPS-specific include section
From: Tomi Valkeinen @ 2014-01-10 11:56 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Jean-Christophe Plagniol-Villard, Ralf Baechle, linux-fbdev,
	linux-mips
In-Reply-To: <1383554550-20901-1-git-send-email-geert@linux-m68k.org>

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On 2013-11-04 10:42, Geert Uytterhoeven wrote:
> Since commit 41702d9a4fffa9e25b2ad9d4af09b3013fa155e1 ("logo.c: get rid of
> mips_machgroup") there's no longer a need to include <asm/bootinfo.h> on
> MIPS.
> 
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
>  drivers/video/logo/logo.c |    4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/video/logo/logo.c b/drivers/video/logo/logo.c
> index 080c35b34bbb..b670cbda38e3 100644
> --- a/drivers/video/logo/logo.c
> +++ b/drivers/video/logo/logo.c
> @@ -17,10 +17,6 @@
>  #include <asm/setup.h>
>  #endif
>  
> -#ifdef CONFIG_MIPS
> -#include <asm/bootinfo.h>
> -#endif
> -
>  static bool nologo;
>  module_param(nologo, bool, 0);
>  MODULE_PARM_DESC(nologo, "Disables startup logo");
> 

Queued for 3.14.

 Tomi



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* Re: [patch v2] tgafb: potential NULL dereference in init
From: Tomi Valkeinen @ 2014-01-10 11:33 UTC (permalink / raw)
  To: linux-fbdev

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On 2013-12-16 11:49, Dan Carpenter wrote:
> Static checkers complain that there are paths where "tga_type_name" can
> be NULL.  I've re-arranged the code slightly so that's impossible.
> 
> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
> ---
> v1: had introduced a "dereferencing uninitialized variable" bug.  Thanks
> to Geert Uytterhoeven for catching that.
> 
> diff --git a/drivers/video/tgafb.c b/drivers/video/tgafb.c
> index f28674fea909..afd8887fd656 100644
> --- a/drivers/video/tgafb.c
> +++ b/drivers/video/tgafb.c
> @@ -1496,10 +1496,9 @@ tgafb_init_fix(struct fb_info *info)
>  		if (tga_bus_tc)
>  			tga_type_name = "Digital ZLX-E3";
>  		break;
> -	default:
> -		tga_type_name = "Unknown";
> -		break;
>  	}
> +	if (!tga_type_name)
> +		tga_type_name = "Unknown";
>  
>  	strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
>  
> 

Queued for 3.14.

 Tomi



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* Re: [patch 2/2] video: mmp: Using plain integer as NULL pointer
From: Tomi Valkeinen @ 2014-01-10 11:31 UTC (permalink / raw)
  To: linux-fbdev

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On 2013-11-14 10:19, Dan Carpenter wrote:
> Sparse complains here:
> 
> 	drivers/video/mmp/core.c:33:16:
> 		warning: Using plain integer as NULL pointer
> 
> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
> 
> diff --git a/drivers/video/mmp/core.c b/drivers/video/mmp/core.c
> index c8d4265..b563b92 100644
> --- a/drivers/video/mmp/core.c
> +++ b/drivers/video/mmp/core.c
> @@ -30,7 +30,7 @@ static struct mmp_overlay *path_get_overlay(struct mmp_path *path,
>  {
>  	if (path && overlay_id < path->overlay_num)
>  		return &path->overlays[overlay_id];
> -	return 0;
> +	return NULL;
>  }
>  
>  static int path_check_status(struct mmp_path *path)
> 

Queued for 3.14.

 Tomi



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* Re: [patch 1/2] video: mmp: delete a stray mutex_unlock()
From: Tomi Valkeinen @ 2014-01-10 11:29 UTC (permalink / raw)
  To: linux-fbdev
In-Reply-To: <20131114081918.GB8150@elgon.mountain>

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On 2013-11-14 10:19, Dan Carpenter wrote:
> We aren't holding the disp_lock so we shouldn't release it.
> 
> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
> 
> diff --git a/drivers/video/mmp/core.c b/drivers/video/mmp/core.c
> index 84de263..c8d4265 100644
> --- a/drivers/video/mmp/core.c
> +++ b/drivers/video/mmp/core.c
> @@ -173,7 +173,7 @@ struct mmp_path *mmp_register_path(struct mmp_path_info *info)
>  		+ sizeof(struct mmp_overlay) * info->overlay_num;
>  	path = kzalloc(size, GFP_KERNEL);
>  	if (!path)
> -		goto failed;
> +		return NULL;
>  
>  	/* path set */
>  	mutex_init(&path->access_ok);
> @@ -219,11 +219,6 @@ struct mmp_path *mmp_register_path(struct mmp_path_info *info)
>  
>  	mutex_unlock(&disp_lock);
>  	return path;
> -
> -failed:
> -	kfree(path);
> -	mutex_unlock(&disp_lock);
> -	return NULL;
>  }
>  EXPORT_SYMBOL_GPL(mmp_register_path);
>  
> 

Queued for 3.14.

 Tomi



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* Re: [PATCH] video: amba-clcd: Make CLCD driver available on more platforms
From: Tomi Valkeinen @ 2014-01-10 11:27 UTC (permalink / raw)
  To: linux-fbdev
In-Reply-To: <1386868390-12231-1-git-send-email-broonie@kernel.org>

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On 2013-12-12 19:13, Mark Brown wrote:
> From: Mark Brown <broonie@linaro.org>
> 
> The CLCD driver is used on ARM reference models for ARMv8 so add ARM64
> to the list of dependencies. The driver also has no build time dependencies
> on ARM (stubs are provided for ARM-specific DMA functions in the code) so
> make it available with COMPILE_TEST in order to maximise build coverage.
> 
> Signed-off-by: Mark Brown <broonie@linaro.org>
> ---
>  drivers/video/Kconfig | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
> index 4f2e1b35eb38..e6c7fb1a389b 100644
> --- a/drivers/video/Kconfig
> +++ b/drivers/video/Kconfig
> @@ -312,7 +312,8 @@ config FB_PM2_FIFO_DISCONNECT
>  
>  config FB_ARMCLCD
>  	tristate "ARM PrimeCell PL110 support"
> -	depends on FB && ARM && ARM_AMBA
> +	depends on ARM || ARM64 || COMPILE_TEST
> +	depends on FB && ARM_AMBA
>  	select FB_CFB_FILLRECT
>  	select FB_CFB_COPYAREA
>  	select FB_CFB_IMAGEBLIT
> 

Queued for 3.14.

 Tomi



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* Re: [PATCH] fbcon: Avoid corrupting active workqueue entries
From: Tomi Valkeinen @ 2014-01-10 11:24 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx
  Cc: Jean-Christophe Plagniol-Villard, linux-fbdev, dri-devel, stable
In-Reply-To: <1387290459-26440-1-git-send-email-chris@chris-wilson.co.uk>

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Hi,

On 2013-12-17 16:27, Chris Wilson wrote:
> We attempt to reschedule an active work which can itself corrupt the
> workqueue lists, and we may then free the work item whilst the task is
> still pending. Both of these may lead to a system deadlock and an
> unresponsive machine without any outputs for a panic to even be shown.

This gives the following warning:

drivers/video/console/fbcon.c:407:20: warning: unused variable ‘ops’
[-Wunused-variable]

I can fix that. Or maybe it's better if you send a v2 with that fixed,
so that this gets properly to stable-kernel.

However, I wouldn't mind an acked-by or reviewed-by from someone.

 Tomi



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* Re: [PATCH v2] ARM: OMAPFB: panel-sony-acx565akm: fix missing mutex unlocks
From: Tomi Valkeinen @ 2014-01-10 10:56 UTC (permalink / raw)
  To: Ivaylo Dimitrov
  Cc: plagnioj, pali.rohar, pavel, linux-omap, linux-fbdev,
	linux-kernel, Ivaylo Dimitrov, Aaro Koskinen
In-Reply-To: <1388927585-5640-1-git-send-email-ivo.g.dimitrov.75@gmail.com>

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On 2014-01-05 15:13, Ivaylo Dimitrov wrote:
> From: Ivaylo Dimitrov <freemangordon@abv.bg>
> 
> Commit c37dd677988ca50bc8bc60ab5ab053720583c168 fixes the unbalanced
> unlock in acx565akm_enable but introduces another problem - if
> acx565akm_panel_power_on exits early, the mutex is not unlocked. Fix
> that by unlocking the mutex on early return. Also add mutex protection in
> acx565akm_panel_power_off and remove an unused variable
> 

I think this is just getting more messy. How about we more or less revert the c37dd677988ca50bc8bc60ab5ab053720583c168 and fix it like this:


diff --git a/drivers/video/omap2/displays-new/panel-sony-acx565akm.c b/drivers/video/omap2/displays-new/panel-sony-acx565akm.c
index 714ee92dfb9f..8e97d06921ff 100644
--- a/drivers/video/omap2/displays-new/panel-sony-acx565akm.c
+++ b/drivers/video/omap2/displays-new/panel-sony-acx565akm.c
@@ -346,28 +346,22 @@ static int acx565akm_get_actual_brightness(struct panel_drv_data *ddata)
 static int acx565akm_bl_update_status(struct backlight_device *dev)
 {
 	struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev);
-	int r;
 	int level;
 
 	dev_dbg(&ddata->spi->dev, "%s\n", __func__);
 
-	mutex_lock(&ddata->mutex);
-
 	if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
 			dev->props.power == FB_BLANK_UNBLANK)
 		level = dev->props.brightness;
 	else
 		level = 0;
 
-	r = 0;
 	if (ddata->has_bc)
 		acx565akm_set_brightness(ddata, level);
 	else
-		r = -ENODEV;
-
-	mutex_unlock(&ddata->mutex);
+		return -ENODEV;
 
-	return r;
+	return 0;
 }
 
 static int acx565akm_bl_get_intensity(struct backlight_device *dev)
@@ -390,9 +384,33 @@ static int acx565akm_bl_get_intensity(struct backlight_device *dev)
 	return 0;
 }
 
+static int acx565akm_bl_update_status_locked(struct backlight_device *dev)
+{
+	struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev);
+	int r;
+
+	mutex_lock(&ddata->mutex);
+	r = acx565akm_bl_update_status(dev);
+	mutex_unlock(&ddata->mutex);
+
+	return r;
+}
+
+static int acx565akm_bl_get_intensity_locked(struct backlight_device *dev)
+{
+	struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev);
+	int r;
+
+	mutex_lock(&ddata->mutex);
+	r = acx565akm_bl_get_intensity(dev);
+	mutex_unlock(&ddata->mutex);
+
+	return r;
+}
+
 static const struct backlight_ops acx565akm_bl_ops = {
-	.get_brightness = acx565akm_bl_get_intensity,
-	.update_status  = acx565akm_bl_update_status,
+	.get_brightness = acx565akm_bl_get_intensity_locked,
+	.update_status  = acx565akm_bl_update_status_locked,
 };
 
 /*--------------------Auto Brightness control via Sysfs---------------------*/
@@ -526,8 +544,6 @@ static int acx565akm_panel_power_on(struct omap_dss_device *dssdev)
 	struct omap_dss_device *in = ddata->in;
 	int r;
 
-	mutex_lock(&ddata->mutex);
-
 	dev_dbg(&ddata->spi->dev, "%s\n", __func__);
 
 	in->ops.sdi->set_timings(in, &ddata->videomode);
@@ -568,8 +584,6 @@ static int acx565akm_panel_power_on(struct omap_dss_device *dssdev)
 	set_display_state(ddata, 1);
 	set_cabc_mode(ddata, ddata->cabc_mode);
 
-	mutex_unlock(&ddata->mutex);
-
 	return acx565akm_bl_update_status(ddata->bl_dev);
 }
 
@@ -605,6 +619,7 @@ static void acx565akm_panel_power_off(struct omap_dss_device *dssdev)
 
 static int acx565akm_enable(struct omap_dss_device *dssdev)
 {
+	struct panel_drv_data *ddata = to_panel_data(dssdev);
 	int r;
 
 	dev_dbg(dssdev->dev, "%s\n", __func__);
@@ -615,7 +630,9 @@ static int acx565akm_enable(struct omap_dss_device *dssdev)
 	if (omapdss_device_is_enabled(dssdev))
 		return 0;
 
+	mutex_lock(&ddata->mutex);
 	r = acx565akm_panel_power_on(dssdev);
+	mutex_unlock(&ddata->mutex);
 	if (r)
 		return r;
 



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* Re: [PATCH] video: mmp: add device tree support
From: 'Sascha Hauer' @ 2014-01-10  9:07 UTC (permalink / raw)
  To: Zhou Zhu
  Cc: Jingoo Han, linux-fbdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	'Tomi Valkeinen',
	'Jean-Christophe Plagniol-Villard',
	'Haojian Zhuang', Chao Xie, Guoqing Li,
	devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <52CE9165.7050002-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>

On Thu, Jan 09, 2014 at 08:09:09PM +0800, Zhou Zhu wrote:
> Sascha/Jingoo,
> Thank you for your review!
> 
> On 01/09/2014 03:43 PM, Jingoo Han wrote:
> >On Thursday, January 09, 2014 4:32 PM, Sascha Hauer wrote:
> >>On Thu, Jan 09, 2014 at 01:13:14PM +0800, Zhou Zhu wrote:
> >>>add device tree support for mmp fb/controller
> >>>the description at Documentation/devicetree/bindings/fb/mmp-disp.txt
> >>>
> >>>Signed-off-by: Zhou Zhu <zzhu3@marvell.com>
> >>>---
> >>>  Documentation/devicetree/bindings/fb/mmp-disp.txt |   71 ++++++++++++
> >>>  drivers/video/mmp/fb/mmpfb.c                      |   71 ++++++++----
> >>>  drivers/video/mmp/hw/mmp_ctrl.c                   |  120 ++++++++++++++++-----
> >>>  3 files changed, 217 insertions(+), 45 deletions(-)
> >>>  create mode 100644 Documentation/devicetree/bindings/fb/mmp-disp.txt
> >>>
> 
> [...]
> 
> >>+fb: fb {
> >>+	compatible = "marvell,mmp-fb";
> >
> >This compatible should have the specific SoC name in it, not just
> >'mmp'. Otherwise you can't properly distinguish between this version and
> >future versions of the mmp core.
> >
> We are using a same display IP for all mmp serial SoCs, and there
> would be inside register to get version. So I am planning put same
> compatible here for all SoCs using this IP.
> Would it be ok if I update compatible to "marvell,mmpdcx-fb"?
> "mmpdcx" is the IP name.

Using the SoC name is really good practice. This way you can add SoC
specific data to the compatible entry in the driver. Most bindings I've
seen which bind to some more generic string tend to add some additional
properties to the binding like marvell,has-new-feature or
marvell,needs-workaround-for-xy which you don't need at all if you bind
to the specific SoC in the first place.

If you insist on a generic binding you can still do a

	compatible = "marvell,soc-xy-fb", "marvell,mmp-fb";

This way you at least have the SoC information around (even in old
devicetrees) should you need it in the future.

BTW I've seen often enough that the version register is at a different
location on newer generations which makes it pretty useless.

> >> +	interrupts = <0 41 0x4>;
> >> +	marvell,disp-name = "mmp_disp";
> >> +	marvell,path-num = <1>;
> >> +	marvell,clk-name = "LCDCIHCLK";
> >
> > Don't pass clk names like this. We have a documented clock binding, use
> > it.
> >
> The patches to add dt support in common clk in our platforms are not
> upstreamed yet. As there's only one clock in this device, could I
> remove clock name related codes and direct use: devm_clk_get(dev,
> NULL)?

The clock name is defined by the device you are implementing, *not*
the name of the clock in the SoC. So if you have:

                                     ----------------------
   ---------  LCDCIHCLK             |            MMP       |
  | OSC/PLL |-----------------------|>pixclk               |
  ----------                        |                      |
                                     ----------------------


You have to do clk_get(dev, "pixclk") because you want to get the
clock associated to the pixclk input. Doing clk_get(dev, "LCDCIHCLK")
is wrong because that may change in future SoCs.
If you do this correctly there is no need to put the clk name into the
devicetree. You only have to put the information "which clk is connected
to the pixclk input of the MMP" into the devicetree.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

^ permalink raw reply

* Re: [PATCH] fbdev: sh_mipi_dsi/sh_mobile_hdmi: clk_round_rate() can return a zero upon error
From: Tomi Valkeinen @ 2014-01-09 13:03 UTC (permalink / raw)
  To: linux-fbdev
In-Reply-To: <alpine.DEB.2.02.1311261651300.11450@tamien>

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On 2013-11-27 02:53, Paul Walmsley wrote:
> 
> Treat both negative and zero return values from clk_round_rate() as
> errors.  This is needed since subsequent patches will convert
> clk_round_rate()'s return value to be an unsigned type, rather than a
> signed type, since some clock sources can generate rates higher than
> (2^31)-1 Hz.
> 
> Eventually, when calling clk_round_rate(), only a return value of zero
> will be considered a error.  All other values will be considered valid
> rates.  The comparison against values less than 0 is kept to preserve
> the correct behavior in the meantime.
> 
> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
> ---
> 
> Applies on v3.13-rc1.  See also:

I'm not able to apply this, I'm just getting "patch doesn't apply". I
tried both the patch saved from my email client, and the patch from
patchworks...

Can you rebase to, say, rc6, and resend?

 Tomi



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* RE: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
From: Hiremath, Vaibhav @ 2014-01-09 13:02 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <52CE5C1A.3070603@ti.com>



> -----Original Message-----
> From: Hiremath, Vaibhav
> Sent: Thursday, January 09, 2014 2:01 PM
> To: Valkeinen, Tomi; Ivaylo Dimitrov
> Cc: Tony Lindgren; linux-omap@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-fbdev@vger.kernel.org
> Subject: RE: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
> 
> 
> > -----Original Message-----
> > From: Valkeinen, Tomi
> > Sent: Thursday, January 09, 2014 1:52 PM
> > To: Hiremath, Vaibhav; Ivaylo Dimitrov
> > Cc: Tony Lindgren; linux-omap@vger.kernel.org; linux-arm-
> > kernel@lists.infradead.org; linux-fbdev@vger.kernel.org
> > Subject: Re: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
> >
> > On 2014-01-09 07:06, Hiremath, Vaibhav wrote:
> >
> > > I am seeing underflow issue on AM43x device if I use omapfb_vram
> argument.
> > > Did you see this on OMAP?
> > >
> > > I am using "omapfb_vram\x10M@0xA0000000", and I believe it is correct
> > > way
> > of usage.
> >
> > Hmm ok... The AM4x seems to have issues anyway, as we're seeing
> > underflows easily in other situations also.
> >
> > Well, there's a small difference in the allocation. The normal dma
> > alloc uses
> > dma_alloc_attrs() and passes DMA_ATTR_WRITE_COMBINE as a flag, whereas
> > allocating from the absolute address just uses the piece of memory. I
> > couldn't find how to set write-combine for the abs memory area.
> >
> > Then again, that's for CPU caching, so I don't see why it would affect
> > DSS as such (but that's still something we should measure, cpu
> > read/write perf for normal and abs allocation).
> >
> > The only thought I have is that somehow the reserved memory area is
> > missing some configuration that is done for the rest of the memory.
> > But that's purely a guess, this is totally out of my area of expertise...
> >
> > Vaibhav, just to be sure, can you run both with normal dma_alloc and
> > with the reserve, and verify that the dispc register dumps are the same?
> > I don't see how they could be different, but just to be sure.
> >
> 
> Will check and update you shortly.
> 

I checked both the DSS configuration in both scenarios and they look same to me.


With normal dma_alloc:
=========root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /proc/cmdline
console=ttyO0,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait mem\x128M consoleblank=0 clocksource=gp_timer consoleblank=0 earlyprintk
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /sys/kernel/debug/omapdss/dss
DSS_REVISION                        00000020
DSS_SYSCONFIG                       00000001
DSS_SYSSTATUS                       00000001
DSS_CONTROL                         00000018
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /sys/kernel/debug/omapdss/clk
- DSS -
DSS_FCK (DSS_FCLK1) = 198000000
- DISPC -
dispc fclk source = DSS_FCK (DSS_FCLK1)
fck             198000000
- LCD -
LCD clk source = DSS_FCK (DSS_FCLK1)
lck             198000000       lck div 1
pck             33000000        pck div 6
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /sys/kernel/debug/omapdss/dispc_irq
period 44780 ms
irqs 1
FRAMEDONE                     0
VSYNC                         1
EVSYNC_EVEN                   1
EVSYNC_ODD                    1
ACBIAS_COUNT_STAT             0
PROG_LINE_NUM                 1
GFX_FIFO_UNDERFLOW            0
GFX_END_WIN                   1
PAL_GAMMA_MASK                0
OCP_ERR                       0
VID1_FIFO_UNDERFLOW           0
VID1_END_WIN                  0
VID2_FIFO_UNDERFLOW           0
VID2_END_WIN                  0
SYNC_LOST                     0
SYNC_LOST_DIGIT               0
WAKEUP                        0
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /sys/kernel/debug/omapdss/dispc
DISPC_REVISION                                     00000030
DISPC_SYSCONFIG                                    00002011
DISPC_SYSSTATUS                                    00000001
DISPC_IRQSTATUS                                    000000ae
DISPC_IRQENABLE                                    0000d640
DISPC_CONTROL                                      00018309
DISPC_CONFIG                                       00000204
DISPC_CAPABLE                                      000003ff
DISPC_LINE_STATUS                                  000000b1
DISPC_LINE_NUMBER                                  00000000
DISPC_GLOBAL_ALPHA                                 000000ff
DISPC_DEFAULT_COLOR(LCD)                           00000000
DISPC_TRANS_COLOR(LCD)                             00000000
DISPC_SIZE_MGR(LCD)                                01df031f
DISPC_DEFAULT_COLOR(LCD)                           00000000
DISPC_TRANS_COLOR(LCD)                             00000000
DISPC_TIMING_H(LCD)                                00f0d11d
DISPC_TIMING_V(LCD)                                00a0160c
DISPC_POL_FREQ(LCD)                                00003000
DISPC_DIVISORo(LCD)                                00010006
DISPC_SIZE_MGR(LCD)                                01df031f
DISPC_DATA_CYCLE1(LCD)                             00000000
DISPC_DATA_CYCLE2(LCD)                             00000000
DISPC_DATA_CYCLE3(LCD)                             00000000
DISPC_CPR_COEF_R(LCD)                              00000000
DISPC_CPR_COEF_G(LCD)                              00000000
DISPC_CPR_COEF_B(LCD)                              00000000
DISPC_OVL_BA0(GFX)                                 86900000
DISPC_OVL_BA1(GFX)                                 86900000
DISPC_OVL_POSITION(GFX)                            00000000
DISPC_OVL_SIZE(GFX)                                01df031f
DISPC_OVL_ATTRIBUTES(GFX)                          00000091
DISPC_OVL_FIFO_THRESHOLD(GFX)                      03ff03c0
DISPC_OVL_FIFO_SIZE_STATUS(GFX)                    00000400
DISPC_OVL_ROW_INC(GFX)                             00000001
DISPC_OVL_PIXEL_INC(GFX)                           00000001
DISPC_OVL_PRELOAD(GFX)                             00000100
DISPC_OVL_WINDOW_SKIP(GFX)                         00000000
DISPC_OVL_TABLE_BA(GFX)                            00000000
DISPC_OVL_BA0(VID1)                                00000000
DISPC_OVL_BA1(VID1)                                00000000
DISPC_OVL_POSITION(VID1)                           00000000
DISPC_OVL_SIZE(VID1)                               00000000
DISPC_OVL_ATTRIBUTES(VID1)                         00008000
DISPC_OVL_FIFO_THRESHOLD(VID1)                     03ff03c0
DISPC_OVL_FIFO_SIZE_STATUS(VID1)                   00000400
DISPC_OVL_ROW_INC(VID1)                            00000001
DISPC_OVL_PIXEL_INC(VID1)                          00000001
DISPC_OVL_PRELOAD(VID1)                            00000100
DISPC_OVL_FIR(VID1)                                00000000
DISPC_OVL_PICTURE_SIZE(VID1)                       00000000
DISPC_OVL_ACCU0(VID1)                              00000000
DISPC_OVL_ACCU1(VID1)                              00000000
DISPC_OVL_PRELOAD(VID1)                            00000100
DISPC_OVL_BA0(VID2)                                00000000
DISPC_OVL_BA1(VID2)                                00000000
DISPC_OVL_POSITION(VID2)                           00000000
DISPC_OVL_SIZE(VID2)                               00000000
DISPC_OVL_ATTRIBUTES(VID2)                         00008000
DISPC_OVL_FIFO_THRESHOLD(VID2)                     03ff03c0
DISPC_OVL_FIFO_SIZE_STATUS(VID2)                   00000400
DISPC_OVL_ROW_INC(VID2)                            00000001
DISPC_OVL_PIXEL_INC(VID2)                          00000001
DISPC_OVL_PRELOAD(VID2)                            00000100
DISPC_OVL_FIR(VID2)                                00000000
DISPC_OVL_PICTURE_SIZE(VID2)                       00000000
DISPC_OVL_ACCU0(VID2)                              00000000
DISPC_OVL_ACCU1(VID2)                              00000000
DISPC_OVL_PRELOAD(VID2)                            00000100
DISPC_OVL_FIR_COEF_H_0(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_1(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_2(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_3(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_4(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_5(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_6(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_7(VID1)                       00000000
DISPC_OVL_FIR_COEF_HV_0(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_1(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_2(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_3(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_4(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_5(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_6(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_7(VID1)                      00000000
DISPC_OVL_CONV_COEF_0(VID1)                        0199012a
DISPC_OVL_CONV_COEF_1(VID1)                        012a0000
DISPC_OVL_CONV_COEF_2(VID1)                        079c0730
DISPC_OVL_CONV_COEF_3(VID1)                        0000012a
DISPC_OVL_CONV_COEF_4(VID1)                        00000205
DISPC_OVL_FIR_COEF_V_0(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_2(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_3(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_4(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_5(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_6(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_7(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_0(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_1(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_2(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_3(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_4(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_5(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_6(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_7(VID2)                       00000000
DISPC_OVL_FIR_COEF_HV_0(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_1(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_2(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_3(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_4(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_5(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_6(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_7(VID2)                      00000000
DISPC_OVL_CONV_COEF_0(VID2)                        0199012a
DISPC_OVL_CONV_COEF_1(VID2)                        012a0000
DISPC_OVL_CONV_COEF_2(VID2)                        079c0730
DISPC_OVL_CONV_COEF_3(VID2)                        0000012a
DISPC_OVL_CONV_COEF_4(VID2)                        00000205
DISPC_OVL_FIR_COEF_V_0(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_2(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_3(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_4(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_5(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_6(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_7(VID2)                       00000000
root@am43xx-epos-evm:~#




With Reserved memory for FB:
==============
root@am43xx-epos-evm:~# cat /proc/cmdline
console=ttyO0,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait mem\x128M consoleblank=0 clocksource=gp_timer consoleblank=0 earlyprintk omapfb_vram\x10M@0xA0000000
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /sys/kernel/debug/omapdss/dss
DSS_REVISION                        00000020
DSS_SYSCONFIG                       00000001
DSS_SYSSTATUS                       00000001
DSS_CONTROL                         00000018
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /sys/kernel/debug/omapdss/clk
- DSS -
DSS_FCK (DSS_FCLK1) = 198000000
- DISPC -
dispc fclk source = DSS_FCK (DSS_FCLK1)
fck             198000000
- LCD -
LCD clk source = DSS_FCK (DSS_FCLK1)
lck             198000000       lck div 1
pck             33000000        pck div 6
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /sys/kernel/debug/omapdss/dispc_irq
period 48010 ms
irqs 2
FRAMEDONE                     0
VSYNC                         2
EVSYNC_EVEN                   2
EVSYNC_ODD                    2
ACBIAS_COUNT_STAT             0
PROG_LINE_NUM                 2
GFX_FIFO_UNDERFLOW            2
GFX_END_WIN                   2
PAL_GAMMA_MASK                0
OCP_ERR                       0
VID1_FIFO_UNDERFLOW           0
VID1_END_WIN                  0
VID2_FIFO_UNDERFLOW           0
VID2_END_WIN                  0
SYNC_LOST                     0

SYNC_LOST_DIGIT               0
WAKEUP                        0
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~#
root@am43xx-epos-evm:~# cat /sys/kernel/debug/omapdss/dispc
DISPC_REVISION                                     00000030
DISPC_SYSCONFIG                                    00002011
DISPC_SYSSTATUS                                    00000001
DISPC_IRQSTATUS                                    0000002e
DISPC_IRQENABLE                                    0000d640
DISPC_CONTROL                                      00018309
DISPC_CONFIG                                       00000204
DISPC_CAPABLE                                      000003ff
DISPC_LINE_STATUS                                  0000011d
DISPC_LINE_NUMBER                                  00000000
DISPC_GLOBAL_ALPHA                                 000000ff
DISPC_DEFAULT_COLOR(LCD)                           00000000
DISPC_TRANS_COLOR(LCD)                             00000000
DISPC_SIZE_MGR(LCD)                                01df031f
DISPC_DEFAULT_COLOR(LCD)                           00000000
DISPC_TRANS_COLOR(LCD)                             00000000
DISPC_TIMING_H(LCD)                                00f0d11d
DISPC_TIMING_V(LCD)                                00a0160c
DISPC_POL_FREQ(LCD)                                00003000
DISPC_DIVISORo(LCD)                                00010006
DISPC_SIZE_MGR(LCD)                                01df031f
DISPC_DATA_CYCLE1(LCD)                             00000000
DISPC_DATA_CYCLE2(LCD)                             00000000
DISPC_DATA_CYCLE3(LCD)                             00000000
DISPC_CPR_COEF_R(LCD)                              00000000
DISPC_CPR_COEF_G(LCD)                              00000000
DISPC_CPR_COEF_B(LCD)                              00000000
DISPC_OVL_BA0(GFX)                                 a0000000
DISPC_OVL_BA1(GFX)                                 a0000000
DISPC_OVL_POSITION(GFX)                            00000000
DISPC_OVL_SIZE(GFX)                                01df031f
DISPC_OVL_ATTRIBUTES(GFX)                          00000090
DISPC_OVL_FIFO_THRESHOLD(GFX)                      03ff03c0
DISPC_OVL_FIFO_SIZE_STATUS(GFX)                    00000400
DISPC_OVL_ROW_INC(GFX)                             00000001
DISPC_OVL_PIXEL_INC(GFX)                           00000001
DISPC_OVL_PRELOAD(GFX)                             00000100
DISPC_OVL_WINDOW_SKIP(GFX)                         00000000
DISPC_OVL_TABLE_BA(GFX)                            00000000
DISPC_OVL_BA0(VID1)                                00000000
DISPC_OVL_BA1(VID1)                                00000000
DISPC_OVL_POSITION(VID1)                           00000000
DISPC_OVL_SIZE(VID1)                               00000000
DISPC_OVL_ATTRIBUTES(VID1)                         00008000
DISPC_OVL_FIFO_THRESHOLD(VID1)                     03ff03c0
DISPC_OVL_FIFO_SIZE_STATUS(VID1)                   00000400
DISPC_OVL_ROW_INC(VID1)                            00000001
DISPC_OVL_PIXEL_INC(VID1)                          00000001
DISPC_OVL_PRELOAD(VID1)                            00000100
DISPC_OVL_FIR(VID1)                                00000000
DISPC_OVL_PICTURE_SIZE(VID1)                       00000000
DISPC_OVL_ACCU0(VID1)                              00000000
DISPC_OVL_ACCU1(VID1)                              00000000
DISPC_OVL_PRELOAD(VID1)                            00000100
DISPC_OVL_BA0(VID2)                                00000000
DISPC_OVL_BA1(VID2)                                00000000
DISPC_OVL_POSITION(VID2)                           00000000
DISPC_OVL_SIZE(VID2)                               00000000
DISPC_OVL_ATTRIBUTES(VID2)                         00008000
DISPC_OVL_FIFO_THRESHOLD(VID2)                     03ff03c0
DISPC_OVL_FIFO_SIZE_STATUS(VID2)                   00000400
DISPC_OVL_ROW_INC(VID2)                            00000001
DISPC_OVL_PIXEL_INC(VID2)                          00000001
DISPC_OVL_PRELOAD(VID2)                            00000100
DISPC_OVL_FIR(VID2)                                00000000
DISPC_OVL_PICTURE_SIZE(VID2)                       00000000
DISPC_OVL_ACCU0(VID2)                              00000000
DISPC_OVL_ACCU1(VID2)                              00000000
DISPC_OVL_PRELOAD(VID2)                            00000100
DISPC_OVL_FIR_COEF_H_0(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_1(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_2(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_3(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_4(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_5(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_6(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_7(VID1)                       00000000
DISPC_OVL_FIR_COEF_HV_0(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_1(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_2(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_3(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_4(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_5(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_6(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV_7(VID1)                      00000000
DISPC_OVL_CONV_COEF_0(VID1)                        0199012a
DISPC_OVL_CONV_COEF_1(VID1)                        012a0000
DISPC_OVL_CONV_COEF_2(VID1)                        079c0730
DISPC_OVL_CONV_COEF_3(VID1)                        0000012a
DISPC_OVL_CONV_COEF_4(VID1)                        00000205
DISPC_OVL_FIR_COEF_V_0(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_2(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_3(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_4(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_5(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_6(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_7(VID1)                       00000000
DISPC_OVL_FIR_COEF_H_0(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_1(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_2(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_3(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_4(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_5(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_6(VID2)                       00000000
DISPC_OVL_FIR_COEF_H_7(VID2)                       00000000
DISPC_OVL_FIR_COEF_HV_0(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_1(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_2(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_3(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_4(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_5(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_6(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV_7(VID2)                      00000000
DISPC_OVL_CONV_COEF_0(VID2)                        0199012a
DISPC_OVL_CONV_COEF_1(VID2)                        012a0000
DISPC_OVL_CONV_COEF_2(VID2)                        079c0730
DISPC_OVL_CONV_COEF_3(VID2)                        0000012a
DISPC_OVL_CONV_COEF_4(VID2)                        00000205
DISPC_OVL_FIR_COEF_V_0(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_2(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_3(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_4(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_5(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_6(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_7(VID2)                       00000000
root@am43xx-epos-evm:~#


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* Re: [PATCH RESEND] drivers: video: metronomefb: avoid out-of-bounds array access
From: Tomi Valkeinen @ 2014-01-09 12:21 UTC (permalink / raw)
  To: Michal Nazarewicz
  Cc: Jean-Christophe Plagniol-Villard, linux-fbdev, linux-kernel
In-Reply-To: <1385743903-9079-1-git-send-email-mpn@google.com>

[-- Attachment #1: Type: text/plain, Size: 2135 bytes --]

On 2013-11-29 18:51, Michal Nazarewicz wrote:
> From: Michal Nazarewicz <mina86@mina86.com>
> 
> load_waveform function checks whether padding bytes in stuff2a
> and stuff2b are all zero, but does so by treating those arrays
> as a single longer array.  Since the structure is packed, and
> the size sum matches, it all works, but creates some confusion
> in the code.
> 
> This commit changes the stuff2a and stuff2b arrays into pad1 and
> pad2 fields such that they cover the same bytes as the arrays
> covered, and changes the check in the load_waveform function so
> that the fields are read instead of iterating over an arary.
> 
> It also renames the other “stuff” fields to “ignore*” fields to
> give them more semantic meaning.
> 
> Signed-off-by: Michal Nazarewicz <mina86@mina86.com>
> ---
>  drivers/video/metronomefb.c | 17 ++++++++---------
>  1 file changed, 8 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/video/metronomefb.c b/drivers/video/metronomefb.c
> index 195cc2d..4f36a2b 100644
> --- a/drivers/video/metronomefb.c
> +++ b/drivers/video/metronomefb.c
> @@ -126,7 +126,7 @@ static struct fb_var_screeninfo metronomefb_var = {
>  
>  /* the waveform structure that is coming from userspace firmware */
>  struct waveform_hdr {
> -	u8 stuff[32];
> +	u8 ignore1[32];
>  
>  	u8 wmta[3];
>  	u8 fvsn;
> @@ -134,13 +134,14 @@ struct waveform_hdr {
>  	u8 luts;
>  	u8 mc;
>  	u8 trc;
> -	u8 stuff3;
> +	u8 ignore2;
>  
>  	u8 endb;
>  	u8 swtb;
> -	u8 stuff2a[2];
> +	u32 pad1; /* u16 halfof(pad1) */
>  
> -	u8 stuff2b[3];
> +	/* u16 halfof(pad1) */
> +	u8 pad2;

I don't quite follow what those comments mean...

I know nothing of the hw in question, but I guess there's some reason
the stuff2a and stuff2b has been separate, and there's even a blank line
between. If they pad a particular block in the data structure, doesn't
your change make it confusing?

It wouldn't be too pad to have those 5 fields as separate ones. One u16
for the stuff2a, and u16 + u8 for the stuff2b. It'd be simple to check
that those are zero.

 Tomi



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* Re: [PATCH] video: mmp: add device tree support
From: Zhou Zhu @ 2014-01-09 12:09 UTC (permalink / raw)
  To: Jingoo Han, 'Sascha Hauer'
  Cc: linux-fbdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	'Tomi Valkeinen',
	'Jean-Christophe Plagniol-Villard',
	'Haojian Zhuang', Chao Xie, Guoqing Li,
	devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <000301cf0d0e$91f29090$b5d7b1b0$%han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>

Sascha/Jingoo,
Thank you for your review!

On 01/09/2014 03:43 PM, Jingoo Han wrote:
> On Thursday, January 09, 2014 4:32 PM, Sascha Hauer wrote:
>> On Thu, Jan 09, 2014 at 01:13:14PM +0800, Zhou Zhu wrote:
>>> add device tree support for mmp fb/controller
>>> the description at Documentation/devicetree/bindings/fb/mmp-disp.txt
>>>
>>> Signed-off-by: Zhou Zhu <zzhu3@marvell.com>
>>> ---
>>>   Documentation/devicetree/bindings/fb/mmp-disp.txt |   71 ++++++++++++
>>>   drivers/video/mmp/fb/mmpfb.c                      |   71 ++++++++----
>>>   drivers/video/mmp/hw/mmp_ctrl.c                   |  120 ++++++++++++++++-----
>>>   3 files changed, 217 insertions(+), 45 deletions(-)
>>>   create mode 100644 Documentation/devicetree/bindings/fb/mmp-disp.txt
>>>

[...]

>> +fb: fb {
>> +	compatible = "marvell,mmp-fb";
>
> This compatible should have the specific SoC name in it, not just
> 'mmp'. Otherwise you can't properly distinguish between this version and
> future versions of the mmp core.
>
We are using a same display IP for all mmp serial SoCs, and there would 
be inside register to get version. So I am planning put same compatible 
here for all SoCs using this IP.
Would it be ok if I update compatible to "marvell,mmpdcx-fb"? "mmpdcx" 
is the IP name.

 >
 >> +	marvell,fb-name = "mmp_fb";
 >> +	marvell,path-name = "mmp_pnpath";
 >
 > You're not going to use this string to reference to another node, do
 > you? We have phandles for this.
 >
I will update it in v2.

 >> +	marvell,overlay-id = <0>;
 >> +	marvell,dmafetch-id = <1>;
 >> +	marvell,default-pixfmt = <0x108>;
 >> +};
 >> +
 >> +disp: disp@d420b000 {
 >> +	compatible = "marvell,mmp-disp";
 >> +	reg = <0xd420b000 0x1fc>;
 >> +	interrupts = <0 41 0x4>;
 >> +	marvell,disp-name = "mmp_disp";
 >> +	marvell,path-num = <1>;
 >> +	marvell,clk-name = "LCDCIHCLK";
 >
 > Don't pass clk names like this. We have a documented clock binding, use
 > it.
 >
The patches to add dt support in common clk in our platforms are not 
upstreamed yet. As there's only one clock in this device, could I remove 
clock name related codes and direct use: devm_clk_get(dev, NULL)?

>
>>
>>> +#ifdef CONFIG_OF
>>> +	struct device_node *np;
>>> +#else
>>>   	struct mmp_buffer_driver_mach_info *mi;
>>> +#endif
>>>   	struct fb_info *info = 0;
>>>   	struct mmpfb_info *fbi = 0;
>>> -	int ret, modes_num;
>>> -
>>> -	mi = pdev->dev.platform_data;
>>> -	if (mi = NULL) {
>>> -		dev_err(&pdev->dev, "no platform data defined\n");
>>> -		return -EINVAL;
>>> -	}
>>> +	int ret = -EINVAL, modes_num;
>>> +	int overlay_id, dmafetch_id;
>>> +	const char *path_name;
>>>
>>>   	/* initialize fb */
>>>   	info = framebuffer_alloc(sizeof(struct mmpfb_info), &pdev->dev);
>>>   	if (info = NULL)
>>>   		return -ENOMEM;
>>>   	fbi = info->par;
>>> -	if (!fbi) {
>>> -		ret = -EINVAL;
>>> +	if (!fbi)
>>> +		goto failed;
>>> +
>>> +#ifdef CONFIG_OF
>>
>> Just because your kernel build does have CONFIG_OF enabled doesn't mean
>> it's actually started with a devicetree. You need to make a runtime
>> decision, not compile time.
>
> Yes, right.
> As Sascha Hauer said, you need to make a runtime decision,
> instead of compile time. Please keep the same binary for
> both cases (CONFIG_OF is 'enabled' and 'disabled').
>
> For example,
>
> 	if (pdev->dev.of_node) {
> 		// DT code
> 	} else {
> 		// Non-DT code
> 	}
>
Thank you for your suggestion. I will update the code to dynamic in v2.

-- 
Thanks, -Zhou

^ permalink raw reply

* Re: [PATCH] video: Replace local macro with PCI standard macro
From: Tomi Valkeinen @ 2014-01-09 12:05 UTC (permalink / raw)
  To: Yijing Wang
  Cc: Jean-Christophe Plagniol-Villard, linux-fbdev, linux-kernel,
	Hanjun Guo
In-Reply-To: <1386242718-24372-1-git-send-email-wangyijing@huawei.com>

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On 2013-12-05 13:25, Yijing Wang wrote:
> Replace local macro TGA_BUS_PCI with PCI standard
> marco dev_is_pci().
> 
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
> ---
>  drivers/video/tgafb.c |   16 +++++-----------
>  1 files changed, 5 insertions(+), 11 deletions(-)

Thanks, queued for 3.14.

 Tomi



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* RE: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
From: Hiremath, Vaibhav @ 2014-01-09  8:31 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <52CE5D6F.3050700@ti.com>


> -----Original Message-----
> From: Valkeinen, Tomi
> Sent: Thursday, January 09, 2014 1:57 PM
> To: Hiremath, Vaibhav; Ivaylo Dimitrov; Ivaylo Dimitrov
> Cc: Tony Lindgren; linux-omap@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-fbdev@vger.kernel.org
> Subject: Re: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
> 
> On 2014-01-09 10:08, Hiremath, Vaibhav wrote:
> 
> > No, that's what is causing issue to me. Can you try predefined address flow?
> > Just to highlight, I get UNDERFLOW during boot itself, immediately when it
> gets mapped to userspace.
> >
> > Boot LOG:
> >
> 
> > [    4.822549] Freeing unused kernel memory: 440K (c0919000 - c0987000)
> > [    5.276615] OMAPFB: pan_display(0)
> > [    5.276625] OMAPFB: setcmap
> > [    5.276635] OMAPFB: setcmap
> > [    5.293518] OMAPFB: user mmap region start a0000000, len 1536000, off 0
> > [    5.300171] omapdss APPLY error: FIFO UNDERFLOW on gfx, disabling the
> overlay
> 
> Hmm that's interesting... So you have some tool that's ran early, which draws
> something on the screen? Or maybe that's X starting?
> 

It's initial demo, not sure whether you heard of MATRIX demo. I am running Matrix demo
As part of init script.

> Ah... I think I understand now. As I mentioned, AM4x has issues already.
> I think the CPU/others can block DSS when accessing memory. So, if we have
> bad caching for the mapped framebuffer, the CPU will use more bandwidth
> when reading/writing to it, and that will cause DSS to underflow.
> 

Yeah, AM4x already has some issues but I am comparing normal dma_alloc and reserved
Memory and I see different behavior and it could be due to bad caching for the mapped buffers.

Thanks,
Vaibhav

^ permalink raw reply

* RE: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
From: Hiremath, Vaibhav @ 2014-01-09  8:31 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <52CE5C1A.3070603@ti.com>


> -----Original Message-----
> From: Valkeinen, Tomi
> Sent: Thursday, January 09, 2014 1:52 PM
> To: Hiremath, Vaibhav; Ivaylo Dimitrov
> Cc: Tony Lindgren; linux-omap@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-fbdev@vger.kernel.org
> Subject: Re: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
> 
> On 2014-01-09 07:06, Hiremath, Vaibhav wrote:
> 
> > I am seeing underflow issue on AM43x device if I use omapfb_vram argument.
> > Did you see this on OMAP?
> >
> > I am using "omapfb_vram\x10M@0xA0000000", and I believe it is correct way
> of usage.
> 
> Hmm ok... The AM4x seems to have issues anyway, as we're seeing underflows
> easily in other situations also.
> 
> Well, there's a small difference in the allocation. The normal dma alloc uses
> dma_alloc_attrs() and passes DMA_ATTR_WRITE_COMBINE as a flag, whereas
> allocating from the absolute address just uses the piece of memory. I couldn't
> find how to set write-combine for the abs memory area.
> 
> Then again, that's for CPU caching, so I don't see why it would affect DSS as
> such (but that's still something we should measure, cpu read/write perf for
> normal and abs allocation).
> 
> The only thought I have is that somehow the reserved memory area is missing
> some configuration that is done for the rest of the memory. But that's purely a
> guess, this is totally out of my area of expertise...
> 
> Vaibhav, just to be sure, can you run both with normal dma_alloc and with the
> reserve, and verify that the dispc register dumps are the same?
> I don't see how they could be different, but just to be sure.
> 

Will check and update you shortly.

Thanks,
Vaibhav

^ permalink raw reply

* Re: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
From: Tomi Valkeinen @ 2014-01-09  8:27 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EDB141E@DBDE04.ent.ti.com>

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On 2014-01-09 10:08, Hiremath, Vaibhav wrote:

> No, that's what is causing issue to me. Can you try predefined address flow?
> Just to highlight, I get UNDERFLOW during boot itself, immediately when it gets mapped to userspace.
> 
> Boot LOG:
> 

> [    4.822549] Freeing unused kernel memory: 440K (c0919000 - c0987000)
> [    5.276615] OMAPFB: pan_display(0)
> [    5.276625] OMAPFB: setcmap
> [    5.276635] OMAPFB: setcmap
> [    5.293518] OMAPFB: user mmap region start a0000000, len 1536000, off 0
> [    5.300171] omapdss APPLY error: FIFO UNDERFLOW on gfx, disabling the overlay

Hmm that's interesting... So you have some tool that's ran early, which
draws something on the screen? Or maybe that's X starting?

Ah... I think I understand now. As I mentioned, AM4x has issues already.
I think the CPU/others can block DSS when accessing memory. So, if we
have bad caching for the mapped framebuffer, the CPU will use more
bandwidth when reading/writing to it, and that will cause DSS to underflow.

 Tomi



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* Re: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
From: Tomi Valkeinen @ 2014-01-09  8:21 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <79CD15C6BA57404B839C016229A409A83EDB11F5@DBDE04.ent.ti.com>

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On 2014-01-09 07:06, Hiremath, Vaibhav wrote:

> I am seeing underflow issue on AM43x device if I use omapfb_vram argument.
> Did you see this on OMAP?
> 
> I am using "omapfb_vram=10M@0xA0000000", and I believe it is correct way of usage.

Hmm ok... The AM4x seems to have issues anyway, as we're seeing
underflows easily in other situations also.

Well, there's a small difference in the allocation. The normal dma alloc
uses dma_alloc_attrs() and passes DMA_ATTR_WRITE_COMBINE as a flag,
whereas allocating from the absolute address just uses the piece of
memory. I couldn't find how to set write-combine for the abs memory area.

Then again, that's for CPU caching, so I don't see why it would affect
DSS as such (but that's still something we should measure, cpu
read/write perf for normal and abs allocation).

The only thought I have is that somehow the reserved memory area is
missing some configuration that is done for the rest of the memory. But
that's purely a guess, this is totally out of my area of expertise...

Vaibhav, just to be sure, can you run both with normal dma_alloc and
with the reserve, and verify that the dispc register dumps are the same?
I don't see how they could be different, but just to be sure.

 Tomi



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* RE: RE: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
From: Hiremath, Vaibhav @ 2014-01-09  8:08 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <52CE5123.9050702@gmail.com>

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Ivaylo Dimitrov
> Sent: Thursday, January 09, 2014 1:05 PM
> To: Hiremath, Vaibhav; Valkeinen, Tomi; Tony Lindgren; Ivaylo Dimitrov
> Cc: linux-omap@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> fbdev@vger.kernel.org
> Subject: Re: RE: [PATCH 1/2] ARM: omapfb: add coherent dma memory support
> 
> 
> On 09.01.2014 07:06, Hiremath, Vaibhav wrote:
> > Tomi,
> >
> > I am seeing underflow issue on AM43x device if I use omapfb_vram argument.
> > Did you see this on OMAP?
> >
> > I am using "omapfb_vram\x10M@0xA0000000", and I believe it is correct way
> of usage.
> >
> > Thanks,
> > Vaibhav
> >
> 
> AFAIK underflow interrupts could come from badly calculated DSS core clock or
> bad HW resizer setup and should be unrelated to the memory allocation. It
> might be something similar to the problem I have on N900
> - see https://lkml.org/lkml/2014/1/6/173
> 

I can see the difference when I really "omapfb_vram" command line argument.

Without omapfb_vram in bootargs 
-------------------------------------------
bootargs=console=ttyO0,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait mem\x128M 
consoleblank=0 clocksource=gp_timer consoleblank=0 earlyprintk omapfb.debug=y omapdss.debug=y

I do not get UNDERFLOW during boot.

With omapfb_vram in the bootargs
---------------------------------------------
bootargs=console=ttyO0,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait mem\x128M 
consoleblank=0 clocksource=gp_timer consoleblank=0 earlyprintk omapfb_vram\x10M@0xA0000000 
omapfb.debug=y omapdss.debug=y

I always get UNDERFLOW during boot itself.

> Is it possible to upload the video you have problems with, so me to test it on
> N900? So far I didn't see any underflow issues on it (N900 is OMAP3, in case
> you're not aware), no matter the resolution of the videos I played(up to 720p),
> however I didn't test the part that allocates the memory on a pre-defined
> address. Though I don't think that should matter.

No, that's what is causing issue to me. Can you try predefined address flow?
Just to highlight, I get UNDERFLOW during boot itself, immediately when it gets mapped to userspace.

Boot LOG:

[    1.443021] OMAPFB: omapfb_probe
[    1.446137] OMAPFB: create 3 framebuffers
[    1.446178] OMAPFB: fb_infos allocated
[    1.446198] OMAPFB: allocating 1536000 bytes for fb 0
[    1.451044] OMAPFB: allocated VRAM paddr a0000000, vaddr ca000000
[    1.451069] OMAPFB: region0 phys a0000000 virt ca000000 size\x1536000
[    1.451086] OMAPFB: region1 phys 00000000 virt   (null) size=0
[    1.451100] OMAPFB: region2 phys 00000000 virt   (null) size=0
[    1.451109] OMAPFB: fbmems allocated
[    1.451363] OMAPFB: check_fb_var 0
[    1.451386] OMAPFB: max frame size 1536000, line size 3200
[    1.451401] OMAPFB: xres = 800, yres = 480, vxres = 800, vyres = 480
[    1.451414] OMAPFB: set_fb_fix
[    1.460278] OMAPFB: fb_infos initialized
[    1.465325] OMAPFB: set_par(0)
[    1.465384] OMAPFB: set_fb_fix
[    1.465393] OMAPFB: apply_changes, fb 0, ovl 0
[    1.465443] OMAPFB: setup_overlay 0, posx 0, posy 0, outw 800, outh 480
[    1.465450] OMAPFB: paddr a0000000
[    1.465592] OMAPFB: pan_display(0)
[    1.465600] OMAPFB: setcmap
[    1.465607] OMAPFB: setcmap
[    1.474504] Console: switching to colour frame buffer device 100x30
[    1.474528] OMAPFB: pan_display(0)
[    1.474534] OMAPFB: setcmap
[    1.482185] OMAPFB: setcmap
[    1.484808] OMAPFB: framebuffers registered
[    1.484839] OMAPFB: apply_changes, fb 0, ovl 0
[    1.484857] OMAPFB: setup_overlay 0, posx 0, posy 0, outw 800, outh 480
[    1.484870] OMAPFB: paddr a0000000
[    1.484919] OMAPFB: apply_changes, fb 1, ovl 1
[    1.485010] OMAPFB: apply_changes, fb 2, ovl 2
[    1.485111] OMAPFB: create_framebuffers done
[    1.485128] OMAPFB: mgr->apply'ed
[    1.489793] OMAPFB: create sysfs for fbs
[    1.489816] OMAPFB: create sysfs for fbs

....

[    4.822549] Freeing unused kernel memory: 440K (c0919000 - c0987000)
[    5.276615] OMAPFB: pan_display(0)
[    5.276625] OMAPFB: setcmap
[    5.276635] OMAPFB: setcmap
[    5.293518] OMAPFB: user mmap region start a0000000, len 1536000, off 0
[    5.300171] omapdss APPLY error: FIFO UNDERFLOW on gfx, disabling the overlay

...

[   20.499076] OMAPFB: pan_display(0)
[   20.499085] OMAPFB: setcmap
[   20.499093] OMAPFB: setcmap
[   20.544419] OMAPFB: check_var(0)
[   20.544631] OMAPFB: check_fb_var 0
[   20.544644] OMAPFB: max frame size 1536000, line size 3200
[   20.544651] OMAPFB: xres = 800, yres = 480, vxres = 800, vyres = 480
[   20.544699] OMAPFB: set_par(0)
[   20.544706] OMAPFB: set_fb_fix
[   20.544712] OMAPFB: apply_changes, fb 0, ovl 0
[   20.544762] OMAPFB: setup_overlay 0, posx 0, posy 0, outw 800, outh 480
[   20.544767] OMAPFB: paddr a0000000
[   20.544798] OMAPFB: pan_display(0)
[   20.544802] OMAPFB: setcmap
[   20.544859] OMAPFB: pan_display(0)
[   20.544865] OMAPFB: setcmap
[   20.544872] OMAPFB: setcmap
[   20.553841] OMAPFB: setcmap
[   23.002160] OMAPFB: user mmap region start a0000000, len 1536000, off 0

Thanks,
Vaibhav

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