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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2023 18:00:41.2017 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f65b210a-d244-40c9-285e-08db9db98a09 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4361 Signed-off-by: Mario Limonciello --- cxgb4/configs/t4-config-default.txt | 6 +++--- cxgb4/configs/t5-config-default.txt | 6 +++--- cxgb4/configs/t5-config-hashfilter.txt | 6 +++--- cxgb4/configs/t6-config-default.txt | 6 +++--- cxgb4/configs/t6-config-hashfilter.txt | 8 ++++---- 5 files changed, 16 insertions(+), 16 deletions(-) diff --git a/cxgb4/configs/t4-config-default.txt b/cxgb4/configs/t4-config-default.txt index 1774b4d9..b758fc5e 100644 --- a/cxgb4/configs/t4-config-default.txt +++ b/cxgb4/configs/t4-config-default.txt @@ -17,7 +17,7 @@ # finite. This requires balancing the configuration/operation needs of # device drivers across OSes and a large number of customer application. # -# Some of the more important resources to allocate and their constaints are: +# Some of the more important resources to allocate and their constraints are: # 1. Virtual Interfaces: 128. # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions # must use a power of 2 Ingress Queues. @@ -275,7 +275,7 @@ # to directly select the type of Physical Function to which they wish to be # attached. # -# Note that the actual values used for the PCI-E Intelectual Property will be +# Note that the actual values used for the PCI-E Intellectual Property will be # 1 less than those below since that's the way it "counts" things. For # readability, we use the number we actually mean ... # @@ -491,7 +491,7 @@ # MPS features a 196608 bytes ingress buffer that is used for ingress buffering # for packets from the wire as well as the loopback path of the L2 switch. The -# folling params control how the buffer memory is distributed and the L2 flow +# following params control how the buffer memory is distributed and the L2 flow # control settings: # # bg_mem: %-age of mem to use for port/buffer group diff --git a/cxgb4/configs/t5-config-default.txt b/cxgb4/configs/t5-config-default.txt index 44fdfad7..352af3c0 100644 --- a/cxgb4/configs/t5-config-default.txt +++ b/cxgb4/configs/t5-config-default.txt @@ -18,7 +18,7 @@ # are finite. This requires balancing the configuration/operation needs of # device drivers across OSes and a large number of customer application. # -# Some of the more important resources to allocate and their constaints are: +# Some of the more important resources to allocate and their constraints are: # 1. Virtual Interfaces: 256. # 2. Ingress Queues with Free Lists: 1024. # 3. Egress Queues: 128K. @@ -310,7 +310,7 @@ # to directly select the type of Physical Function to which they wish to be # attached. # -# Note that the actual values used for the PCI-E Intelectual Property will be +# Note that the actual values used for the PCI-E Intellectual Property will be # 1 less than those below since that's the way it "counts" things. For # readability, we use the number we actually mean ... # @@ -540,7 +540,7 @@ # MPS features a 196608 bytes ingress buffer that is used for ingress buffering # for packets from the wire as well as the loopback path of the L2 switch. The -# folling params control how the buffer memory is distributed and the L2 flow +# following params control how the buffer memory is distributed and the L2 flow # control settings: # # bg_mem: %-age of mem to use for port/buffer group diff --git a/cxgb4/configs/t5-config-hashfilter.txt b/cxgb4/configs/t5-config-hashfilter.txt index e106f24b..38e8ef4b 100644 --- a/cxgb4/configs/t5-config-hashfilter.txt +++ b/cxgb4/configs/t5-config-hashfilter.txt @@ -18,7 +18,7 @@ # are finite. This requires balancing the configuration/operation needs of # device drivers across OSes and a large number of customer application. # -# Some of the more important resources to allocate and their constaints are: +# Some of the more important resources to allocate and their constraints are: # 1. Virtual Interfaces: 256. # 2. Ingress Queues with Free Lists: 1024. # 3. Egress Queues: 128K. @@ -316,7 +316,7 @@ # to directly select the type of Physical Function to which they wish to be # attached. # -# Note that the actual values used for the PCI-E Intelectual Property will be +# Note that the actual values used for the PCI-E Intellectual Property will be # 1 less than those below since that's the way it "counts" things. For # readability, we use the number we actually mean ... # @@ -408,7 +408,7 @@ # MPS features a 196608 bytes ingress buffer that is used for ingress buffering # for packets from the wire as well as the loopback path of the L2 switch. The -# folling params control how the buffer memory is distributed and the L2 flow +# following params control how the buffer memory is distributed and the L2 flow # control settings: # # bg_mem: %-age of mem to use for port/buffer group diff --git a/cxgb4/configs/t6-config-default.txt b/cxgb4/configs/t6-config-default.txt index b0145ab2..bc000316 100644 --- a/cxgb4/configs/t6-config-default.txt +++ b/cxgb4/configs/t6-config-default.txt @@ -18,7 +18,7 @@ # are finite. This requires balancing the configuration/operation needs of # device drivers across OSes and a large number of customer application. # -# Some of the more important resources to allocate and their constaints are: +# Some of the more important resources to allocate and their constraints are: # 1. Virtual Interfaces: 256. # 2. Ingress Queues with Free Lists: 1024. # 3. Egress Queues: 128K. @@ -327,7 +327,7 @@ # to directly select the type of Physical Function to which they wish to be # attached. # -# Note that the actual values used for the PCI-E Intelectual Property will be +# Note that the actual values used for the PCI-E Intellectual Property will be # 1 less than those below since that's the way it "counts" things. For # readability, we use the number we actually mean ... # @@ -556,7 +556,7 @@ # MPS features a 196608 bytes ingress buffer that is used for ingress buffering # for packets from the wire as well as the loopback path of the L2 switch. The -# folling params control how the buffer memory is distributed and the L2 flow +# following params control how the buffer memory is distributed and the L2 flow # control settings: # # bg_mem: %-age of mem to use for port/buffer group diff --git a/cxgb4/configs/t6-config-hashfilter.txt b/cxgb4/configs/t6-config-hashfilter.txt index f8c78210..921a30d2 100644 --- a/cxgb4/configs/t6-config-hashfilter.txt +++ b/cxgb4/configs/t6-config-hashfilter.txt @@ -18,7 +18,7 @@ # are finite. This requires balancing the configuration/operation needs of # device drivers across OSes and a large number of customer application. # -# Some of the more important resources to allocate and their constaints are: +# Some of the more important resources to allocate and their constraints are: # 1. Virtual Interfaces: 256. # 2. Ingress Queues with Free Lists: 1024. # 3. Egress Queues: 128K. @@ -167,7 +167,7 @@ # LE_DB_CONFIG reg[0x19c04] = 0x00000000/0x02040000 # LE IPv4 compression disabled - # EXTN_HASH_IPV4 Diable + # EXTN_HASH_IPV4 Disable #LE_DB_RSP_CODE_0 reg[0x19c74] = 0x00000004/0x0000000f # TCAM_ACTV_HIT = 4 @@ -304,7 +304,7 @@ # to directly select the type of Physical Function to which they wish to be # attached. # -# Note that the actual values used for the PCI-E Intelectual Property will be +# Note that the actual values used for the PCI-E Intellectual Property will be # 1 less than those below since that's the way it "counts" things. For # readability, we use the number we actually mean ... # @@ -393,7 +393,7 @@ # MPS features a 196608 bytes ingress buffer that is used for ingress buffering # for packets from the wire as well as the loopback path of the L2 switch. The -# folling params control how the buffer memory is distributed and the L2 flow +# following params control how the buffer memory is distributed and the L2 flow # control settings: # # bg_mem: %-age of mem to use for port/buffer group -- 2.25.1