From: Moritz Fischer <mdf@kernel.org>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
Alan Tull <atull@kernel.org>, Moritz Fischer <mdf@kernel.org>,
linux-fpga@vger.kernel.org, Marek Vasut <marek.vasut@gmail.com>
Subject: Re: [PATCH] fpga: add simple userspace interface to trigger FPGA programming
Date: Mon, 11 Dec 2017 14:05:45 -0800 [thread overview]
Message-ID: <20171211220545.GA12954@tyrael.ni.corp.natinst.com> (raw)
In-Reply-To: <818e6012-6919-7428-1d05-79d5b89a5e1d@gmail.com>
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On Sun, Dec 10, 2017 at 02:59:36PM -0800, Florian Fainelli wrote:
>
>
> On 12/10/2017 02:44 PM, Thomas Petazzoni wrote:
> > Hello,
> >
> > On Sat, 9 Dec 2017 22:03:06 -0600, Alan Tull wrote:
> >
> >>> We can actually use the Linux device driver model to do that though.
> >>> Assuming all peripherals behind the FPGA do have the FPGA manager's
> >>> struct device as a parent (which they should), when there is a bistream
> >>> load request, we ought to be able to teardown all of these child struct
> >>> device's and their corresponding drivers (unbind), load the bistream,
> >>> and then rebind the drivers accordingly.
> >>
> >> Hi Florain,
> >>
> >> FPGA regions are a way of handling all that plus the bridges [1] or
> >> are you proposing something else? An FPGA region knows what manager
> >> to use and what bridges (if any) needs to be disabled while
> >> programming is happening. Applying a DT overlay targeting a FPGA
> >> region is used to program the FPGA.
> >
> > I thought my initial patch made it clear: DT overlays are not an
> > applicable solution for my use case, for two reasons:
> >
> > 1. My platform doesn't use Device Tree at all.
> >
> > 2. The device implemented in the FPGA is self-discoverable because it
> > sits on a PCI bus, so there is no point in doing a static
> > description of the device in a DT overlay.
>
> Agreed, sorry for side tracking the discussion a bit on that topic.
I do agree that wee need to find a solution for this. We should not
force people to use DT overlays in a system that is discoverable,
or out of tree hacks.
>
> >
> > So, solutions based on DT overlays are quite irrelevant for my use
> > case. Am I missing something here ?
>
> I don't think you are, in fact, as it stands today, unless your FPGA has
> a bistream which is already loaded, in which case you don't really need
> the FPGA manager framework at all, this framework is completely useless
> in offering people the ability to load bistreams on non-DT enabled
> platforms without resorting to out of tree hacks like this one for instance:
>
> https://github.com/ffainelli/linux/commit/78a4824165d7bf627c1b2dbb645ce013185331de
>
> So what needs to be done so we can allow people to take full advantage
> of the fact that FPGAs are (re)programmable, even when the platform does
> not use DT?
I like your suggestion of tying into the device model, to tear down
everything underneath.
Would making the PCIe root complex a child to a FPGA region work? Seems
clumsy. Do we have other examples of devices reloading firmware
triggered by userland?
- Moritz
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next prev parent reply other threads:[~2017-12-11 22:05 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-04 15:43 [PATCH] fpga: add simple userspace interface to trigger FPGA programming Thomas Petazzoni
2017-12-04 15:50 ` Alan Tull
2017-12-04 15:58 ` Thomas Petazzoni
2017-12-04 16:25 ` Alan Tull
2017-12-04 16:49 ` Moritz Fischer
2017-12-04 17:30 ` Alan Tull
2017-12-09 18:05 ` Florian Fainelli
2017-12-10 4:03 ` Alan Tull
2017-12-10 22:44 ` Thomas Petazzoni
2017-12-10 22:59 ` Florian Fainelli
2017-12-11 22:05 ` Moritz Fischer [this message]
2017-12-11 23:32 ` Alan Tull
2017-12-13 6:30 ` yves.vandervennet
2017-12-13 5:23 ` Thomas Petazzoni
2017-12-13 15:59 ` Alan Tull
2017-12-14 5:27 ` Thomas Petazzoni
2017-12-14 20:10 ` Alan Tull
2017-12-10 22:42 ` Thomas Petazzoni
2018-08-11 15:01 ` Philippe De Muyter
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