From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: Date: Mon, 11 Dec 2017 14:05:45 -0800 From: Moritz Fischer Subject: Re: [PATCH] fpga: add simple userspace interface to trigger FPGA programming Message-ID: <20171211220545.GA12954@tyrael.ni.corp.natinst.com> References: <20171204154315.30128-1-thomas.petazzoni@free-electrons.com> <20171210234410.67e48bae@windsurf.lan> <818e6012-6919-7428-1d05-79d5b89a5e1d@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="r5Pyd7+fXNt84Ff3" Content-Disposition: inline In-Reply-To: <818e6012-6919-7428-1d05-79d5b89a5e1d@gmail.com> To: Florian Fainelli Cc: Thomas Petazzoni , Alan Tull , Moritz Fischer , linux-fpga@vger.kernel.org, Marek Vasut List-ID: --r5Pyd7+fXNt84Ff3 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Dec 10, 2017 at 02:59:36PM -0800, Florian Fainelli wrote: >=20 >=20 > On 12/10/2017 02:44 PM, Thomas Petazzoni wrote: > > Hello, > >=20 > > On Sat, 9 Dec 2017 22:03:06 -0600, Alan Tull wrote: > >=20 > >>> We can actually use the Linux device driver model to do that though. > >>> Assuming all peripherals behind the FPGA do have the FPGA manager's > >>> struct device as a parent (which they should), when there is a bistre= am > >>> load request, we ought to be able to teardown all of these child stru= ct > >>> device's and their corresponding drivers (unbind), load the bistream, > >>> and then rebind the drivers accordingly. =20 > >> > >> Hi Florain, > >> > >> FPGA regions are a way of handling all that plus the bridges [1] or > >> are you proposing something else? An FPGA region knows what manager > >> to use and what bridges (if any) needs to be disabled while > >> programming is happening. Applying a DT overlay targeting a FPGA > >> region is used to program the FPGA. > >=20 > > I thought my initial patch made it clear: DT overlays are not an > > applicable solution for my use case, for two reasons: > >=20 > > 1. My platform doesn't use Device Tree at all. > >=20 > > 2. The device implemented in the FPGA is self-discoverable because it > > sits on a PCI bus, so there is no point in doing a static > > description of the device in a DT overlay. >=20 > Agreed, sorry for side tracking the discussion a bit on that topic. I do agree that wee need to find a solution for this. We should not force people to use DT overlays in a system that is discoverable, or out of tree hacks. >=20 > >=20 > > So, solutions based on DT overlays are quite irrelevant for my use > > case. Am I missing something here ? >=20 > I don't think you are, in fact, as it stands today, unless your FPGA has > a bistream which is already loaded, in which case you don't really need > the FPGA manager framework at all, this framework is completely useless > in offering people the ability to load bistreams on non-DT enabled > platforms without resorting to out of tree hacks like this one for instan= ce: >=20 > https://github.com/ffainelli/linux/commit/78a4824165d7bf627c1b2dbb645ce01= 3185331de >=20 > So what needs to be done so we can allow people to take full advantage > of the fact that FPGAs are (re)programmable, even when the platform does > not use DT? I like your suggestion of tying into the device model, to tear down everything underneath. Would making the PCIe root complex a child to a FPGA region work? Seems clumsy. Do we have other examples of devices reloading firmware triggered by userland? - Moritz --r5Pyd7+fXNt84Ff3 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEowQ4eJSlIZpNWnl2UVwKRFcJcNgFAlovATMACgkQUVwKRFcJ cNh/SAf9G/obCRo7/8UMCe9CdrxJipegiZy6OUuc/TMOP/n7s9H1MSDsE+S+IT4X xO6LZ72PZAavFzmkSNr6e6uvhZoOLoGHa8Phu+XFPW05sXIMaYUma4MGvb35DntP QqldtiA5kQGD8ia1Ck8+Bno0neltEJjmlwXM8DxrY8b2VvRyZEpm0tf/iF3JXDNW OiKUPcEpFt2QKTS+NWS4pv2SfbrYHyHXtY3ARaY/Cs7yytf0+G7JS6ab+DRsEI4b xx0pO83YMClktYjw7OLQ14OVQpBnXPl4N6RRwTHs/0ith+enuuFva/3zMSmrwrJa tnNAcSOL0xV+KkFiX38lODwMv5HYnw== =pEM9 -----END PGP SIGNATURE----- --r5Pyd7+fXNt84Ff3--