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From: matthew.gerlach@linux.intel.com
To: hao.wu@intel.com, trix@redhat.com, linux-fpga@vger.kernel.org,
	linux-kernel@vger.kernel.org, yilun.xu@intel.com,
	russell.h.weight@intel.com, mdf@kernel.org
Cc: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: [PATCH] fpga: dfl: pci: gracefully handle misconfigured port entries
Date: Tue, 20 Apr 2021 10:27:40 -0700	[thread overview]
Message-ID: <20210420172740.707259-1-matthew.gerlach@linux.intel.com> (raw)

From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

Gracefully ignore misconfigured port entries encountered in
incorrect FPGA images.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
 drivers/fpga/dfl-pci.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
index b44523e..660d3b6 100644
--- a/drivers/fpga/dfl-pci.c
+++ b/drivers/fpga/dfl-pci.c
@@ -212,6 +212,7 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
 	int port_num, bar, i, ret = 0;
 	resource_size_t start, len;
 	void __iomem *base;
+	int bars = 0;
 	u32 offset;
 	u64 v;
 
@@ -228,6 +229,7 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
 	if (dfl_feature_is_fme(base)) {
 		start = pci_resource_start(pcidev, 0);
 		len = pci_resource_len(pcidev, 0);
+		bars |= BIT(0);
 
 		dfl_fpga_enum_info_add_dfl(info, start, len);
 
@@ -253,9 +255,21 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
 			 */
 			bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
 			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
+			if (bars & BIT(bar)) {
+				dev_warn(&pcidev->dev, "skipping bad port BAR %d\n", bar);
+				continue;
+			}
+
 			start = pci_resource_start(pcidev, bar) + offset;
-			len = pci_resource_len(pcidev, bar) - offset;
+			len = pci_resource_len(pcidev, bar);
+			if (offset >= len) {
+				dev_warn(&pcidev->dev, "bad port offset %u >= %pa\n",
+					 offset, &len);
+				continue;
+			}
 
+			len -= offset;
+			bars |= BIT(bar);
 			dfl_fpga_enum_info_add_dfl(info, start, len);
 		}
 	} else if (dfl_feature_is_port(base)) {
-- 
1.8.3.1


             reply	other threads:[~2021-04-20 17:26 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-20 17:27 matthew.gerlach [this message]
2021-04-20 18:49 ` [PATCH] fpga: dfl: pci: gracefully handle misconfigured port entries Tom Rix
2021-04-20 19:19   ` matthew.gerlach
2021-04-26  1:21     ` Moritz Fischer
2021-04-21  5:25 ` Wu, Hao
2021-04-21 17:06   ` matthew.gerlach
2021-04-26  2:39     ` Wu, Hao

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