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From: Ivan Bornyakov <i.bornyakov@metrotek.ru>
To: Xu Yilun <yilun.xu@intel.com>
Cc: mdf@kernel.org, hao.wu@intel.com, trix@redhat.com,
	conor.dooley@microchip.com, linux-kernel@vger.kernel.org,
	linux-fpga@vger.kernel.org, system@metrotek.ru
Subject: Re: [PATCH v4] fpga: microchip-spi: add Microchip FPGA manager
Date: Sat, 19 Feb 2022 09:16:27 +0300	[thread overview]
Message-ID: <20220219061627.3oanqx5glsyq47xk@x260> (raw)
In-Reply-To: <20220218160555.GA1333893@yilunxu-OptiPlex-7050>

Hi, Yilun.

On Sat, Feb 19, 2022 at 12:05:55AM +0800, Xu Yilun wrote:
> On Thu, Feb 17, 2022 at 10:18:51PM +0300, Ivan Bornyakov wrote:
> > +static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
> > +{
> > +	ssize_t bitstream_start = 0, bitstream_size;
> > +	struct mpf_priv *priv = mgr->priv;
> > +	struct spi_device *spi = priv->spi;
> > +	struct device *dev = &mgr->dev;
> > +	u8 tmp_buf[SPI_FRAME_SIZE + 1];
> > +	int ret, i;
> > +
> > +	if (crc_ccitt(0, buf, count)) {
> > +		dev_err(dev, "CRC error\n");
> > +
> > +		return -EINVAL;
> > +	}
> > +
> > +	bitstream_start = lookup_block_start(BITSTREAM_ID, buf, count);
> > +	if (bitstream_start < 0) {
> > +		dev_err(dev, "Failed to find bitstream start %zd\n",
> > +			bitstream_start);
> > +
> > +		return bitstream_start;
> > +	}
> > +
> > +	bitstream_size = parse_bitstream_size(buf, count);
> > +	if (bitstream_size < 0) {
> > +		dev_err(dev, "Failed to parse bitstream size %zd\n",
> > +			bitstream_size);
> > +
> > +		return bitstream_size;
> > +	}
> > +
> > +	if (bitstream_start + bitstream_size * SPI_FRAME_SIZE > count) {
> > +		dev_err(dev,
> > +			"Bitstram outruns firmware. Bitstream start %zd, bitstream size %zd, firmware size %zu\n",
> 
> 			 Bitstream
> 
> > +			bitstream_start, bitstream_size * SPI_FRAME_SIZE, count);
> > +
> > +		return -EFAULT;
> > +	}
> > +
> 
> If I understand right, this function assumes the users provide the
> entire image buffer. But it is possible the image buffer is from a
> scatter list and the callback would be called several times.
> 

That is unfortunate. I thought fpga_manager_ops->write_sg() is here for
that purpose.

>
> Maybe the bitstream info at the head of the image could be parsed in
> write_init(), and this requires the driver fill the
> fpga_manager_ops.initial_header_size
>

Header size is not known beforehand and is stored in 25th byte of the
image.

Overall, thanks for detailed review


  reply	other threads:[~2022-02-19  6:36 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-14 13:38 [PATCH] fpga: microsemi-spi: add Microsemi FPGA manager Ivan Bornyakov
2022-02-14 19:22 ` kernel test robot
2022-02-14 20:34 ` kernel test robot
2022-02-15 11:58 ` [PATCH v2] " Ivan Bornyakov
2022-02-15 17:37   ` Conor Dooley
2022-02-15 17:52     ` Moritz Fischer
2022-02-15 18:05       ` Ivan Bornyakov
2022-02-16 12:55   ` Conor.Dooley
2022-02-16 15:56 ` [PATCH v3] fpga: microchip-spi: add Microchip " Ivan Bornyakov
2022-02-17 19:18 ` [PATCH v4] " Ivan Bornyakov
2022-02-18 15:22   ` Conor.Dooley
2022-02-19  5:45     ` Ivan Bornyakov
2022-02-18 16:05   ` Xu Yilun
2022-02-19  6:16     ` Ivan Bornyakov [this message]
2022-02-19 10:42       ` Ivan Bornyakov

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