From: kernel test robot <lkp@intel.com>
To: Ivan Bornyakov <i.bornyakov@metrotek.ru>
Cc: kbuild-all@lists.01.org, mdf@kernel.org, hao.wu@intel.com,
yilun.xu@intel.com, trix@redhat.com, conor.dooley@microchip.com,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
linux-fpga@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, system@metrotek.ru,
Ivan Bornyakov <i.bornyakov@metrotek.ru>
Subject: Re: [PATCH v10 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager
Date: Sat, 7 May 2022 00:12:41 +0800 [thread overview]
Message-ID: <202205070006.tWQ4lFSL-lkp@intel.com> (raw)
In-Reply-To: <20220506125710.25550-3-i.bornyakov@metrotek.ru>
Hi Ivan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on next-20220506]
[cannot apply to robh/for-next linus/master v5.18-rc5 v5.18-rc4 v5.18-rc3 v5.18-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Ivan-Bornyakov/Microchip-Polarfire-FPGA-manager/20220506-212355
base: 38a288f5941ef03752887ad86f2d85442358c99a
config: m68k-allmodconfig (https://download.01.org/0day-ci/archive/20220507/202205070006.tWQ4lFSL-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/9c87e90e1315e8a6028064516aef34a05f3f9625
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Ivan-Bornyakov/Microchip-Polarfire-FPGA-manager/20220506-212355
git checkout 9c87e90e1315e8a6028064516aef34a05f3f9625
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=m68k SHELL=/bin/bash drivers/fpga/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/fpga/microchip-spi.c: In function 'mpf_ops_parse_header':
>> drivers/fpga/microchip-spi.c:118:31: error: implicit declaration of function 'get_unaligned_le32' [-Werror=implicit-function-declaration]
118 | block_start = get_unaligned_le32(buf + block_start_offset);
| ^~~~~~~~~~~~~~~~~~
>> drivers/fpga/microchip-spi.c:152:26: error: implicit declaration of function 'get_unaligned_le16' [-Werror=implicit-function-declaration]
152 | components_num = get_unaligned_le16(buf + MPF_DATA_SIZE_OFFSET);
| ^~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/get_unaligned_le32 +118 drivers/fpga/microchip-spi.c
79
80 static int mpf_ops_parse_header(struct fpga_manager *mgr,
81 struct fpga_image_info *info,
82 const char *buf, size_t count)
83 {
84 size_t component_size_byte_num, component_size_byte_off,
85 components_size_start = 0, bitstream_start = 0,
86 block_id_offset, block_start_offset, i;
87 u8 header_size, blocks_num, block_id;
88 u32 block_start, component_size;
89 u16 components_num;
90
91 if (!buf) {
92 dev_err(&mgr->dev, "Image buffer is not provided\n");
93 return -EINVAL;
94 }
95
96 header_size = *(buf + MPF_HEADER_SIZE_OFFSET);
97 if (header_size > count) {
98 info->header_size = header_size;
99 return -EAGAIN;
100 }
101
102 /*
103 * Go through look-up table to find out where actual bitstream starts
104 * and where sizes of components of the bitstream lies.
105 */
106 blocks_num = *(buf + header_size - 1);
107 block_id_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET;
108 block_start_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_START_OFFSET;
109
110 header_size += blocks_num * MPF_LOOKUP_TABLE_RECORD_SIZE;
111 if (header_size > count) {
112 info->header_size = header_size;
113 return -EAGAIN;
114 }
115
116 while (blocks_num--) {
117 block_id = *(buf + block_id_offset);
> 118 block_start = get_unaligned_le32(buf + block_start_offset);
119
120 switch (block_id) {
121 case MPF_BITSTREAM_ID:
122 info->header_size = bitstream_start = block_start;
123 if (block_start > count)
124 return -EAGAIN;
125
126 break;
127 case MPF_COMPONENTS_SIZE_ID:
128 components_size_start = block_start;
129 break;
130 default:
131 break;
132 }
133
134 if (bitstream_start && components_size_start)
135 break;
136
137 block_id_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
138 block_start_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
139 }
140
141 if (!bitstream_start || !components_size_start) {
142 dev_err(&mgr->dev, "Failed to parse header look-up table\n");
143 return -EFAULT;
144 }
145
146 /*
147 * Parse bitstream size.
148 * Sizes of components of the bitstream are 22-bits long placed next
149 * to each other. Image header should be extended by now up to where
150 * actual bitstream starts, so no need for overflow check anymore.
151 */
> 152 components_num = get_unaligned_le16(buf + MPF_DATA_SIZE_OFFSET);
153
154 for (i = 0; i < components_num; i++) {
155 component_size_byte_num =
156 (i * MPF_BITS_PER_COMPONENT_SIZE) / BITS_PER_BYTE;
157 component_size_byte_off =
158 (i * MPF_BITS_PER_COMPONENT_SIZE) % BITS_PER_BYTE;
159
160 component_size = get_unaligned_le32(buf +
161 components_size_start +
162 component_size_byte_num);
163 component_size >>= component_size_byte_off;
164 component_size &= GENMASK(MPF_BITS_PER_COMPONENT_SIZE - 1, 0);
165
166 info->data_size += component_size * MPF_SPI_FRAME_SIZE;
167 }
168
169 return 0;
170 }
171
--
0-DAY CI Kernel Test Service
https://01.org/lkp
next prev parent reply other threads:[~2022-05-06 16:24 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-06 12:57 [PATCH v10 0/3] Microchip Polarfire FPGA manager Ivan Bornyakov
2022-05-06 12:57 ` [PATCH v10 1/3] fpga: fpga-mgr: support bitstream offset in image buffer Ivan Bornyakov
2022-05-06 12:57 ` [PATCH v10 2/3] fpga: microchip-spi: add Microchip MPF FPGA manager Ivan Bornyakov
2022-05-06 16:12 ` kernel test robot [this message]
2022-05-06 12:57 ` [PATCH v10 3/3] dt-bindings: fpga: add binding doc for microchip-spi fpga mgr Ivan Bornyakov
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