From: Ivan Bornyakov <i.bornyakov@metrotek.ru>
To: "Daniel Glöckner" <dg@emlix.com>
Cc: mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com,
trix@redhat.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, linux-fpga@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
system@metrotek.ru
Subject: Re: [PATCH v5 1/2] fpga: ecp5-spi: add Lattice ECP5 FPGA manager
Date: Tue, 9 Aug 2022 09:54:31 +0300 [thread overview]
Message-ID: <20220809065431.nbfopsvx6teja37i@x260> (raw)
In-Reply-To: <20220801072448.GA11993@homes.emlix.com>
On Mon, Aug 01, 2022 at 09:24:49AM +0200, Daniel Glöckner wrote:
> Hi,
>
> On Tue, Jul 19, 2022 at 02:23:34PM +0300, Ivan Bornyakov wrote:
> > + /* Enter init mode */
> > + gpiod_set_value(priv->program, 1);
> > +
> > + ret = ecp5_poll_gpio(priv->init, true);
> > + if (!ret)
> > + ret = ecp5_poll_gpio(priv->done, false);
> > +
> > + if (ret) {
> > + dev_err(dev, "Failed to go to initialization mode\n");
> > + return ret;
> > + }
>
> To me the documentation looks like the chip will deassert INITN after
> tINITL regardless of the PROGRAMN signal. At 55ns max tINITL is too
> short to reliably sample INITN while it is asserted when we have
> interrupts enabled. Can you confirm that INITN stays asserted as long
> as PROGRAMN is asserted?
I confirm that INITN stays asserted while PROGRAMN is asserted, just
rechecked.
next prev parent reply other threads:[~2022-08-09 7:22 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-19 11:23 [PATCH v5 0/2] Lattice ECP5 FPGA manager Ivan Bornyakov
2022-07-19 11:23 ` [PATCH v5 1/2] fpga: ecp5-spi: add " Ivan Bornyakov
2022-07-29 12:41 ` Daniel Glöckner
2022-08-01 7:24 ` Daniel Glöckner
2022-08-09 6:54 ` Ivan Bornyakov [this message]
2022-07-19 11:23 ` [PATCH v5 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr Ivan Bornyakov
2022-07-29 9:01 ` Daniel Glöckner
2022-07-29 14:57 ` Xu Yilun
2022-07-29 16:33 ` Ivan Bornyakov
2022-07-29 17:49 ` Daniel Glöckner
2022-07-21 7:44 ` [PATCH v5 0/2] Lattice ECP5 FPGA manager Xu Yilun
2022-07-21 8:54 ` Ivan Bornyakov
2022-07-27 6:00 ` Ivan Bornyakov
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