[PATCH] fpga: versal: Add support for 44-bit DMA operations

[PATCH] fpga: versal: Add support for 44-bit DMA operations

[Nava kishore Manne]

The existing implementation support only 32-bit DMA operation.
So, it fails to load the bitstream for the high DDR designs(Beyond 4GB).
To fix this issue update the DMA mask handling logic to support 44-bit
DMA operations.

Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
---
 drivers/fpga/versal-fpga.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
index e1601b3a345b..3710e8f01be2 100644
--- a/drivers/fpga/versal-fpga.c
+++ b/drivers/fpga/versal-fpga.c
@@ -48,7 +48,7 @@ static int versal_fpga_probe(struct platform_device *pdev)
 	struct fpga_manager *mgr;
 	int ret;
 
-	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
 	if (ret < 0) {
 		dev_err(dev, "no usable DMA configuration\n");
 		return ret;
-- 
2.25.1

RE: [PATCH] fpga: versal: Add support for 44-bit DMA operations

[Pandey, Radhey Shyam]

> -----Original Message-----
> From: Manne, Nava kishore <nava.kishore.manne@amd.com>
> Sent: Tuesday, October 3, 2023 12:44 PM
> To: mdf@kernel.org; hao.wu@intel.com; yilun.xu@intel.com;
> trix@redhat.com; linux-fpga@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: Pandey, Radhey Shyam <radhey.shyam.pandey@amd.com>
> Subject: [PATCH] fpga: versal: Add support for 44-bit DMA operations
> 
> The existing implementation support only 32-bit DMA operation.
> So, it fails to load the bitstream for the high DDR designs(Beyond 4GB).
> To fix this issue update the DMA mask handling logic to support 44-bit DMA
> operations.
> 
> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
As I reviewed it on internal list - adding my reviewed tag here as well.
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Thanks!
> ---
>  drivers/fpga/versal-fpga.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c index
> e1601b3a345b..3710e8f01be2 100644
> --- a/drivers/fpga/versal-fpga.c
> +++ b/drivers/fpga/versal-fpga.c
> @@ -48,7 +48,7 @@ static int versal_fpga_probe(struct platform_device
> *pdev)
>  	struct fpga_manager *mgr;
>  	int ret;
> 
> -	ret = dma_set_mask_and_coherent(&pdev->dev,
> DMA_BIT_MASK(32));
> +	ret = dma_set_mask_and_coherent(&pdev->dev,
> DMA_BIT_MASK(44));
>  	if (ret < 0) {
>  		dev_err(dev, "no usable DMA configuration\n");
>  		return ret;
> --
> 2.25.1

Re: [PATCH] fpga: versal: Add support for 44-bit DMA operations

[Xu Yilun]

On Tue, Oct 03, 2023 at 12:44:09PM +0530, Nava kishore Manne wrote:
> The existing implementation support only 32-bit DMA operation.
> So, it fails to load the bitstream for the high DDR designs(Beyond 4GB).
> To fix this issue update the DMA mask handling logic to support 44-bit

This is the HW defined DMA addressing capability. Does the device
only support up to 44 bits DMA? Any Doc?

Thanks,
Yilun

> DMA operations.
> 
> Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> ---
>  drivers/fpga/versal-fpga.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
> index e1601b3a345b..3710e8f01be2 100644
> --- a/drivers/fpga/versal-fpga.c
> +++ b/drivers/fpga/versal-fpga.c
> @@ -48,7 +48,7 @@ static int versal_fpga_probe(struct platform_device *pdev)
>  	struct fpga_manager *mgr;
>  	int ret;
>  
> -	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
> +	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
>  	if (ret < 0) {
>  		dev_err(dev, "no usable DMA configuration\n");
>  		return ret;
> -- 
> 2.25.1
> 

RE: [PATCH] fpga: versal: Add support for 44-bit DMA operations

[Manne, Nava kishore]

Hi Yilun,

	Thanks for providing the review comments.
Please find my response inline.

> -----Original Message-----
> From: Xu Yilun <yilun.xu@linux.intel.com>
> Sent: Saturday, October 7, 2023 12:47 PM
> To: Manne, Nava kishore <nava.kishore.manne@amd.com>
> Cc: mdf@kernel.org; hao.wu@intel.com; yilun.xu@intel.com;
> trix@redhat.com; linux-fpga@vger.kernel.org; linux-kernel@vger.kernel.org;
> Pandey, Radhey Shyam <radhey.shyam.pandey@amd.com>
> Subject: Re: [PATCH] fpga: versal: Add support for 44-bit DMA operations
> 
> On Tue, Oct 03, 2023 at 12:44:09PM +0530, Nava kishore Manne wrote:
> > The existing implementation support only 32-bit DMA operation.
> > So, it fails to load the bitstream for the high DDR designs(Beyond 4GB).
> > To fix this issue update the DMA mask handling logic to support 44-bit
> 
> This is the HW defined DMA addressing capability. Does the device only
> support up to 44 bits DMA? Any Doc?
> 
The versal platform supports a maximum physical address size is 44-bit in AArch64.
For more details, please refer the Versal TRM (Memory space- section):
 https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Memory-Space

Regards,
Navakishore.

Re: [PATCH] fpga: versal: Add support for 44-bit DMA operations

[Xu Yilun]

On Tue, Oct 10, 2023 at 05:37:43AM +0000, Manne, Nava kishore wrote:
> Hi Yilun,
> 
> 	Thanks for providing the review comments.
> Please find my response inline.
> 
> > -----Original Message-----
> > From: Xu Yilun <yilun.xu@linux.intel.com>
> > Sent: Saturday, October 7, 2023 12:47 PM
> > To: Manne, Nava kishore <nava.kishore.manne@amd.com>
> > Cc: mdf@kernel.org; hao.wu@intel.com; yilun.xu@intel.com;
> > trix@redhat.com; linux-fpga@vger.kernel.org; linux-kernel@vger.kernel.org;
> > Pandey, Radhey Shyam <radhey.shyam.pandey@amd.com>
> > Subject: Re: [PATCH] fpga: versal: Add support for 44-bit DMA operations
> > 
> > On Tue, Oct 03, 2023 at 12:44:09PM +0530, Nava kishore Manne wrote:
> > > The existing implementation support only 32-bit DMA operation.
> > > So, it fails to load the bitstream for the high DDR designs(Beyond 4GB).
> > > To fix this issue update the DMA mask handling logic to support 44-bit
> > 
> > This is the HW defined DMA addressing capability. Does the device only
> > support up to 44 bits DMA? Any Doc?
> > 
> The versal platform supports a maximum physical address size is 44-bit in AArch64.
> For more details, please refer the Versal TRM (Memory space- section):
>  https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Memory-Space

Acked-by: Xu Yilun <yilun.xu@intel.com>

Applied.

> 
> Regards,
> Navakishore.
>