From: Marco Felsch <m.felsch@pengutronix.de>
To: Conor Dooley <conor@kernel.org>
Cc: conor.dooley@microchip.com, v.georgiev@metrotek.ru,
mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com,
trix@redhat.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, linux-fpga@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
Subject: Re: [PATCH] dt-bindings: fpga: microchip,mpf-spi-fpga-mgr: document CPOL/CPHA support
Date: Thu, 22 Feb 2024 21:02:30 +0100 [thread overview]
Message-ID: <20240222200230.ulhguouu37nm6inu@pengutronix.de> (raw)
In-Reply-To: <20240222-rotten-truck-cf5e4b681ac1@spud>
On 24-02-22, Conor Dooley wrote:
> On Wed, Feb 21, 2024 at 08:12:47PM +0100, Marco Felsch wrote:
> > Microchip FPGAs can communicate in different modes, so document them to
> > avoid dt-validate warnings.
>
> Are you sure it can "communicate in different modes"?
No I'm not but I didn't found an overview within the FPGA datasheet [1]
which modes are supported. What I did found was an note which says:
"""
1. Parameters are referenced to the active edge of SCK, which depends on
the configured SPI protocol (for example, Motorola SPI mode uses rising
edge as active edge if SPO = 0)
"""
Therefore I thought that this can be configured somehow differently.
[1] https://www.microsemi.com/document-portal/doc_view/136519-ds0141-polarfire-fpga-datasheet
> The documentation actually says "Motorla SPI Mode 3 is required to
> communicate with M2S, M2GL, and MPF devices using dedicated system
> controller SPI port" with mode 3 being SPO = SPH = 1:
> https://www.microsemi.com/document-portal/doc_view/137543-spi-directc-sp1-v2-0-user-guide
Thanks for the Pointer, there are plenty documents for the Polarfire
FPGA.
> I suspect the answer is that it can actually communicate in different
> modes (because I don't recall setting those options), but the binding
> should enforce the correct way of doing it IMO.
Sure, I will rephrase my commit message to:
"""
dt-bindings: fpga: microchip,mpf-spi-fpga-mgr: document CPOL/CPHA
Using the dedicated system controller SPI port requires Motorola SPI
Mode 3 according the SPI-DirectC v2.0 User Guid [1]. So require the
spi-cpol and spi-cpha to be set.
[1] https://www.microsemi.com/document-portal/doc_view/137543-spi-directc-sp1-v2-0-user-guide
"""
Regards,
Marco
>
> Cheers,
> Conor.
>
> >
> > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> > ---
> > .../devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
> > index a157eecfb5fc..bb9a7d16db60 100644
> > --- a/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
> > +++ b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml
> > @@ -22,6 +22,9 @@ properties:
> > description: SPI chip select
> > maxItems: 1
> >
> > + spi-cpol: true
> > + spi-cpha: true
> > +
> > required:
> > - compatible
> > - reg
> > --
> > 2.39.2
> >
> >
next prev parent reply other threads:[~2024-02-22 20:03 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-21 19:12 [PATCH] dt-bindings: fpga: microchip,mpf-spi-fpga-mgr: document CPOL/CPHA support Marco Felsch
2024-02-22 17:23 ` Conor Dooley
2024-02-22 20:02 ` Marco Felsch [this message]
2024-02-23 19:13 ` Conor Dooley
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