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X-CSE-ConnectionGUID: Efk0HLtdQoyfmo6ObaiG9A== X-CSE-MsgGUID: 24mJEfUDRF2iLaBiwXtWfw== X-IronPort-AV: E=Sophos;i="6.08,254,1712646000"; d="asc'?scan'208";a="28316196" X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Jun 2024 03:43:22 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 21 Jun 2024 03:43:11 -0700 Received: from wendy (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Fri, 21 Jun 2024 03:43:09 -0700 Date: Fri, 21 Jun 2024 11:42:50 +0100 From: Conor Dooley To: Conor Dooley , , , , , , , , , , , Subject: Re: [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming binding description Message-ID: <20240621-promptly-railroad-8b83cd213282@wendy> References: <20240620144440.125374-1-iansdannapel@gmail.com> <20240620-rubdown-buffing-312d308c2d4d@spud> <20240621-operation-trapezoid-844948baa860@thorsis.com> Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="UQWwXbW7nYjmx+9s" Content-Disposition: inline In-Reply-To: <20240621-operation-trapezoid-844948baa860@thorsis.com> --UQWwXbW7nYjmx+9s Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jun 21, 2024 at 10:11:24AM +0200, Alexander Dahl wrote: > Am Thu, Jun 20, 2024 at 04:47:41PM +0100 schrieb Conor Dooley: > > On Thu, Jun 20, 2024 at 04:44:40PM +0200, iansdannapel@gmail.com wrote: > > > From: Ian Dannapel > > >=20 > > > Add device tree binding documentation for configuring Efinix FPGA > > > using serial SPI passive programming mode. > > >=20 > > > Signed-off-by: Ian Dannapel > > > --- > > > .../bindings/fpga/efnx,fpga-passive-spi.yaml | 76 +++++++++++++++++= ++ > > > 1 file changed, 76 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/fpga/efnx,fpga-= passive-spi.yaml > > >=20 > > > diff --git a/Documentation/devicetree/bindings/fpga/efnx,fpga-passive= -spi.yaml b/Documentation/devicetree/bindings/fpga/efnx,fpga-passive-spi.ya= ml > > > new file mode 100644 > > > index 000000000000..855ceb3b89e8 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/fpga/efnx,fpga-passive-spi.ya= ml > > > @@ -0,0 +1,76 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/fpga/efnx,fpga-passive-spi.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Efinix SPI FPGA Manager > > > + > > > +description: | > > > + Efinix Trion and Titanium Series FPGAs support a method of loading= the > > > + bitstream over what is referred to as "SPI Passive Programming". > > > + Only serial (1x bus width) is supported, setting the programming m= ode > > > + is not in the scope the this manager and must be done elsewhere. > > > + > > > + References: > > > + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-= v2.6.pdf > > > + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.= 0.pdf > > > + > > > +allOf: > > > + - $ref: /schemas/spi/spi-peripheral-props.yaml# > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - efnx,fpga-spi-passive > >=20 > > Ahh, here is the user. Can you please add specific compatibles for the > > Trion and Titanium series FPGAs? And when you do, make the filename > > match a compatible please. > >=20 > > Additionally, why "efnx" and not "efinix"? >=20 > FWIW, there already is "altr,fpga-passive-serial" for Altera devices. >=20 > Not sure why Altera got this short vendor prefix, but that was 2013 > with commit 5db17a71a526 ("of: add vendor prefix for Altera Corp.") > and we probably never know? I think that was the stock ticker name for Altera. > The method of transferring the configuration data over SPI into the > FPGA is comparable. I would go so far to claim a single driver could > support both device families for passive configuration over SPI. I've > done that in a non-public driver for U-Boot few months ago, and used > "efinix,fpga-passive-serial" as a compatible there. The difference is > basically Altera requiring more GPIOs considered, and Efinix keeping > the SPI clock on for some time after data is already transfered. That'd prob be helpful to comment on the driver patch. I'd still like to see device specific compatibles here for the trion and titanium though. Thanks, Conor. --UQWwXbW7nYjmx+9s Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZnVZKgAKCRB4tDGHoIJi 0gZSAQDqlDo1xAYJ4/GeyETk0Bz7ymm1MdkQONKwauwXvxEGAQD/VMjKhnkITsG7 +q2ZN93g1i58IH9Q+MyMd2fYx2QuHg8= =VM7l -----END PGP SIGNATURE----- --UQWwXbW7nYjmx+9s--