From: "Nuno Sá via B4 Relay" <devnull+nuno.sa.analog.com@kernel.org>
To: linux-clk@vger.kernel.org, linux-fpga@vger.kernel.org
Cc: Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Moritz Fischer <mdf@kernel.org>, Wu Hao <hao.wu@intel.com>,
Xu Yilun <yilun.xu@intel.com>, Tom Rix <trix@redhat.com>
Subject: [PATCH RESEND v3 3/6] include: fpga: adi-axi-common: add new helper macros
Date: Mon, 21 Apr 2025 15:58:04 +0100 [thread overview]
Message-ID: <20250421-dev-axi-clkgen-limits-v3-3-4203b4fed2c9@analog.com> (raw)
In-Reply-To: <20250421-dev-axi-clkgen-limits-v3-0-4203b4fed2c9@analog.com>
From: Nuno Sá <nuno.sa@analog.com>
Add new helper macros and enums to help identifying the platform and some
characteristics of it at runtime.
Signed-off-by: Nuno Sá <nuno.sa@analog.com>
---
include/linux/fpga/adi-axi-common.h | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/include/linux/fpga/adi-axi-common.h b/include/linux/fpga/adi-axi-common.h
index 141ac3f251e6f256526812b9d55cd440a2a46e76..a832ef9b37473ca339a2a2ff8a4a5716d428fd29 100644
--- a/include/linux/fpga/adi-axi-common.h
+++ b/include/linux/fpga/adi-axi-common.h
@@ -12,6 +12,8 @@
#define ADI_AXI_COMMON_H_
#define ADI_AXI_REG_VERSION 0x0000
+#define ADI_AXI_REG_FPGA_INFO 0x001C
+#define ADI_AXI_REG_FPGA_VOLTAGE 0x0140
#define ADI_AXI_PCORE_VER(major, minor, patch) \
(((major) << 16) | ((minor) << 8) | (patch))
@@ -20,4 +22,37 @@
#define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff)
#define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff)
+#define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff)
+#define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff)
+#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info) (((info) >> 8) & 0xff)
+#define ADI_AXI_INFO_FPGA_VOLTAGE(val) ((val) & 0xffff)
+
+enum adi_axi_fpga_technology {
+ ADI_AXI_FPGA_TECH_UNKNOWN = 0,
+ ADI_AXI_FPGA_TECH_SERIES7,
+ ADI_AXI_FPGA_TECH_ULTRASCALE,
+ ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS,
+};
+
+enum adi_axi_fpga_family {
+ ADI_AXI_FPGA_FAMILY_UNKNOWN = 0,
+ ADI_AXI_FPGA_FAMILY_ARTIX,
+ ADI_AXI_FPGA_FAMILY_KINTEX,
+ ADI_AXI_FPGA_FAMILY_VIRTEX,
+ ADI_AXI_FPGA_FAMILY_ZYNQ,
+};
+
+enum adi_axi_fpga_speed_grade {
+ ADI_AXI_FPGA_SPEED_UNKNOWN = 0,
+ ADI_AXI_FPGA_SPEED_1 = 10,
+ ADI_AXI_FPGA_SPEED_1L = 11,
+ ADI_AXI_FPGA_SPEED_1H = 12,
+ ADI_AXI_FPGA_SPEED_1HV = 13,
+ ADI_AXI_FPGA_SPEED_1LV = 14,
+ ADI_AXI_FPGA_SPEED_2 = 20,
+ ADI_AXI_FPGA_SPEED_2L = 21,
+ ADI_AXI_FPGA_SPEED_2LV = 22,
+ ADI_AXI_FPGA_SPEED_3 = 30,
+};
+
#endif /* ADI_AXI_COMMON_H_ */
--
2.49.0
next prev parent reply other threads:[~2025-04-21 14:58 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-21 14:58 [PATCH RESEND v3 0/6] clk: clk-axi-clkgen: improvements and some fixes Nuno Sá via B4 Relay
2025-04-21 14:58 ` [PATCH RESEND v3 1/6] clk: clk-axi-clkgen: fix fpfd_max frequency for zynq Nuno Sá via B4 Relay
2025-04-21 14:58 ` [PATCH RESEND v3 2/6] clk: clk-axi-clkgen: make sure to include mod_devicetable.h Nuno Sá via B4 Relay
2025-04-21 14:58 ` Nuno Sá via B4 Relay [this message]
2025-04-24 10:16 ` [PATCH RESEND v3 3/6] include: fpga: adi-axi-common: add new helper macros Xu Yilun
2025-04-28 9:02 ` Nuno Sá
2025-04-21 14:58 ` [PATCH RESEND v3 4/6] clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime Nuno Sá via B4 Relay
2025-04-21 14:58 ` [PATCH RESEND v3 5/6] clk: clk-axi-clkgen move to min/max() Nuno Sá via B4 Relay
2025-04-21 14:58 ` [PATCH RESEND v3 6/6] clk: clk-axi-clkgen: fix coding style issues Nuno Sá via B4 Relay
2025-04-22 8:53 ` [PATCH RESEND v3 0/6] clk: clk-axi-clkgen: improvements and some fixes Nuno Sá
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