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From: Pavel Pisa <pisa@fel.cvut.cz>
To: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: linux-fpga@vger.kernel.org, Michal Simek <michal.simek@amd.com>,
	Jason Gunthorpe <jgg@nvidia.com>, Xu Yilun <yilun.xu@intel.com>,
	Pavel Hronek <hronepa1@fel.cvut.cz>,
	Jiri Novak <jnovak@fel.cvut.cz>,
	Ondrej Ille <ondrej.ille@gmail.com>
Subject: AMD/Xilinx Zynq FPGA manager stopped to work after 6.16.0-g283564a43383
Date: Mon, 4 Aug 2025 15:48:22 +0200	[thread overview]
Message-ID: <202508041548.22955.pisa@fel.cvut.cz> (raw)

Hello Marek and others,

we are running daily tests of SocketCAN stack on mainline and RT kernel
with our CTU CAN FD IP core

   https://canbus.pages.fel.cvut.cz/#can-bus-channels-mutual-latency-testing

It seems that the setup is broken after the mainlie kernel version
from 2025-07-29, 6.16.0-g283564a43383. There is only one commit
identified in drivers/fpga after the last working version

  zynq_fpga: use sgtable-based scatterlist wrappers

The last working mainlne kernel version is recorded in the
last graph data 

  https://canbus.pages.fel.cvut.cz/can-latester/inspect.html

We use the dtbocfg out of tree module to initiate update
by devicetree overlay but fpga manager is mainline one
and all worked for years correctly. The log messages

[  104.934323] dtbocfg: loading out-of-tree module taints kernel.
[  104.940681] dtbocfg: 0.1.0
[  104.943543] dtbocfg: OK
[  105.022979] fpga_manager fpga0: writing system.bit.bin to Xilinx Zynq FPGA Manager
[  105.097721] fpga_manager fpga0: Unable to DMA map (TO_DEVICE)
[  105.103562] fpga_manager fpga0: Error while writing image data to FPGA
[  105.110485] fpga_region region0: failed to load FPGA image
[  105.116059] OF: overlay: overlay changeset pre-apply notifier error -12, target: /fpga-full
[  105.124499] dtbocfg_overlay_item_create: Failed to apply overlay (ret_val=-12)

The overlay source is available there

  https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top/-/blob/can-bench-2x-xcan-4x-ctu/scripts/dts/bitstream+dt.dts

The base zynq-7000.dtsi could be a little dated, but I have not
found related change except name/alias change in mainline

-       fpga_full: fpga-full {
+       fpga_full: fpga-region {

but there are recorded months of correct operation after
this change. I am aware that there has been change of name
alias 

-       amba: amba {
+       amba: axi {

in the sources but again, it has not been problem.

It seems that mapping fails in

        priv->dma_nelms =
            dma_map_sgtable(mgr->dev.parent, sgt, DMA_TO_DEVICE, 0);

The last tested failing mainline kernel version is from this
midnight

   6.16.0-ge991acf1bce7

Do you have some idea what could be a problem?

Do you have suggestion what to test?

Best wishes

                Pavel

                Pavel Pisa
    phone:      +420 603531357
    e-mail:     pisa@cmp.felk.cvut.cz
    Department of Control Engineering FEE CVUT
    Karlovo namesti 13, 121 35, Prague 2
    university: http://control.fel.cvut.cz/
    personal:   http://cmp.felk.cvut.cz/~pisa
    social:     https://social.kernel.org/ppisa
    projects:   https://www.openhub.net/accounts/ppisa
    CAN related:http://canbus.pages.fel.cvut.cz/
    RISC-V education: https://comparch.edu.cvut.cz/
    Open Technologies Research Education and Exchange Services
    https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home

             reply	other threads:[~2025-08-04 13:57 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20250804134826eucas1p1350956e17ae463332a69eaa67dc2f8d7@eucas1p1.samsung.com>
2025-08-04 13:48 ` Pavel Pisa [this message]
2025-08-05 10:01   ` AMD/Xilinx Zynq FPGA manager stopped to work after 6.16.0-g283564a43383 Marek Szyprowski
2025-08-05 17:12     ` Xu Yilun
2025-08-05 18:52       ` Jason Gunthorpe
2025-08-05 19:39         ` Pavel Pisa
2025-08-06  7:11           ` Xu Yilun
2025-08-06  5:22       ` Marek Szyprowski

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