Re: AMD/Xilinx Zynq FPGA manager stopped to work after 6.16.0-g283564a43383

[Pavel Pisa <pisa@fel.cvut.cz>]

Hello all

On Tuesday 05 of August 2025 20:52:35 Jason Gunthorpe wrote:
> On Wed, Aug 06, 2025 at 01:12:46AM +0800, Xu Yilun wrote:
> > @@ -405,12 +405,12 @@ static int zynq_fpga_ops_write(struct fpga_manager
> > *mgr, struct sg_table *sgt) }
> >         }
> >
> > -       priv->dma_nelms =
> > -           dma_map_sgtable(mgr->dev.parent, sgt, DMA_TO_DEVICE, 0);
> > -       if (priv->dma_nelms == 0) {
> > +       err = dma_map_sgtable(mgr->dev.parent, sgt, DMA_TO_DEVICE, 0);
> > +       if (err) {
> >                 dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n");
> > -               return -ENOMEM;
> > +               return err;
> >         }
> > +       priv->dma_nelms = sgt->nents;
>
> That looks pretty good, Marek is certainly right the original had a
> bug.
>
> Jason

Thanks for the fast correction proposal. I have tested the change
at our kernel build, actual mainline version form midnight
rebuild with patch now

  Linux mzapo 6.16.0+ #2 SMP Tue Aug  5 20:59:36 CEST 2025 armv7l GNU/Linux

and it works correctly, DTBOCFG and FPGA manager is able to load
CTU CAN FD IP core design and then driver is loaded and its instances
are setup according to the device tree overlay and driver detects
CAN controllers implemented in FPGA. I have not run whole CAN test
sequence but I do not expect problems there. You can add my

Reported-by: Pavel Pisa <pisa@fel.cvut.cz>
Tested-by: Pavel Pisa <pisa@fel.cvut.cz>

Do you have some idea how fast can the change propagate
into mainline? I would setup automatic patching with
the fix if the testing setup is broken for some longer time.
If the fix can get in mainline in days or week then I would
spent time on that.

Best wishes,

                Pavel

                Pavel Pisa
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