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Tue, 5 Aug 2025 21:40:01 +0200 (CEST) From: Pavel Pisa To: Jason Gunthorpe , Xu Yilun , Marek Szyprowski Subject: Re: AMD/Xilinx Zynq FPGA manager stopped to work after 6.16.0-g283564a43383 Date: Tue, 5 Aug 2025 21:39:59 +0200 User-Agent: KMail/1.9.10 Cc: linux-fpga@vger.kernel.org, Michal Simek , Xu Yilun , Pavel Hronek , Jiri Novak , Ondrej Ille References: <20250805185235.GP184255@nvidia.com> In-Reply-To: <20250805185235.GP184255@nvidia.com> X-KMail-QuotePrefix: > Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <202508052140.00023.pisa@fel.cvut.cz> Hello all On Tuesday 05 of August 2025 20:52:35 Jason Gunthorpe wrote: > On Wed, Aug 06, 2025 at 01:12:46AM +0800, Xu Yilun wrote: > > @@ -405,12 +405,12 @@ static int zynq_fpga_ops_write(struct fpga_manager > > *mgr, struct sg_table *sgt) } > > } > > > > - priv->dma_nelms = > > - dma_map_sgtable(mgr->dev.parent, sgt, DMA_TO_DEVICE, 0); > > - if (priv->dma_nelms == 0) { > > + err = dma_map_sgtable(mgr->dev.parent, sgt, DMA_TO_DEVICE, 0); > > + if (err) { > > dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n"); > > - return -ENOMEM; > > + return err; > > } > > + priv->dma_nelms = sgt->nents; > > That looks pretty good, Marek is certainly right the original had a > bug. > > Jason Thanks for the fast correction proposal. I have tested the change at our kernel build, actual mainline version form midnight rebuild with patch now Linux mzapo 6.16.0+ #2 SMP Tue Aug 5 20:59:36 CEST 2025 armv7l GNU/Linux and it works correctly, DTBOCFG and FPGA manager is able to load CTU CAN FD IP core design and then driver is loaded and its instances are setup according to the device tree overlay and driver detects CAN controllers implemented in FPGA. I have not run whole CAN test sequence but I do not expect problems there. You can add my Reported-by: Pavel Pisa Tested-by: Pavel Pisa Do you have some idea how fast can the change propagate into mainline? I would setup automatic patching with the fix if the testing setup is broken for some longer time. If the fix can get in mainline in days or week then I would spent time on that. Best wishes, Pavel Pavel Pisa phone: +420 603531357 e-mail: pisa@cmp.felk.cvut.cz Department of Control Engineering FEE CVUT Karlovo namesti 13, 121 35, Prague 2 university: http://control.fel.cvut.cz/ personal: http://cmp.felk.cvut.cz/~pisa social: https://social.kernel.org/ppisa projects: https://www.openhub.net/accounts/ppisa CAN related:http://canbus.pages.fel.cvut.cz/ RISC-V education: https://comparch.edu.cvut.cz/ Open Technologies Research Education and Exchange Services https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home