Re: [PATCH 1/1] fpga: zynq_fpga: Fix the wrong usage of dma_map_sgtable()

[Pavel Pisa <pisa@fel.cvut.cz>]

Hello Greg and others,

please, is there some progress/decision about the fix for mainline?

Our daily test of mainline Linux kernel build and test of CAN
communication latency on Zynq system with loaded CTU CAN FD
IP core ends with unresponsive kernel. The last successful
mainline build is from July 29
 
  run-250729-042256-hist+6.16.0-g283564a43383+oaat-kern.json
  https://canbus.pages.fel.cvut.cz/can-latester/

I have analyzed the cause and reported (August 4) that mainline
Zynq runtime FPGA bitstream loading was broken by patch

  37e00703228a ("zynq_fpga: use sgtable-based scatterlist wrappers")

Xu Yilun and others from the FPGA community reacted promptly
with the fix on August 6. The fix has propagated into linux-next.
Is there a plan to accept it for the 6.17 version, or would it be
accepted only for 6.18?

If it is expected that it takes a longer time, or even 6.17
would be released with non-functional Zynq FPGA manager support
then we need to add patching of the broken kernel into our system
because we do not want to lose months of kernel state monitoring
and testing, because more problems could slip in during that time.
We have already caught some problems with the RT variant in the past
thanks to our effort and we have reported quickly even actual
case still during 6.17 merge window. The current breakage
in the mainline test fails our whole series, and we are losing even
RT assessment without changes prepared for the long-term mainline
fails, which is exceptional in our three-year testing effort.

Best wishes,

Pavel


On Wednesday 06 of August 2025 09:06:05 Xu Yilun wrote:
> dma_map_sgtable() returns only 0 or the error code. Read sgt->nents to
> get the number of mapped segments.
>
> CC: stable@vger.kernel.org
> Fixes: 37e00703228a ("zynq_fpga: use sgtable-based scatterlist wrappers")
> Reported-by: Pavel Pisa <pisa@fel.cvut.cz>
> Closes:
> https://lore.kernel.org/linux-fpga/202508041548.22955.pisa@fel.cvut.cz/
> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
> Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
> Tested-by: Pavel Pisa <pisa@fel.cvut.cz>
> ---
>  drivers/fpga/zynq-fpga.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> index 0be0d569589d..b7629a0e4813 100644
> --- a/drivers/fpga/zynq-fpga.c
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -405,12 +405,12 @@ static int zynq_fpga_ops_write(struct fpga_manager
> *mgr, struct sg_table *sgt) }
>  	}
>
> -	priv->dma_nelms =
> -	    dma_map_sgtable(mgr->dev.parent, sgt, DMA_TO_DEVICE, 0);
> -	if (priv->dma_nelms == 0) {
> +	err = dma_map_sgtable(mgr->dev.parent, sgt, DMA_TO_DEVICE, 0);
> +	if (err) {
>  		dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n");
> -		return -ENOMEM;
> +		return err;
>  	}
> +	priv->dma_nelms = sgt->nents;
>
>  	/* enable clock */
>  	err = clk_enable(priv->clk);


-- 
                Pavel Pisa
    phone:      +420 603531357
    e-mail:     pisa@cmp.felk.cvut.cz
    Department of Control Engineering FEE CVUT
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