[PATCH 0/1] Last minute FPGA fix for v6.17-rc1

[PATCH 0/1] Last minute FPGA fix for v6.17-rc1

[Xu Yilun]

Hi Greg:

Pavel found the patch (already in your repo) for v6.17-rc1

  37e00703228a ("zynq_fpga: use sgtable-based scatterlist wrappers")

breaks Xilinux FPGA driver. Here is the fix and I just pushed it in
for-next.

Since it is now rc7, not sure how to address the failure:

 1. revert the original patch 37e00703228a
 2. quick apply this fix
 3. merge this fix into 37e00703228a

Xu Yilun (1):
  fpga: zynq_fpga: Fix the wrong usage of dma_map_sgtable()

 drivers/fpga/zynq-fpga.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

-- 
2.34.1

[PATCH 1/1] fpga: zynq_fpga: Fix the wrong usage of dma_map_sgtable()

[Xu Yilun]

dma_map_sgtable() returns only 0 or the error code. Read sgt->nents to
get the number of mapped segments.

CC: stable@vger.kernel.org
Fixes: 37e00703228a ("zynq_fpga: use sgtable-based scatterlist wrappers")
Reported-by: Pavel Pisa <pisa@fel.cvut.cz>
Closes: https://lore.kernel.org/linux-fpga/202508041548.22955.pisa@fel.cvut.cz/
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
Tested-by: Pavel Pisa <pisa@fel.cvut.cz>
---
 drivers/fpga/zynq-fpga.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
index 0be0d569589d..b7629a0e4813 100644
--- a/drivers/fpga/zynq-fpga.c
+++ b/drivers/fpga/zynq-fpga.c
@@ -405,12 +405,12 @@ static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt)
 		}
 	}
 
-	priv->dma_nelms =
-	    dma_map_sgtable(mgr->dev.parent, sgt, DMA_TO_DEVICE, 0);
-	if (priv->dma_nelms == 0) {
+	err = dma_map_sgtable(mgr->dev.parent, sgt, DMA_TO_DEVICE, 0);
+	if (err) {
 		dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n");
-		return -ENOMEM;
+		return err;
 	}
+	priv->dma_nelms = sgt->nents;
 
 	/* enable clock */
 	err = clk_enable(priv->clk);
-- 
2.34.1

Re: [PATCH 1/1] fpga: zynq_fpga: Fix the wrong usage of dma_map_sgtable()

[Pavel Pisa]

Hello Greg and others,

please, is there some progress/decision about the fix for mainline?

Our daily test of mainline Linux kernel build and test of CAN
communication latency on Zynq system with loaded CTU CAN FD
IP core ends with unresponsive kernel. The last successful
mainline build is from July 29
 
  run-250729-042256-hist+6.16.0-g283564a43383+oaat-kern.json
  https://canbus.pages.fel.cvut.cz/can-latester/

I have analyzed the cause and reported (August 4) that mainline
Zynq runtime FPGA bitstream loading was broken by patch

  37e00703228a ("zynq_fpga: use sgtable-based scatterlist wrappers")

Xu Yilun and others from the FPGA community reacted promptly
with the fix on August 6. The fix has propagated into linux-next.
Is there a plan to accept it for the 6.17 version, or would it be
accepted only for 6.18?

If it is expected that it takes a longer time, or even 6.17
would be released with non-functional Zynq FPGA manager support
then we need to add patching of the broken kernel into our system
because we do not want to lose months of kernel state monitoring
and testing, because more problems could slip in during that time.
We have already caught some problems with the RT variant in the past
thanks to our effort and we have reported quickly even actual
case still during 6.17 merge window. The current breakage
in the mainline test fails our whole series, and we are losing even
RT assessment without changes prepared for the long-term mainline
fails, which is exceptional in our three-year testing effort.

Best wishes,

Pavel


On Wednesday 06 of August 2025 09:06:05 Xu Yilun wrote:
> dma_map_sgtable() returns only 0 or the error code. Read sgt->nents to
> get the number of mapped segments.
>
> CC: stable@vger.kernel.org
> Fixes: 37e00703228a ("zynq_fpga: use sgtable-based scatterlist wrappers")
> Reported-by: Pavel Pisa <pisa@fel.cvut.cz>
> Closes:
> https://lore.kernel.org/linux-fpga/202508041548.22955.pisa@fel.cvut.cz/
> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
> Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
> Tested-by: Pavel Pisa <pisa@fel.cvut.cz>
> ---
>  drivers/fpga/zynq-fpga.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> index 0be0d569589d..b7629a0e4813 100644
> --- a/drivers/fpga/zynq-fpga.c
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -405,12 +405,12 @@ static int zynq_fpga_ops_write(struct fpga_manager
> *mgr, struct sg_table *sgt) }
>  	}
>
> -	priv->dma_nelms =
> -	    dma_map_sgtable(mgr->dev.parent, sgt, DMA_TO_DEVICE, 0);
> -	if (priv->dma_nelms == 0) {
> +	err = dma_map_sgtable(mgr->dev.parent, sgt, DMA_TO_DEVICE, 0);
> +	if (err) {
>  		dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n");
> -		return -ENOMEM;
> +		return err;
>  	}
> +	priv->dma_nelms = sgt->nents;
>
>  	/* enable clock */
>  	err = clk_enable(priv->clk);


-- 
                Pavel Pisa
    phone:      +420 603531357
    e-mail:     pisa@cmp.felk.cvut.cz
    Department of Control Engineering FEE CVUT
    Karlovo namesti 13, 121 35, Prague 2
    university: http://control.fel.cvut.cz/
    personal:   http://cmp.felk.cvut.cz/~pisa
    social:     https://social.kernel.org/ppisa
    projects:   https://www.openhub.net/accounts/ppisa
    CAN related:http://canbus.pages.fel.cvut.cz/
    RISC-V education: https://comparch.edu.cvut.cz/
    Open Technologies Research Education and Exchange Services
    https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home

Re: [PATCH 1/1] fpga: zynq_fpga: Fix the wrong usage of dma_map_sgtable()

[Greg KH]

On Tue, Aug 19, 2025 at 12:39:02AM +0200, Pavel Pisa wrote:
> Hello Greg and others,
> 
> please, is there some progress/decision about the fix for mainline?
> 
> Our daily test of mainline Linux kernel build and test of CAN
> communication latency on Zynq system with loaded CTU CAN FD
> IP core ends with unresponsive kernel. The last successful
> mainline build is from July 29
>  
>   run-250729-042256-hist+6.16.0-g283564a43383+oaat-kern.json
>   https://canbus.pages.fel.cvut.cz/can-latester/
> 
> I have analyzed the cause and reported (August 4) that mainline
> Zynq runtime FPGA bitstream loading was broken by patch
> 
>   37e00703228a ("zynq_fpga: use sgtable-based scatterlist wrappers")
> 
> Xu Yilun and others from the FPGA community reacted promptly
> with the fix on August 6. The fix has propagated into linux-next.
> Is there a plan to accept it for the 6.17 version, or would it be
> accepted only for 6.18?

It's in my "to apply" queue to get to for 6.17-final.

Please give us a chance to catch up, August is usually a time for
vacations :)

thanks,

greg k-h

Re: [PATCH 1/1] fpga: zynq_fpga: Fix the wrong usage of dma_map_sgtable()

[Pavel Pisa]

Hello Greg,

On Tuesday 19 of August 2025 07:25:57 Greg KH wrote:
> On Tue, Aug 19, 2025 at 12:39:02AM +0200, Pavel Pisa wrote:
> > I have analyzed the cause and reported (August 4) that mainline
> > Zynq runtime FPGA bitstream loading was broken by patch
> >
> >   37e00703228a ("zynq_fpga: use sgtable-based scatterlist wrappers")
> >
....

> It's in my "to apply" queue to get to for 6.17-final.
>
> Please give us a chance to catch up, August is usually a time for
> vacations :)

Thanks lot for the pushing the patch

  fpga: zynq_fpga: Fix the wrong usage of dma_map_sgtable()

into the Linux kernel mainline. I report success - the mainline
is not stuck after FPGA reconfiguration and CTU CAN FD tests
progress to successful finish for mainline kernel.

The exact tested version

   6.17.0-rc2-g8d245acc1e88+flood-kern-fd-thrd-load

In the fact, I have noticed that your pull request has been applied
by Linus at 8/23/25 5:27 PM and I have invoked the CAN latester
build queue by had to provide feedback as soon as possible.
It is triggered after CEST midnight normally with results
available next day at the morning.

As for the stable queues (from your e-mail notices), please,
ensure that both patches are applied or none.

As for our whole test round results together with the RT kernel, we do not
reach functional state yet because the problematic patch has propagated
to RT kernel and kernel fails hard way after boot and reconfigure
script invocation now.

When FPGA configuration is skipped and then run manually on RT,
I get

[  233.319355] dtbocfg: loading out-of-tree module taints kernel.
[  233.319999] dtbocfg: 0.1.0
[  233.320105] dtbocfg: OK
[  233.435010] fpga_manager fpga0: writing system.bit.bin to Xilinx Zynq FPGA Manager
[  233.510549] fpga_manager fpga0: Unable to DMA map (TO_DEVICE)
[  233.510567] fpga_manager fpga0: Error while writing image data to FPGA
[  233.510951] fpga_region region0: failed to load FPGA image
[  233.510967] OF: overlay: overlay changeset pre-apply notifier error -12, target: /fpga-full

We build the branch "for-kbuild-bot/current-stable" from
git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git
The actual version

  6.17.0-rc1-rt1-gf54787e29f62

We can switch to another branch or reintroduce some patching
in the automatic process which we have there in the past.

By the way, I have done the first OpenOCD accesses/registers
dumps of our CTU CAN FD IP core on ESP32-C5 to see how it has
propagated to real silocon. We are buying some CAN FD
transceivers in DIL package for initial wire nest
soldering on a bread board now. 

Best wishes,

                Pavel

                Pavel Pisa
    phone:      +420 603531357
    e-mail:     pisa@cmp.felk.cvut.cz
    Department of Control Engineering FEE CVUT
    Karlovo namesti 13, 121 35, Prague 2
    university: http://control.fel.cvut.cz/
    personal:   http://cmp.felk.cvut.cz/~pisa
    social:     https://social.kernel.org/ppisa
    projects:   https://www.openhub.net/accounts/ppisa
    CAN related:http://canbus.pages.fel.cvut.cz/
    RISC-V education: https://comparch.edu.cvut.cz/
    Open Technologies Research Education and Exchange Services
    https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home