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([49.37.171.24]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c826767e677sm13120456a12.4.2026.05.12.11.02.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 May 2026 11:02:34 -0700 (PDT) From: Manish Baing To: mdf@kernel.org, yilun.xu@intel.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: matthew.gerlach@linux.intel.com, trix@redhat.com, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, manishbaing2789@gmail.com Subject: [PATCH] dt-bindings: fpga: altr,a10-pr-ip: convert to DT schema Date: Tue, 12 May 2026 18:02:25 +0000 Message-ID: <20260512180225.65902-1-manishbaing2789@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Convert the Altera Arria 10 Partial Reconfiguration IP bindings from text format to YAML schema. Signed-off-by: Manish Baing --- .../devicetree/bindings/fpga/altera-pr-ip.txt | 12 ------- .../bindings/fpga/altr,a10-pr-ip.yaml | 34 +++++++++++++++++++ 2 files changed, 34 insertions(+), 12 deletions(-) delete mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt create mode 100644 Documentation/devicetree/bindings/fpga/altr,a10-pr-ip.yaml diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt deleted file mode 100644 index 52a294cf2730..000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt +++ /dev/null @@ -1,12 +0,0 @@ -Altera Arria10 Partial Reconfiguration IP - -Required properties: -- compatible : should contain "altr,a10-pr-ip" -- reg : base address and size for memory mapped io. - -Example: - - fpga_mgr: fpga-mgr@ff20c000 { - compatible = "altr,a10-pr-ip"; - reg = <0xff20c000 0x10>; - }; diff --git a/Documentation/devicetree/bindings/fpga/altr,a10-pr-ip.yaml b/Documentation/devicetree/bindings/fpga/altr,a10-pr-ip.yaml new file mode 100644 index 000000000000..1f4df40308bd --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altr,a10-pr-ip.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/altr,a10-pr-ip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Arria10 Partial Reconfiguration IP + +maintainers: + - Matthew Gerlach + +description: + The Altera Arria 10 Partial Reconfiguration IP core allows the host + processor to perform partial reconfiguration of the FPGA fabric. + +properties: + compatible: + const: altr,a10-pr-ip + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + fpga-mgr@ff20c000 { + compatible = "altr,a10-pr-ip"; + reg = <0xff20c000 0x10>; + }; -- 2.43.0