From: Tom Rix <trix@redhat.com>
To: Richard Gong <richard.gong@linux.intel.com>,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: dinguyen@kernel.org, sridhar.rajagopal@intel.com,
Richard Gong <richard.gong@intel.com>
Subject: Re: [PATCHv1 1/4] fpga: fpga-mgr: add FPGA_MGR_BITSTREM_AUTHENTICATION flag
Date: Sat, 14 Nov 2020 07:53:54 -0800 [thread overview]
Message-ID: <28d2ace8-315a-3eaf-75da-88a4e90ea045@redhat.com> (raw)
In-Reply-To: <4dd9a747-05f3-1cca-22a6-35681677223d@linux.intel.com>
On 11/14/20 6:30 AM, Richard Gong wrote:
>
>> A whitespace issue, the new BIT(5) should align with the others, so add two spaces to the others.
>>
>
> There is only one space, also I ran checkpatch with strict option and didn't see any whitespace issue.
>
> In the original patch, BIT(0) to BIT(4) align themselves. I am not sure why we see differently in email.
>
> #define FPGA_MGR_PARTIAL_RECONFIG BIT(0)
> #define FPGA_MGR_EXTERNAL_CONFIG BIT(1)
> #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2)
> #define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3)
> #define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4)
> +#define FPGA_MGR_BITSTREM_AUTHENTICATION BIT(5)
>
> To align BIT(5) with others, I have to use additional tab to BIT(0) to BIT(4). But I don't think I should make such change on them, agree?
The existing table of #defines has aligned values for BIT(0) to BIT(4)
Your addition of BIT(5) value has an inconsistent alignment with the others BIT(0) to BIT(4)
The alignment of all the values should be consistent.
Tom
>
> Regards,
> Richard
>
>> Tom
>>
>>> /**
>>> * struct fpga_image_info - information specific to a FPGA image
>>
>
next prev parent reply other threads:[~2020-11-14 15:54 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-12 18:06 [PATCHv1 0/4] Extend FPGA manager and region drivers for richard.gong
2020-11-12 18:06 ` [PATCHv1 1/4] fpga: fpga-mgr: add FPGA_MGR_BITSTREM_AUTHENTICATION flag richard.gong
2020-11-13 20:24 ` Tom Rix
2020-11-14 14:30 ` Richard Gong
2020-11-14 15:53 ` Tom Rix [this message]
2020-11-16 13:39 ` Richard Gong
2020-11-12 18:06 ` [PATCHv1 2/4] fpga: of-fpga-region: add authenticate-fpga-config property richard.gong
2020-11-13 20:25 ` Tom Rix
2020-11-12 18:06 ` [PATCHv1 3/4] dt-bindings: fpga: " richard.gong
2020-11-13 20:28 ` Tom Rix
2020-11-14 14:52 ` Richard Gong
2020-11-14 15:59 ` Tom Rix
2020-11-16 13:50 ` Richard Gong
2020-11-16 15:11 ` Tom Rix
2020-11-15 19:21 ` Moritz Fischer
2020-11-16 2:47 ` Xu Yilun
2020-11-16 14:14 ` Richard Gong
2020-11-17 2:24 ` Xu Yilun
2020-11-17 15:39 ` Richard Gong
2020-11-18 5:47 ` Xu Yilun
2020-11-18 13:38 ` Richard Gong
2020-11-19 11:14 ` Xu Yilun
2020-11-16 13:59 ` Richard Gong
2020-11-12 18:06 ` [PATCHv1 4/4] fpga: stratix10-soc: entend driver for bitstream authentication richard.gong
2020-11-13 20:31 ` Tom Rix
2020-11-14 14:55 ` Richard Gong
2020-11-15 19:19 ` Moritz Fischer
2020-11-16 14:39 ` Richard Gong
2020-11-16 2:41 ` [PATCHv1 0/4] Extend FPGA manager and region drivers for Xu Yilun
2020-11-16 14:02 ` Richard Gong
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