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From: David Laight <David.Laight@ACULAB.COM>
Subject: RE: [PATCH v3 08/21] fpga: add Intel FPGA DFL PCIe device
Date: Wed, 6 Dec 2017 09:34:14 +0000
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To: 'Wu Hao' <hao.wu@intel.com>, Alan Tull <atull@kernel.org>
Cc: "mdf@kernel.org" <mdf@kernel.org>, "linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-api@vger.kernel.org" <linux-api@vger.kernel.org>, "luwei.kang@intel.com" <luwei.kang@intel.com>, "yi.z.zhang@intel.com" <yi.z.zhang@intel.com>, Tim Whisonant <tim.whisonant@intel.com>, Enno Luebbers <enno.luebbers@intel.com>, Shiva Rao <shiva.rao@intel.com>, Christopher Rauer <christopher.rauer@intel.com>, Xiao
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From: Wu Hao
> Sent: 05 December 2017 03:34
...
> > I don't see anything Intel specific here.  This could all be named dfl-=
*
>=20
> The maybe some device specific things, e.g Intel FPGA devices supported b=
y this
> driver always have FME DFL at the beginning on the BAR0 for PF device.

Since when has that been a method for specifying what the card does?
You need to allocate a PCI-id for your DFL accelerator.

	David