From: Federico Vaga <federico.vaga@cern.ch>
To: federico.vaga@cern.chFederico Vaga <federico.vaga@cern.ch>
Cc: linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-x86_64@vger.kernel.org
Subject: Re: Device Description for FPGA Components on x86 system
Date: Wed, 10 Apr 2019 12:01:33 +0200 [thread overview]
Message-ID: <6563205.xRkLC0driV@pcbe13614> (raw)
In-Reply-To: <1629227.alSmCsHHUc@pcbe13614>
Hello,
sorry to push for an answer but I do not want to take the risk of designing
something useless. I do not know how should I interpret a no-answer.
If the solution really does not exist today, then I would like to collect
opinions/arguments/requirements on the topic so that I can write something
useful not only for CERN but for the entire community.
Thank you
On Wednesday, March 27, 2019 6:17:18 PM CEST Federico Vaga wrote:
> Hello,
>
> I'm looking for guidance
>
> What I have:
> * Intel x86_64 computer
> * PCIe card with FPGA on it
>
> What I want to achieve:
> * load an FPGA bitstream on the card
> * load a device-tree like description for the FPGA devices contained in the
> bitstream
>
> This is achievable on ARM with DeviceTree, overlay-dt, fpga-mgr; but I'm
> puzzled about the x86_64 use-case. I'm not able to find recent and clear
> information.
>
> Does anyone know if this is doable? Perhaps with ACPI SSDTs overlay? Or with
> the DT?
>
> thanks
next prev parent reply other threads:[~2019-04-10 10:02 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-27 17:17 Device Description for FPGA Components on x86 system Federico Vaga
2019-04-10 10:01 ` Federico Vaga [this message]
2019-04-10 10:30 ` Eric Schwarz
2019-04-10 12:50 ` Federico Vaga
2019-04-10 14:21 ` Alan Tull
2019-04-10 15:13 ` Federico Vaga
2019-04-15 11:55 ` Enrico Weigelt, metux IT consult
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