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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Conor Dooley <conor.dooley@microchip.com>,
	Ian Dannapel <iansdannapel@gmail.com>
Cc: "Conor Dooley" <conor@kernel.org>,
	linux-fpga@vger.kernel.org, "Moritz Fischer" <mdf@kernel.org>,
	"Wu Hao" <hao.wu@intel.com>, "Xu Yilun" <yilun.xu@intel.com>,
	"Tom Rix" <trix@redhat.com>, "Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
	"Rafał Miłecki" <rafal@milecki.pl>,
	"Aradhya Bhatia" <a-bhatia1@ti.com>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [v4 2/3] dt-bindings: fpga: Add Efinix SPI programming bindings
Date: Mon, 3 Mar 2025 11:34:35 +0100	[thread overview]
Message-ID: <766cc092-896f-4dc7-b1e4-9996b4b8f35d@kernel.org> (raw)
In-Reply-To: <20250303-imply-ferocity-bbb6d866b149@wendy>

On 03/03/2025 11:31, Conor Dooley wrote:
> On Mon, Mar 03, 2025 at 11:10:53AM +0100, Ian Dannapel wrote:
>> Hi Conor, thanks for the quick response.
>>
>> On Fri, Feb 28, 2025 at 7:28 PM Conor Dooley <conor@kernel.org> wrote:
>>>> +description: |
>>>> +  Efinix FPGAs (Trion, Topaz, and Titanium families) support loading bitstreams
>>>> +  through "SPI Passive Mode".
>>>> +  Note 1: Only bus width 1x is supported.
>>>> +  Note 2: Additional pins hogs for bus width configuration must be set
>>>> +  elsewhere, if necessary.
>>>> +  Note 3: Topaz and Titanium support is based on documentation but remains
>>>> +  untested.
>>>
>>> Points 1 and 3 here seem to be driver limitations, and shouldn't really
>>> be present in a document describing the hardware?
>>>
>> Yes, they are driver limitations and probably do not belong here.
>>
>>>> +properties:
>>>> +  compatible:
>>>> +    enum:
>>>> +      - efinix,trion-spi
>>>> +      - efinix,titanium-spi
>>>> +      - efinix,topaz-spi
>>>
>>>> +      - efinix,fpga-spi
>>>
>>> What hardware does this device represent? Other ones are obvious matches
>>> to the families you mention, but what is this one?
> 
>> The proposed compatible is a generic fallback for any Efinix FPGA Series.
> 
> If it is a fallback, your binding should look like:
> compatible:
>   items:
>     - enum:
>         - efinix,trion-spi
>         - efinix,titanium-spi
>         - efinix,topaz-spi
>     - const: efinix,fpga-spi
> 
> |+static const struct of_device_id efinix_spi_of_match[] = {
> |+       { .compatible = "efinix,trion-spi", },
> |+       { .compatible = "efinix,titanium-spi", },
> |+       { .compatible = "efinix,topaz-spi", },
> 
> And these three compatibles can/should be removed from the driver, since
> the fallback is required.
> 
> |+       { .compatible = "efinix,fpga-spi", },
> |+       {}

Yes, except that one of the devices should be the fallback, not generic
"fpga".


Best regards,
Krzysztof

  reply	other threads:[~2025-03-03 10:34 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-28  9:47 [v4 0/3] Add Efinix FPGA SPI programming support iansdannapel
2025-02-28  9:47 ` [v4 1/3] dt-bindings: vendor-prefix: Add prefix for Efinix, Inc iansdannapel
2025-02-28 18:29   ` Conor Dooley
2025-03-01 13:10   ` Krzysztof Kozlowski
2025-03-04 11:24     ` Alexander Dahl
2025-02-28  9:47 ` [v4 2/3] dt-bindings: fpga: Add Efinix SPI programming bindings iansdannapel
2025-02-28 18:28   ` Conor Dooley
2025-03-03 10:10     ` Ian Dannapel
2025-03-03 10:29       ` Ian Dannapel
2025-03-03 10:33         ` Krzysztof Kozlowski
2025-03-03 10:31       ` Conor Dooley
2025-03-03 10:34         ` Krzysztof Kozlowski [this message]
2025-03-01 13:13   ` Krzysztof Kozlowski
2025-02-28  9:47 ` [v4 3/3] fpga-mgr: Add Efinix SPI programming driver iansdannapel
2025-03-03 11:57   ` Manne, Nava kishore
2025-03-03 12:16     ` Ian Dannapel
2025-03-16 15:03   ` Xu Yilun

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