messages from 2026-09-28 01:16:00 to 2026-10-29 03:53:27 UTC [more...]
[PATCH] fpga: dfl: afu: prevent read-only region mappings from becoming writable
2026-10-29 3:53 UTC
[PATCH v2] fpga: altera-cvp: Add Agilex5 CVP credit register support
2026-10-28 10:40 UTC
[PATCH v2] fpga: dfl: afu: prevent read-only port mappings from becoming writable
2026-10-23 11:44 UTC
[PATCH 0/3] fpga: stratix10-soc: harden wait, ERROR order, and timeout
2026-10-20 7:49 UTC (9+ messages)
` [PATCH 2/3] fpga: stratix10-soc: prefer ERROR over BUFFER_DONE
` [PATCH 3/3] fpga: stratix10-soc: floor config_complete_timeout_us
` [PATCH v3 0/3] fpga: stratix10-soc: harden wait, ERROR order, and timeout
` [PATCH v3 1/3] fpga: stratix10-soc: always wait for svc buffer completion
` [PATCH v3 2/3] fpga: stratix10-soc: use config_complete_timeout_us as a deadline
` [PATCH v3 3/3] fpga: stratix10-soc: add SVC wait helper and prefer ERROR
[GIT PULL] FPGA Manager changes for 7.4-rc1
2026-10-09 14:25 UTC (2+ messages)
[PATCH v3] fpga: altera-freeze-bridge: clear all illegal request bits
2026-10-06 2:34 UTC
[PATCH v2] fpga: bridge: incorrect set to clear freeze_illegal_request register
2026-10-02 6:53 UTC (3+ messages)
[PATCH v3 0/2] fpga: altera-cvp: Retry teardown on CFG_RDY timeout
2026-09-29 10:27 UTC (2+ messages)
[PATCH] fpga: region: depopulate child devices on remove
2026-09-28 11:08 UTC (2+ messages)
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