FPGA-HPS DDR contention on Agilex5 SoC while running Linux

[Patryk <pbiel7@gmail.com>]

Hi

I’m working on a device based on an Agilex5 SoC with HPS, which is new
hardware for me.

I've been considering the following scenario: the FPGA and HPS will
share DDR memory, and Linux is running on the HPS at the same time.
The FPGA will be streaming a high volume of data that needs to be
consumed by a userspace program on the CPU.

I’m concerned that if the FPGA saturates the memory interconnect, the
kernel might struggle to perform memory allocations or other
transactions for other threads.

Has anyone encountered this kind of bus contention on Agilex/SoC
platforms? What strategies do you use to prevent FPGA traffic from
starving HPS memory accesses while Linux is running? Also, is there
any recommendation / strategy for an FPGA and a userspace program on
Linux to exchange data efficiently and safely in this kind of setup?

I don't expect in-depth answers, and will be grateful for anything
that will channel me in the right direction.

Best regards
Patryk