From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9117FC7EE24 for ; Mon, 5 Jun 2023 11:13:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232058AbjFELLR (ORCPT ); Mon, 5 Jun 2023 07:11:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231513AbjFELLM (ORCPT ); Mon, 5 Jun 2023 07:11:12 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79465F2 for ; Mon, 5 Jun 2023 04:11:02 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-977d55ac17bso190827966b.3 for ; Mon, 05 Jun 2023 04:11:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20221208.gappssmtp.com; s=20221208; t=1685963461; x=1688555461; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=Xz/gIyGLAa00Ho9qsceUjDdF3ckRJGistqectqhHPQ0=; b=t0XcxfZTmxtrU4/ziMpt5ZPpzi0AXzfijXgg8AHq2rNydhE+oiaDLYH3u0hrpVudeD uXR/hg1KMjTOecO8X4pXeWEBLH868TCm379WtYxsMDs4AVnWZwoS/qKQ/cAKHfiwPTwt eEm0DJrQgNEMIFE4qBFffGyTe/DUOjWmcuBbLMBVnM1qjXE+wjvrVRAAMHL/v9S48L4/ LKH6GTMATUc3X8h8jAHeFqlNi4H/7XDPvxOxLXTIZFJhA7jDKRhyMREGboUMRDZ129yY a+J0TwFcFy2BdtH1TiHjVGkLZyqe2U5O077dsOkiCK4MLTgMChuC42A/WYU+blk08gt7 kg/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685963461; x=1688555461; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xz/gIyGLAa00Ho9qsceUjDdF3ckRJGistqectqhHPQ0=; b=bdcvBzDGXEECOFytdaZi6THtumJR2mZLUIDq2jklIC01xNrmvp8buQbUsj+MLbTpsN OzVe1PjraFfyOYbD5saLtK2nbBSeUscQDLgCpdktGQIUaQ2v89T3LsAQb20p0jK76m7g LfM0J5OD5zr6WODP/Fq+Rp47Zgtpy3YHpWT8FKHzXw1rqBUCPV9bazEHWjvT+KTn965U 5zXn1mwvjtkaeFoKX6Mia5vukKQhJC+v/qKLLpptJU1tktWVpYNZQvWhBsy0vAm5VEyZ HgrvZYV6aFB3F3vnrAgXGgwr8YdNhqC11LUaaPVsvK9Er+fFnnDR6RhKXbsYK2qyc1oH W+cg== X-Gm-Message-State: AC+VfDwH8M8oc1iy70f16qrd799+xUM444B5VZf1veUS5ooORMiHJAud RBk5jEu/TQCThgnTJwEoo0XL2vaFEb6poI2osCM2aw== X-Google-Smtp-Source: ACHHUZ7Myh4P550fmY4KgTrMjcVnpWx0cBq0yOe6l1+zqgJeRkdJtHt3XVmv5M7WqhGVjDr/M7wAxI8E9EIAXW/6zNA= X-Received: by 2002:a17:907:26c4:b0:974:c32c:b484 with SMTP id bp4-20020a17090726c400b00974c32cb484mr5173211ejc.72.1685963460711; Mon, 05 Jun 2023 04:11:00 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Michal Simek Date: Mon, 5 Jun 2023 13:10:48 +0200 Message-ID: Subject: Re: [PATCH] dt-bindings: xilinx: Switch xilinx.com emails to amd.com To: Michal Simek Cc: piyush.mehta@amd.com, nava.kishore.manne@amd.com, sai.krishna.potthuri@amd.com, shubhrajyoti.datta@amd.com, vishal.sagar@amd.com, kalyani.akula@amd.com, bharat.kumar.gogada@amd.com, linux-kernel@vger.kernel.org, git@xilinx.com, Alessandro Zummo , Alexandre Belloni , Andrew Lunn , Bartosz Golaszewski , Bjorn Helgaas , Conor Dooley , Damien Le Moal , Daniel Lezcano , "David S. Miller" , Greg Kroah-Hartman , Guenter Roeck , Herbert Xu , Jassi Brar , Jolly Shah , Krzysztof Kozlowski , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Laurent Pinchart , Linus Walleij , Lorenzo Pieralisi , Manish Narani , Mark Brown , Mauro Carvalho Chehab , Michael Turquette , Moritz Fischer , Rajan Vaja , Rob Herring , Sebastian Reichel , Srinivas Neeli , Stephen Boyd , Thomas Gleixner , Tom Rix , Wim Van Sebroeck , Wu Hao , Xu Yilun , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org, linux-fpga@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org, linux-ide@vger.kernel.org, linux-media@vger.kernel.org, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, linux-rtc@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-watchdog@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org =C3=BAt 16. 5. 2023 v 15:51 odes=C3=ADlatel Michal Simek napsal: > > @xilinx.com is still working but better to switch to new amd.com after > AMD/Xilinx acquisition. > > Signed-off-by: Michal Simek > --- > > Documentation/devicetree/bindings/arm/xilinx.yaml | 2 +- > Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 2 +- > .../devicetree/bindings/clock/xlnx,clocking-wizard.yaml | 2 +- > Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 +- > Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml | 4 ++-- > .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml | 2 +- > .../devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml | 2 +- > Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml | 2 +- > .../devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml | 2 +- > Documentation/devicetree/bindings/gpio/gpio-zynq.yaml | 2 +- > Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml | 2 +- > .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 2 +- > Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml | 2 +- > .../devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml | 2 +- > .../devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml | 2 +- > .../bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml | 2 +- > .../bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml | 2 +- > Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 2 +- > .../devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml | 2 +- > .../devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml | 2 +- > .../devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml | 2 +- > Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml | 2 +- > Documentation/devicetree/bindings/serial/cdns,uart.yaml | 2 +- > Documentation/devicetree/bindings/spi/spi-cadence.yaml | 2 +- > Documentation/devicetree/bindings/spi/spi-xilinx.yaml | 2 +- > Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml | 2 +- > Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml | 2 +- > Documentation/devicetree/bindings/timer/cdns,ttc.yaml | 2 +- > .../devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml | 4 ++-- > 29 files changed, 31 insertions(+), 31 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/xilinx.yaml b/Document= ation/devicetree/bindings/arm/xilinx.yaml > index b3071d10ea65..f57ed0347894 100644 > --- a/Documentation/devicetree/bindings/arm/xilinx.yaml > +++ b/Documentation/devicetree/bindings/arm/xilinx.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx Zynq Platforms > > maintainers: > - - Michal Simek > + - Michal Simek > > description: | > Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC > diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/= Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > index 71364c6081ff..b29ce598f9aa 100644 > --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Ceva AHCI SATA Controller > > maintainers: > - - Piyush Mehta > + - Piyush Mehta > > description: | > The Ceva SATA controller mostly conforms to the AHCI interface with so= me > diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard= .yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > index c1f04830a832..02bd556bd91a 100644 > --- a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx clocking wizard > > maintainers: > - - Shubhrajyoti Datta > + - Shubhrajyoti Datta > > description: > The clocking wizard is a soft ip clocking block of Xilinx versal. It > diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml= b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml > index 229af98b1d30..93ae349cf9e9 100644 > --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml > +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx Versal clock controller > > maintainers: > - - Michal Simek > + - Michal Simek > - Jolly Shah > - Rajan Vaja > > diff --git a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yam= l b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml > index 9e8fbd02b150..8aead97a585b 100644 > --- a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml > +++ b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml > @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx ZynqMP AES-GCM Hardware Accelerator > > maintainers: > - - Kalyani Akula > - - Michal Simek > + - Kalyani Akula > + - Michal Simek > > description: | > The ZynqMP AES-GCM hardened cryptographic accelerator is used to > diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqm= p-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zy= nqmp-firmware.yaml > index f14f7b454f07..910bebe6cfa8 100644 > --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmw= are.yaml > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmw= are.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx firmware driver > > maintainers: > - - Nava kishore Manne > + - Nava kishore Manne > > description: The zynqmp-firmware node describes the interface to platfor= m > firmware. ZynqMP has an interface to communicate with secure firmware. > diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.= yaml b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml > index f47b6140a742..04dcadc2c20e 100644 > --- a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml > +++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx Zynq FPGA Manager > > maintainers: > - - Michal Simek > + - Michal Simek > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml= b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml > index ac6a207278d5..26f18834caa3 100644 > --- a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml > +++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx Versal FPGA driver. > > maintainers: > - - Nava kishore Manne > + - Nava kishore Manne > > description: | > Device Tree Versal FPGA bindings for the Versal SoC, controlled > diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga= .yaml b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml > index 00a8d92ff736..1390ae103b0b 100644 > --- a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx Zynq Ultrascale MPSoC FPGA Manager > > maintainers: > - - Nava kishore Manne > + - Nava kishore Manne > > description: | > Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager. > diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Docu= mentation/devicetree/bindings/gpio/gpio-zynq.yaml > index 572e1718f501..5e2496379a3c 100644 > --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml > +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx Zynq GPIO controller > > maintainers: > - - Michal Simek > + - Michal Simek > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml= b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml > index f333ee2288e7..c1060e5fcef3 100644 > --- a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml > +++ b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx AXI GPIO controller > > maintainers: > - - Neeli Srinivas > + - Neeli Srinivas > > description: > The AXI GPIO design provides a general purpose input/output interface > diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-mode= pin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.= yaml > index 31c0fc345903..18e61aff2185 100644 > --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yam= l > +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yam= l > @@ -12,7 +12,7 @@ description: > PS_MODE). Every pin can be configured as input/output. > > maintainers: > - - Piyush Mehta > + - Piyush Mehta > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml b/= Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml > index cb24d7b3221c..ff57c5416ebc 100644 > --- a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml > +++ b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Cadence I2C controller > > maintainers: > - - Michal Simek > + - Michal Simek > > allOf: > - $ref: /schemas/i2c/i2c-controller.yaml# > diff --git a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-ma= ilbox.yaml b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mail= box.yaml > index 374ffe64016f..aeaddbf574b0 100644 > --- a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.y= aml > +++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.y= aml > @@ -33,7 +33,7 @@ description: | > +------------------------------------------+ > > maintainers: > - - Shubhrajyoti Datta > + - Shubhrajyoti Datta > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss= .yaml b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml > index 7d77823dbb7a..43daf837fc9f 100644 > --- a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx MIPI CSI-2 Receiver Subsystem > > maintainers: > - - Vishal Sagar > + - Vishal Sagar > > description: | > The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2 > diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw= -umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/sn= ps,dw-umctl2-ddrc.yaml > index e68c4306025a..6b62d5d83476 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2= -ddrc.yaml > +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2= -ddrc.yaml > @@ -9,7 +9,7 @@ title: Synopsys DesignWare Universal Multi-Protocol Memor= y Controller > maintainers: > - Krzysztof Kozlowski > - Manish Narani > - - Michal Simek > + - Michal Simek > > description: | > Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable o= f > diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zy= nq-ddrc-a05.yaml b/Documentation/devicetree/bindings/memory-controllers/xln= x,zynq-ddrc-a05.yaml > index 8f72e2f8588a..7864a1c994eb 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc= -a05.yaml > +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc= -a05.yaml > @@ -9,7 +9,7 @@ title: Zynq A05 DDR Memory Controller > maintainers: > - Krzysztof Kozlowski > - Manish Narani > - - Michal Simek > + - Michal Simek > > description: > The Zynq DDR ECC controller has an optional ECC support in half-bus wi= dth > diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml= b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > index 24ddc2855b94..4734be456bde 100644 > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: CPM Host Controller device tree for Xilinx Versal SoCs > > maintainers: > - - Bharat Kumar Gogada > + - Bharat Kumar Gogada > > allOf: > - $ref: /schemas/pci/pci-bus.yaml# > diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.= yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml > index 598a042850b8..b85f9e36ce4b 100644 > --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml > +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx Zynq Pinctrl > > maintainers: > - - Sai Krishna Potthuri > + - Sai Krishna Potthuri > > description: | > Please refer to pinctrl-bindings.txt in this directory for details of = the > diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml > index 2722dc7bb03d..cdebfa991e06 100644 > --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml > +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx ZynqMP Pinctrl > > maintainers: > - - Sai Krishna Potthuri > + - Sai Krishna Potthuri > - Rajan Vaja > > description: | > diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-po= wer.yaml b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.= yaml > index 11f1f98c1cdc..45792e216981 100644 > --- a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yam= l > +++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yam= l > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx Zynq MPSoC Power Management > > maintainers: > - - Michal Simek > + - Michal Simek > > description: | > The zynqmp-power node describes the power management configurations. > diff --git a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml b= /Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml > index 7ed0230f6c67..d1f5eb996dba 100644 > --- a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml > +++ b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml > @@ -11,7 +11,7 @@ description: > The RTC controller has separate IRQ lines for seconds and alarm. > > maintainers: > - - Michal Simek > + - Michal Simek > > allOf: > - $ref: rtc.yaml# > diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Do= cumentation/devicetree/bindings/serial/cdns,uart.yaml > index a8b323d7bf94..e35ad1109efc 100644 > --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml > +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Cadence UART Controller > > maintainers: > - - Michal Simek > + - Michal Simek > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Doc= umentation/devicetree/bindings/spi/spi-cadence.yaml > index b0f83b5c2cdd..b7552739b554 100644 > --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml > +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Cadence SPI controller > > maintainers: > - - Michal Simek > + - Michal Simek > > allOf: > - $ref: spi-controller.yaml# > diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml b/Docu= mentation/devicetree/bindings/spi/spi-xilinx.yaml > index 6bd83836eded..4beb3af0416d 100644 > --- a/Documentation/devicetree/bindings/spi/spi-xilinx.yaml > +++ b/Documentation/devicetree/bindings/spi/spi-xilinx.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx SPI controller > > maintainers: > - - Michal Simek > + - Michal Simek > > allOf: > - $ref: spi-controller.yaml# > diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b= /Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml > index 226d8b493b57..e5199b109dad 100644 > --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml > +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller > > maintainers: > - - Michal Simek > + - Michal Simek > > allOf: > - $ref: spi-controller.yaml# > diff --git a/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml b/= Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml > index 83e8fb4a548d..7ea8fb42ce2c 100644 > --- a/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml > +++ b/Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml > @@ -14,7 +14,7 @@ allOf: > - $ref: spi-controller.yaml# > > maintainers: > - - Michal Simek > + - Michal Simek > > # Everything else is described in the common file > properties: > diff --git a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml b/Docu= mentation/devicetree/bindings/timer/cdns,ttc.yaml > index bc5e6f226295..dbba780c9b02 100644 > --- a/Documentation/devicetree/bindings/timer/cdns,ttc.yaml > +++ b/Documentation/devicetree/bindings/timer/cdns,ttc.yaml > @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Cadence TTC - Triple Timer Counter > > maintainers: > - - Michal Simek > + - Michal Simek > > properties: > compatible: > diff --git a/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase= -wdt.yaml b/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wd= t.yaml > index 8444c56dd602..dc1ff39d05a0 100644 > --- a/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.ya= ml > +++ b/Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.ya= ml > @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > title: Xilinx AXI/PLB softcore and window Watchdog Timer > > maintainers: > - - Shubhrajyoti Datta > - - Srinivas Neeli > + - Shubhrajyoti Datta > + - Srinivas Neeli > > description: > The Timebase watchdog timer(WDT) is a free-running 32 bit counter. > -- > 2.36.1 > Applied. M --=20 Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs