From: Lee Jones <lee@kernel.org>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: linux-fpga@vger.kernel.org, Xu Yilun <yilun.xu@intel.com>,
Wu Hao <hao.wu@intel.com>, Tom Rix <trix@redhat.com>,
Moritz Fischer <mdf@kernel.org>,
Matthew Gerlach <matthew.gerlach@linux.intel.com>,
Russ Weight <russell.h.weight@intel.com>,
Tianfei zhang <tianfei.zhang@intel.com>,
Mark Brown <broonie@kernel.org>,
Marco Pagani <marpagan@redhat.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 04/10] mfd: intel-m10-bmc: Support multiple CSR register layouts
Date: Fri, 13 Jan 2023 14:44:22 +0000 [thread overview]
Message-ID: <Y8FuRtO0etJ0vl78@google.com> (raw)
In-Reply-To: <20221226175849.13056-5-ilpo.jarvinen@linux.intel.com>
On Mon, 26 Dec 2022, Ilpo Järvinen wrote:
> There are different addresses for the MAX10 CSR registers. Introducing
> a new data structure m10bmc_csr_map for the register definition of
> MAX10 CSR.
>
> Provide the csr_map for SPI.
>
> Co-developed-by: Tianfei zhang <tianfei.zhang@intel.com>
> Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
> Reviewed-by: Russ Weight <russell.h.weight@intel.com>
> Reviewed-by: Xu Yilun <yilun.xu@intel.com>
> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> ---
> drivers/fpga/intel-m10-bmc-sec-update.c | 73 +++++++++++++++++--------
> drivers/mfd/intel-m10-bmc-core.c | 10 ++--
> drivers/mfd/intel-m10-bmc-spi.c | 24 ++++++++
> include/linux/mfd/intel-m10-bmc.h | 39 +++++++++++--
> 4 files changed, 113 insertions(+), 33 deletions(-)
For my own reference (apply this as-is to your sign-off block):
Acked-for-MFD-by: Lee Jones <lee@kernel.org>
--
Lee Jones [李琼斯]
next prev parent reply other threads:[~2023-01-13 14:59 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-26 17:58 [PATCH v5 00/10] intel-m10-bmc: Split BMC to core and SPI parts & add PMCI+N6000 support Ilpo Järvinen
2022-12-26 17:58 ` [PATCH v5 01/10] mfd: intel-m10-bmc: Create m10bmc_platform_info for type specific info Ilpo Järvinen
2023-01-09 17:43 ` Lee Jones
2023-01-09 18:04 ` Ilpo Järvinen
2023-01-10 10:05 ` Lee Jones
2022-12-26 17:58 ` [PATCH v5 02/10] mfd: intel-m10-bmc: Rename the local variables Ilpo Järvinen
2023-01-09 18:07 ` Lee Jones
2023-01-09 18:17 ` Ilpo Järvinen
2023-01-10 10:13 ` Lee Jones
2022-12-26 17:58 ` [PATCH v5 03/10] mfd: intel-m10-bmc: Split into core and spi specific parts Ilpo Järvinen
2023-01-13 14:42 ` Lee Jones
2022-12-26 17:58 ` [PATCH v5 04/10] mfd: intel-m10-bmc: Support multiple CSR register layouts Ilpo Järvinen
2023-01-13 14:44 ` Lee Jones [this message]
2022-12-26 17:58 ` [PATCH v5 05/10] fpga: intel-m10-bmc: Rework flash read/write Ilpo Järvinen
2022-12-26 17:58 ` [PATCH v5 06/10] mfd: intel-m10-bmc: Downscope SPI defines & prefix with M10BMC_N3000 Ilpo Järvinen
2023-01-10 17:05 ` Lee Jones
2022-12-26 17:58 ` [PATCH v5 07/10] fpga: m10bmc-sec: Create helpers for rsu status/progress checks Ilpo Järvinen
2022-12-30 3:16 ` Xu Yilun
2022-12-26 17:58 ` [PATCH v5 08/10] fpga: m10bmc-sec: Differentiate rsu status from doorbell in csr map Ilpo Järvinen
2022-12-30 4:32 ` Xu Yilun
2022-12-30 10:23 ` Ilpo Järvinen
2023-01-03 9:34 ` Xu Yilun
2023-01-03 12:12 ` Ilpo Järvinen
2022-12-26 17:58 ` [PATCH v5 09/10] mfd: intel-m10-bmc: Add PMCI driver Ilpo Järvinen
2023-01-13 14:40 ` Lee Jones
2023-01-13 15:08 ` Ilpo Järvinen
2022-12-26 17:58 ` [PATCH v5 10/10] fpga: m10bmc-sec: Add support for N6000 Ilpo Järvinen
2022-12-30 6:10 ` Xu Yilun
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