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From: Xu Yilun <yilun.xu@intel.com>
To: Lee Jones <lee@kernel.org>
Cc: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Wu Hao" <hao.wu@intel.com>, "Tom Rix" <trix@redhat.com>,
	"Moritz Fischer" <mdf@kernel.org>,
	linux-fpga@vger.kernel.org, "Jean Delvare" <jdelvare@suse.com>,
	"Guenter Roeck" <linux@roeck-us.net>,
	"Russ Weight" <russell.h.weight@intel.com>,
	linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org
Subject: Re: [PATCH v3 4/4] mfd: intel-m10-bmc: Manage access to MAX 10 fw handshake registers
Date: Fri, 21 Apr 2023 17:52:19 +0800	[thread overview]
Message-ID: <ZEJc06oNSS2ICS1F@yilunxu-OptiPlex-7050> (raw)
In-Reply-To: <20230420111324.GA970483@google.com>

On 2023-04-20 at 12:13:24 +0100, Lee Jones wrote:
> On Fri, 21 Apr 2023, Xu Yilun wrote:
> 
> > On 2023-04-17 at 12:26:53 +0300, Ilpo Järvinen wrote:
> > > On some MAX 10 cards, the BMC firmware is not available to service
> > > handshake registers during secure update erase and write phases at
> > > normal speeds. This problem affects at least hwmon driver. When the MAX
> > > 10 hwmon driver tries to read the sensor values during a secure update,
> > > the reads are slowed down (e.g., reading all D5005 sensors takes ~24s
> > > which is magnitudes worse than the normal <0.02s).
> > > 
> > > Manage access to the handshake registers using a rw semaphore and a FW
> > > state variable to prevent accesses during those secure update phases
> > > and return -EBUSY instead.
> > > 
> > > If handshake_sys_reg_nranges == 0, don't update bwcfw_state as it is not
> > > used. This avoids the locking cost.
> > > 
> > > Co-developed-by: Russ Weight <russell.h.weight@intel.com>
> > > Signed-off-by: Russ Weight <russell.h.weight@intel.com>
> > > Co-developed-by: Xu Yilun <yilun.xu@intel.com>
> > > Signed-off-by: Xu Yilun <yilun.xu@intel.com>
> > > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> > 
> > Reviewed-by: Xu Yilun <yilun.xu@intel.com>
> > 
> > Hi Lee:
> > 
> > Could the fpga part also been applied to mfd tree when everyone is good?
> 
> Yes, with an Acked-by it can.

Acked-by: Xu Yilun <yilun.xu@intel.com>

> 
> -- 
> Lee Jones [李琼斯]

  reply	other threads:[~2023-04-21  1:53 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-17  9:26 [PATCH v3 0/4] intel-m10-bmc: Manage register access to control delay during sec update Ilpo Järvinen
2023-04-17  9:26 ` [PATCH v3 1/4] mfd: intel-m10-bmc: Move core symbols to own namespace Ilpo Järvinen
2023-04-20 16:08   ` Xu Yilun
2023-04-27 15:05   ` Lee Jones
2023-04-17  9:26 ` [PATCH v3 2/4] mfd: intel-m10-bmc: Create m10bmc_sys_update_bits() Ilpo Järvinen
2023-04-20 16:09   ` Xu Yilun
2023-04-21  9:52   ` Xu Yilun
2023-04-27 15:05   ` Lee Jones
2023-04-17  9:26 ` [PATCH v3 3/4] mfd: intel-m10-bmc: Move m10bmc_sys_read() away from header Ilpo Järvinen
2023-04-20 16:10   ` Xu Yilun
2023-04-27 15:06   ` Lee Jones
2023-04-17  9:26 ` [PATCH v3 4/4] mfd: intel-m10-bmc: Manage access to MAX 10 fw handshake registers Ilpo Järvinen
2023-04-20 16:07   ` Xu Yilun
2023-04-20 11:13     ` Lee Jones
2023-04-21  9:52       ` Xu Yilun [this message]
2023-04-27 15:07   ` Lee Jones
2023-05-10 11:51     ` Ilpo Järvinen
2023-05-15 10:06       ` Lee Jones

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