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The code comments also show this was the original intended behavior. According to the "Zynq 7000 SoC Technical Reference Manual (UG585)" the reset value of the devcfg control register (XDCFG_CTRL_OFFSET) should be 0x0C006000, so CTRL_PCAP_RATE_EN_MASK (bit 25) should be 0 (= max speed) at bootup. However, the devcfg control register reset value seems to be different in reality, and CTRL_PCAP_RATE_EN_MASK seems to be 1 (= reduced speed) at bootup. On top, I don't think it's sane for the driver to just assume a register has a certain initial value and depend on it. Fixes: 37784706bf9e ("fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000") Cc: stable@vger.kernel.org Signed-off-by: Koen Beel --- drivers/fpga/zynq-fpga.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index b7629a0e4813..83030ec1f376 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -344,19 +344,14 @@ static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, /* set configuration register with following options: * - enable PCAP interface - * - set throughput for maximum speed (if bistream not encrypted) + * - set throughput for maximum speed (if bitstream not encrypted) * - set CPU in user mode */ ctrl = zynq_fpga_read(priv, CTRL_OFFSET); - if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM) - zynq_fpga_write(priv, CTRL_OFFSET, - (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK - | CTRL_PCAP_RATE_EN_MASK | ctrl)); - else - zynq_fpga_write(priv, CTRL_OFFSET, - (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK - | ctrl)); - + ctrl |= CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK; + FIELD_MODIFY(CTRL_PCAP_RATE_EN_MASK, &ctrl, + (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM) ? 1 : 0); + zynq_fpga_write(priv, CTRL_OFFSET, ctrl); /* We expect that the command queue is empty right now. */ status = zynq_fpga_read(priv, STATUS_OFFSET); -- 2.51.0