From: Tom Rix <trix@redhat.com>
To: Xu Yilun <yilun.xu@intel.com>,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: lgoncalv@redhat.com, Wu Hao <hao.wu@intel.com>,
Matthew Gerlach <matthew.gerlach@linux.intel.com>,
Russ Weight <russell.h.weight@intel.com>
Subject: Re: [PATCH v3 4/4] fpga: dfl: add support for N3000 nios private feature
Date: Tue, 4 Aug 2020 11:45:33 -0700 [thread overview]
Message-ID: <b5d4157b-1bdf-445c-58a7-abd2f485a5ff@redhat.com> (raw)
In-Reply-To: <1596524715-18038-5-git-send-email-yilun.xu@intel.com>
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Some minor edits.
I have added definitions for fec, kr, and rs.
Reviewed-by: Tom Rix <trix@redhat.com>
Tom
> --- /dev/null
> +++ b/Documentation/fpga/dfl-n3000-nios.rst
> @@ -0,0 +1,39 @@
> +.. SPDX-License-Identifier: GPL-2.0
> +
> +=====================================
> +DFL N3000 Nios Private Feature Driver
> +=====================================
> +
> +The dfl n3000 nios driver supports for the nios handshake private feature on
> +Intel N3000 FPGA Card.
> +
> +This private feature provides a handshake interface to FPGA NIOS firmware,
> +which receives the ethernet retimer configuration command from host and
> +do the configuration via an internal SPI master. When nios finished the
does the configuration..
When nios finishes the ..
> +configuration, host takes over the ownership of the SPI master to control an
> +Intel MAX10 BMC Chip on the SPI bus.
> +
> +So the driver does 2 major tasks on probe, requires NIOS firmware to configure
, uses the NIOS firmware to configure the ethernet retimer, and then ..
> +the ethernet retimer by operating the handshake interfaces, and then creates a
> +spi master platform device with the MAX10 device info in spi_board_info.
> +
> +Module Parameters
> +=================
> +
> +The dfl n3000 nios driver supports the following module parameters:
> +
> +* fec_mode: string
> + Require the NIOS firmware to set the FEC mode of the ethernet retimer on
the FEC (Forward Error Correction) mode
> + the PAC N3000 FPGA card. The possible values could be:
> +
> + - "rs": RS FEC mode (default)
- "rs" : Reed Solomon FEC (default)
> + - "kr": KR FEC mode
- "kr": Fire Code FEC
> + - "no": NO FEC mode
> +
> + The configuration could only be set once after the board powers up, the
The configuration can only be ..
> + firmware will not accept a second configuration afterward. So the fec mode
second configuration.
> + will not be changed if the module is reloaded with a different param value.
> +
> + The configured value of the fec mode could be queried from sysfs node:
> +
> + /sys/bus/dfl/devices/dfl-fme.X.X/fec_mode
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next prev parent reply other threads:[~2020-08-04 18:45 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-04 7:05 [PATCH v3 0/4] Modularization of DFL private feature drivers Xu Yilun
2020-08-04 7:05 ` Xu Yilun
2020-08-04 7:05 ` [PATCH v3 1/4] fpga: dfl: change data type of feature id to u16 Xu Yilun
2020-08-04 7:05 ` Xu Yilun
2020-08-05 9:13 ` Wu, Hao
2020-08-05 9:13 ` Wu, Hao
2020-08-04 7:05 ` [PATCH v3 2/4] fpga: dfl: map feature mmio resources in their own feature drivers Xu Yilun
2020-08-04 7:05 ` Xu Yilun
2020-08-05 12:15 ` Wu, Hao
2020-08-05 12:15 ` Wu, Hao
2020-08-06 2:43 ` Xu Yilun
2020-08-04 7:05 ` [PATCH v3 3/4] fpga: dfl: create a dfl bus type to support DFL devices Xu Yilun
2020-08-04 7:05 ` Xu Yilun
2020-08-05 10:29 ` Wu, Hao
2020-08-05 10:29 ` Wu, Hao
2020-08-06 6:02 ` Xu Yilun
2020-08-06 7:11 ` Wu, Hao
2020-08-06 8:50 ` Xu Yilun
2020-08-04 7:05 ` [PATCH v3 4/4] fpga: dfl: add support for N3000 nios private feature Xu Yilun
2020-08-04 7:05 ` Xu Yilun
2020-08-04 12:56 ` Wu, Hao
2020-08-04 12:56 ` Wu, Hao
2020-08-05 8:35 ` Xu Yilun
2020-08-05 8:35 ` Xu Yilun
2020-08-05 9:11 ` Wu, Hao
2020-08-05 9:11 ` Wu, Hao
2020-08-04 18:45 ` Tom Rix [this message]
2020-08-05 8:36 ` Xu Yilun
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