Some minor edits.

I have added definitions for fec, kr, and rs.

Reviewed-by: Tom Rix <trix@redhat.com>

Tom

--- /dev/null
+++ b/Documentation/fpga/dfl-n3000-nios.rst
@@ -0,0 +1,39 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=====================================
+DFL N3000 Nios Private Feature Driver
+=====================================
+
+The dfl n3000 nios driver supports for the nios handshake private feature on
+Intel N3000 FPGA Card.
+
+This private feature provides a handshake interface to FPGA NIOS firmware,
+which receives the ethernet retimer configuration command from host and
+do the configuration via an internal SPI master. When nios finished the

does the configuration..

When nios finishes the ..

+configuration, host takes over the ownership of the SPI master to control an
+Intel MAX10 BMC Chip on the SPI bus.
+
+So the driver does 2 major tasks on probe, requires NIOS firmware to configure

+the ethernet retimer by operating the handshake interfaces, and then creates a
+spi master platform device with the MAX10 device info in spi_board_info.
+
+Module Parameters
+=================
+
+The dfl n3000 nios driver supports the following module parameters:
+
+* fec_mode: string
+  Require the NIOS firmware to set the FEC mode of the ethernet retimer on

+  the PAC N3000 FPGA card. The possible values could be:
+
+  - "rs": RS FEC mode (default)

+  - "kr": KR FEC mode

+  - "no": NO FEC mode
+
+  The configuration could only be set once after the board powers up, the

+  firmware will not accept a second configuration afterward. So the fec mode

+  will not be changed if the module is reloaded with a different param value.
+
+  The configured value of the fec mode could be queried from sysfs node:
+
+  /sys/bus/dfl/devices/dfl-fme.X.X/fec_mode