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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Cc: hao.wu@intel.com, yilun.xu@intel.com,
	Russ Weight <russell.h.weight@intel.com>,
	basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
	mdf@kernel.org, linux-fpga@vger.kernel.org,
	linux-doc@vger.kernel.org, LKML <linux-kernel@vger.kernel.org>,
	tianfei.zhang@intel.com, corbet@lwn.net,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	linux-serial <linux-serial@vger.kernel.org>,
	Jiri Slaby <jirislaby@kernel.org>,
	geert+renesas@glider.be,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk,
	johan@kernel.org, Lukas Wunner <lukas@wunner.de>,
	marpagan@redhat.com, bagasdotme@gmail.com
Subject: Re: [PATCH v7 3/4] fpga: dfl: add basic support for DFHv1
Date: Wed, 21 Dec 2022 13:58:37 +0200 (EET)	[thread overview]
Message-ID: <c041442c-fb78-e1a0-c67-a5c2ee947@linux.intel.com> (raw)
In-Reply-To: <20221220163652.499831-4-matthew.gerlach@linux.intel.com>

[-- Attachment #1: Type: text/plain, Size: 2587 bytes --]

On Tue, 20 Dec 2022, matthew.gerlach@linux.intel.com wrote:

> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> 
> Version 1 of the Device Feature Header (DFH) definition adds
> functionality to the DFL bus.
> 
> A DFHv1 header may have one or more parameter blocks that
> further describes the HW to SW.  Add support to the DFL bus
> to parse the MSI-X parameter.
> 
> The location of a feature's register set is explicitly
> described in DFHv1 and can be relative to the base of the DFHv1
> or an absolute address.  Parse the location and pass the information
> to DFL driver.
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> ---
> v7: no change
> 
> v6: move MSI_X parameter definitions to drivers/fpga/dfl.h
> 
> v5: update field names
>     fix find_param/dfh_get_psize
>     clean up mmio_res assignments
>     use u64* instead of void*
>     use FIELD_GET instead of masking
> 
> v4: s/MSIX/MSI_X
>     move kernel doc to implementation
>     use structure assignment
>     fix decode of absolute address
>     clean up comment in parse_feature_irqs
>     remove use of csr_res
> 
> v3: remove unneeded blank line
>     use clearer variable name
>     pass finfo into parse_feature_irqs()
>     refactor code for better indentation
>     use switch statement for irq parsing
>     squash in code parsing register location
> 
> v2: fix kernel doc
>     clarify use of DFH_VERSION field
> ---

> +static u64 *find_param(u64 *params, resource_size_t max, int param_id)
> +{
> +	u64 *end = params + max / sizeof(u64);
> +	u64 v, next;
> +
> +	while (params < end) {
> +		v = *params;
> +		if (param_id == FIELD_GET(DFHv1_PARAM_HDR_ID, v))
> +			return params;
> +
> +		next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, v);
> +		params += next;
> +		if (FIELD_GET(DFHv1_PARAM_HDR_NEXT_EOP, v))
> +			break;
> +	}
> +
> +	return NULL;
> +}
> +
> +/**
> + * dfh_find_param() - find data for the given parameter id
> + * @dfl_dev: dfl device
> + * @param: id of dfl parameter
> + *
> + * Return: pointer to parameter header on success, NULL otherwise.
> + */
> +u64 *dfh_find_param(struct dfl_device *dfl_dev, int param_id)
> +{
> +	return find_param(dfl_dev->params, dfl_dev->param_size, param_id);
> +}
> +EXPORT_SYMBOL_GPL(dfh_find_param);

BTW, should there be a way for the caller to ensure the parameter is long 
enough?

All callers probably want to ensure the length of the parameter is valid 
so it would perhaps make sense to add a parameter for the required 
(minimum) length?


-- 
 i.

  parent reply	other threads:[~2022-12-21 12:00 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-20 16:36 [PATCH v7 0/4] Enhance definition of DFH and use enhancements for UART driver matthew.gerlach
2022-12-20 16:36 ` [PATCH v7 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-12-20 16:53   ` Andy Shevchenko
2022-12-21 16:52     ` matthew.gerlach
2022-12-20 16:36 ` [PATCH v7 2/4] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-12-20 16:54   ` Andy Shevchenko
2022-12-20 16:36 ` [PATCH v7 3/4] fpga: dfl: add basic support for DFHv1 matthew.gerlach
2022-12-20 17:03   ` Andy Shevchenko
2022-12-21 19:14     ` matthew.gerlach
2022-12-26  3:15       ` Xu Yilun
2022-12-31 20:46         ` matthew.gerlach
2023-01-03  4:22           ` Xu Yilun
2023-01-03 19:50             ` matthew.gerlach
2023-01-04  2:34               ` Xu Yilun
2022-12-21 11:58   ` Ilpo Järvinen [this message]
2022-12-21 22:29     ` matthew.gerlach
2022-12-20 16:36 ` [PATCH v7 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-12-20 17:09   ` Andy Shevchenko
2022-12-21 17:26     ` Marco Pagani
2022-12-21 19:52       ` Marco Pagani
2022-12-21 22:37         ` matthew.gerlach
2022-12-21 22:16     ` matthew.gerlach

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