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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Ian Dannapel <iansdannapel@gmail.com>
Cc: mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com,
	trix@redhat.com, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, neil.armstrong@linaro.org,
	heiko.stuebner@cherry.de, rafal@milecki.pl,
	linus.walleij@linaro.org, linux-fpga@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings
Date: Sat, 28 Sep 2024 09:31:49 +0200	[thread overview]
Message-ID: <c6ac1c4d-7f7a-41a9-9f32-55428f88bdfe@kernel.org> (raw)
In-Reply-To: <CAKrir7irvRbwCsdjF_NNfWy68wTDfRuyW2oHb90gYgBA=L7-Tg@mail.gmail.com>

On 27/09/2024 17:34, Ian Dannapel wrote:
> Thanks for the review Krzysztof.
> 
> Am Fr., 27. Sept. 2024 um 16:26 Uhr schrieb Krzysztof Kozlowski
> <krzk@kernel.org>:
>>
>> On 27/09/2024 16:14, iansdannapel@gmail.com wrote:
>>> From: Ian Dannapel <iansdannapel@gmail.com>
>>>
>>> Add device tree binding documentation for configuring Efinix FPGA
>>> using serial SPI passive programming mode.
>>>
>>> Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
>>> ---
>>>  .../fpga/efinix,trion-spi-passive.yaml        | 85 +++++++++++++++++++
>>>  1 file changed, 85 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
>>> new file mode 100644
>>> index 000000000000..ec6697fa6f44
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
>>> @@ -0,0 +1,85 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Efinix SPI FPGA Manager
>>> +
>>> +maintainers:
>>> +  - Ian Dannapel <iansdannapel@gmail.com>
>>> +
>>> +description: |
>>> +  Efinix Trion and Titanium Series FPGAs support a method of loading the
>>> +  bitstream over what is referred to as "SPI Passive Programming".
>>> +  Only serial (1x bus width) is supported, setting the programming mode
>>> +  is not in the scope the this manager and must be done elsewhere.
>>> +
>>> +  Warning: The slave serial link is not technically SPI and therefore it is
>>> +  not recommended to have other devices on the same bus since it might
>>> +  interfere or be interfered by other transmissions.
>>> +
>>> +  References:
>>> +  - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf
>>> +  - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf
>>> +
>>> +allOf:
>>> +  - $ref: /schemas/spi/spi-peripheral-props.yaml#
>>> +
>>> +properties:
>>> +  compatible:
>>> +    enum:
>>> +      - efinix,trion-spi-passive
>>> +      - efinix,titanium-spi-passive
>>
>> 1. Your driver suggests these are compatible, so make them compatible
>> with using fallback.
>>
>> 2. What is "spi-passive"? Compatible is supposed to be the name of the
>> device, so I assume this is "trion"? Can trion be anything else than fpga?
> spi-passive is the programming mode, where the device is in slave
> mode. There are also other modes, but not supported by this driver.

But we do no describe here drivers, so it does no matter what it supports.

> The name was inspired by similar drivers (spi-xilinx.c). Isn't just
> "efinix,trion"/"efinix,titanium" too generic?

What do you mean too generic? What else could it be? BTW, that was my
question, which you did not answer. Bindings describe hardware, so
describe here hardware.

>>
>>> +
>>> +  spi-cpha: true
>>> +
>>> +  spi-cpol: true
>>> +
>>> +  spi-max-frequency:
>>> +    maximum: 25000000
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +  creset-gpios:
>>
>> reset-gpios
>>
>> Do not invent own properties.
>>
>>> +    description:
>>> +      reset and re-configuration trigger pin (low active)
>>> +    maxItems: 1
>>> +
>>> +  cs-gpios:
>>> +    description:
>>> +      chip-select pin (low active)
>>
>> Eee? That's a property of controller, not child. Aren't you duplicating
>> existing controller property?
> This device uses this pin in combination with the reset to enter the
> programming mode. Also, the driver must guarantee that the pin is

Isn't this the same on every SPI device?

> active for the whole transfer process, including ending dummy bits.
> This is why I added a warning to NOT use this driver with other
> devices on the same bus.

Not really related. None of this grants exception from duplicating
controller's property.

How do you think it will even work in Linux, if same GPIO is requested
twice (imagine controller also has it)? Till now, this would be -EBUSY.

But regardless of implementation, I still do not understand why do you
need duplicate same chip-select. Maybe just the naming is the confusion,
dunno.


Best regards,
Krzysztof


  reply	other threads:[~2024-09-28  7:31 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-27 14:14 [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver iansdannapel
2024-09-27 14:14 ` [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings iansdannapel
2024-09-27 14:26   ` Krzysztof Kozlowski
2024-09-27 15:34     ` Ian Dannapel
2024-09-28  7:31       ` Krzysztof Kozlowski [this message]
2024-09-28 12:33         ` Ian Dannapel
2024-09-28 12:53           ` Krzysztof Kozlowski
2024-09-28 14:26             ` Ian Dannapel
2024-09-29 19:49               ` Krzysztof Kozlowski
2024-09-27 14:14 ` [PATCH 3/3] dt-bindings: vendor-prefix: Add prefix for Efinix, Inc iansdannapel
2024-09-27 14:26   ` Krzysztof Kozlowski
2024-09-30  6:23   ` Alexander Dahl
2024-09-27 14:14 ` [PATCH v3 0/3] Summary of changes iansdannapel
2024-09-27 14:27   ` Krzysztof Kozlowski
2024-09-27 14:22 ` [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver Krzysztof Kozlowski
2024-10-18  1:22   ` Xu Yilun
2024-10-18  1:37 ` Xu Yilun
2024-10-18 16:58   ` Conor Dooley
2024-10-21  2:10     ` Xu Yilun
2024-10-21 12:18       ` Conor Dooley
2024-10-21 13:23         ` Ian Dannapel

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