Re: [PATCH v2 0/2] Enable FPGA Manager support for Agilex5

["Romli, Khairul Anuar" <khairul.anuar.romli@altera.com>]

On 13/11/2025 3:13 pm, Krzysztof Kozlowski wrote:
> On 13/11/2025 07:01, Xu Yilun wrote:
>> On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote:
>>> This patch series adds device tree bindings, driver support, and DTS
>>> updates to enable FPGA Manager functionality for Intel Agilex5 SoC.
>>>
>>> These changes are intended to enable FPGA programming and management
>>> capabilities on Agilex5-based platforms.
>>>
>>> ---
>>> Notes:
>>> Patch #3 depends on  "arm64: dts: intel: Add Agilex5 SVC node with memory
>>
>> There is no patch #3 now. Should be Patch #2 ?
>>
>>> region" from
>>> https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/
>>>
>>> This patch series is applied on socfpga maintainer's tree
>>> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19
>>
>> Given that, @Dinh Nguyen could you take the series if you are good?
>
> This was never tested, so series cannot be taken.
>
> NAK, Altera should test the code BEFORE sending it to upstream, not
> after we say it was not tested.
>
> Best regards,
> Krzysztof

If you are referring to the code being tested on the Agilex5, it was
tested. I even take the measure to add the debug print the in init to
see if the fallback is working, which it did.

Of course I took clock manager patch from Dinh's clock manager driver
for Agilex5 have local defconfig instead of using default defconfig for
testing the code.

https://lore.kernel.org/all/9326ee66cb8e33c0fe83a24e9a1effc8da252ff2.1760396607.git.khairul.anuar.romli@altera.com/

Are you referring to different kind of test?

Thanks.

Best Regards,
Khairul