[PATCH v2 0/2] Enable FPGA Manager support for Agilex5

[PATCH v2 0/2] Enable FPGA Manager support for Agilex5

[Khairul Anuar Romli]

This patch series adds device tree bindings, driver support, and DTS
updates to enable FPGA Manager functionality for Intel Agilex5 SoC.

These changes are intended to enable FPGA programming and management
capabilities on Agilex5-based platforms.

---
Notes:
Patch #3 depends on  "arm64: dts: intel: Add Agilex5 SVC node with memory
region" from
https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/

This patch series is applied on socfpga maintainer's tree
https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19

Changes in v2:
	- Drop "fpga: stratix10-soc: Add support for Agilex5"
	- Add fallback compatible in DT
---
Khairul Anuar Romli (2):
  dt-bindings: fpga: stratix10: add support for Agilex5
  arm64: dts: agilex5: add fpga-region and fpga-mgr nodes

 .../bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml  |  1 +
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi       | 12 ++++++++++++
 2 files changed, 13 insertions(+)

-- 
2.43.7

[PATCH v2 1/2] dt-bindings: fpga: stratix10: add support for Agilex5

[Khairul Anuar Romli]

The Agilex 5 SoC FPGA manager introduces updated hardware features and
register maps that require explicit binding support to enable correct
initialization and control through the FPGA manager subsystem.

It allows FPGA manager drivers detect and configure Agilex 5 FPGA managers
properly. This changes also keep device tree bindings up to date with
hardware platforms changes.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v2:
	- No changes in this patch
---
 .../devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
index 6e536d6b28a9..b531522cca07 100644
--- a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
+++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
@@ -23,6 +23,7 @@ properties:
     enum:
       - intel,stratix10-soc-fpga-mgr
       - intel,agilex-soc-fpga-mgr
+      - intel,agilex5-soc-fpga-mgr
 
 required:
   - compatible
-- 
2.43.7

[PATCH v2 2/2] arm64: dts: agilex5: add fpga-region and fpga-mgr nodes

[Khairul Anuar Romli]

The Intel Agilex 5 SoC contains a programmable FPGA region that requires
proper device tree description to enable FPGA manager support in the Linux
kernel. Without the 'fpga-region' and 'fpga-mgr' nodes, the kernel cannot
detect or manage the FPGA hardware correctly.

This patch adds a 'fpga-region' node with compatible = "fpga-region", along
with appropriate #address-cells and #size-cells properties, to describe the
FPGA region layout.

Also defines specific compatible string for Agilex5 and add Agilex string
as fallback for stratix10-soc driver initialization.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v2:
	- All fallback compatible string to ensure driver is still able to
	  initialize without new compatible string added in the driver.
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index bf7128adddde..06be0b8671c0 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -85,9 +85,21 @@ svc {
 			method = "smc";
 			memory-region = <&service_reserved>;
 			iommus = <&smmu 10>;
+
+			fpga_mgr: fpga-mgr {
+				compatible = "intel,agilex5-soc-fpga-mgr",
+					     "intel,agilex-soc-fpga-mgr";
+			};
 		};
 	};
 
+	fpga-region {
+		compatible = "fpga-region";
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		fpga-mgr = <&fpga_mgr>;
+	};
+
 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";
-- 
2.43.7

Re: [PATCH v2 1/2] dt-bindings: fpga: stratix10: add support for Agilex5

[Xu Yilun]

On Thu, Nov 13, 2025 at 12:43:55PM +0800, Khairul Anuar Romli wrote:
> The Agilex 5 SoC FPGA manager introduces updated hardware features and
> register maps that require explicit binding support to enable correct
> initialization and control through the FPGA manager subsystem.
> 
> It allows FPGA manager drivers detect and configure Agilex 5 FPGA managers
> properly. This changes also keep device tree bindings up to date with
> hardware platforms changes.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v2:
> 	- No changes in this patch
> ---
>  .../devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml   | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> index 6e536d6b28a9..b531522cca07 100644
> --- a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> +++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> @@ -23,6 +23,7 @@ properties:
>      enum:
>        - intel,stratix10-soc-fpga-mgr
>        - intel,agilex-soc-fpga-mgr
> +      - intel,agilex5-soc-fpga-mgr

Reviewed-by: Xu Yilun <yilun.xu@intel.com>

>  
>  required:
>    - compatible
> -- 
> 2.43.7
> 
> 

Re: [PATCH v2 2/2] arm64: dts: agilex5: add fpga-region and fpga-mgr nodes

[Xu Yilun]

On Thu, Nov 13, 2025 at 12:43:56PM +0800, Khairul Anuar Romli wrote:
> The Intel Agilex 5 SoC contains a programmable FPGA region that requires
> proper device tree description to enable FPGA manager support in the Linux
> kernel. Without the 'fpga-region' and 'fpga-mgr' nodes, the kernel cannot
> detect or manage the FPGA hardware correctly.
> 
> This patch adds a 'fpga-region' node with compatible = "fpga-region", along
> with appropriate #address-cells and #size-cells properties, to describe the
> FPGA region layout.
> 
> Also defines specific compatible string for Agilex5 and add Agilex string
> as fallback for stratix10-soc driver initialization.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>

Reviewed-by: Xu Yilun <yilun.xu@intel.com>

Re: [PATCH v2 0/2] Enable FPGA Manager support for Agilex5

[Xu Yilun]

On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote:
> This patch series adds device tree bindings, driver support, and DTS
> updates to enable FPGA Manager functionality for Intel Agilex5 SoC.
> 
> These changes are intended to enable FPGA programming and management
> capabilities on Agilex5-based platforms.
> 
> ---
> Notes:
> Patch #3 depends on  "arm64: dts: intel: Add Agilex5 SVC node with memory

There is no patch #3 now. Should be Patch #2 ?

> region" from
> https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/
> 
> This patch series is applied on socfpga maintainer's tree
> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19

Given that, @Dinh Nguyen could you take the series if you are good?

Thanks,
Yilun

> 
> Changes in v2:
> 	- Drop "fpga: stratix10-soc: Add support for Agilex5"
> 	- Add fallback compatible in DT
> ---
> Khairul Anuar Romli (2):
>   dt-bindings: fpga: stratix10: add support for Agilex5
>   arm64: dts: agilex5: add fpga-region and fpga-mgr nodes
> 
>  .../bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml  |  1 +
>  arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi       | 12 ++++++++++++
>  2 files changed, 13 insertions(+)
> 
> -- 
> 2.43.7
> 
> 

Re: [PATCH v2 2/2] arm64: dts: agilex5: add fpga-region and fpga-mgr nodes

[Krzysztof Kozlowski]

On 13/11/2025 05:43, Khairul Anuar Romli wrote:
> The Intel Agilex 5 SoC contains a programmable FPGA region that requires
> proper device tree description to enable FPGA manager support in the Linux
> kernel. Without the 'fpga-region' and 'fpga-mgr' nodes, the kernel cannot
> detect or manage the FPGA hardware correctly.
> 
> This patch adds a 'fpga-region' node with compatible = "fpga-region", along
> with appropriate #address-cells and #size-cells properties, to describe the
> FPGA region layout.
> 
> Also defines specific compatible string for Agilex5 and add Agilex string
> as fallback for stratix10-soc driver initialization.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v2:
> 	- All fallback compatible string to ensure driver is still able to
> 	  initialize without new compatible string added in the driver.
> ---
>  arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index bf7128adddde..06be0b8671c0 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -85,9 +85,21 @@ svc {
>  			method = "smc";
>  			memory-region = <&service_reserved>;
>  			iommus = <&smmu 10>;
> +
> +			fpga_mgr: fpga-mgr {
> +				compatible = "intel,agilex5-soc-fpga-mgr",
> +					     "intel,agilex-soc-fpga-mgr";


You did not bother to test this...

Best regards,
Krzysztof

Re: [PATCH v2 2/2] arm64: dts: agilex5: add fpga-region and fpga-mgr nodes

[Krzysztof Kozlowski]

On 13/11/2025 06:55, Xu Yilun wrote:
> On Thu, Nov 13, 2025 at 12:43:56PM +0800, Khairul Anuar Romli wrote:
>> The Intel Agilex 5 SoC contains a programmable FPGA region that requires
>> proper device tree description to enable FPGA manager support in the Linux
>> kernel. Without the 'fpga-region' and 'fpga-mgr' nodes, the kernel cannot
>> detect or manage the FPGA hardware correctly.
>>
>> This patch adds a 'fpga-region' node with compatible = "fpga-region", along
>> with appropriate #address-cells and #size-cells properties, to describe the
>> FPGA region layout.
>>
>> Also defines specific compatible string for Agilex5 and add Agilex string
>> as fallback for stratix10-soc driver initialization.
>>
>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> 
> Reviewed-by: Xu Yilun <yilun.xu@intel.com>

How this can be reviewed if it is completely wrong and obviously not
matching the bindings from this patchset?

Best regards,
Krzysztof

Re: [PATCH v2 0/2] Enable FPGA Manager support for Agilex5

[Krzysztof Kozlowski]

On 13/11/2025 07:01, Xu Yilun wrote:
> On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote:
>> This patch series adds device tree bindings, driver support, and DTS
>> updates to enable FPGA Manager functionality for Intel Agilex5 SoC.
>>
>> These changes are intended to enable FPGA programming and management
>> capabilities on Agilex5-based platforms.
>>
>> ---
>> Notes:
>> Patch #3 depends on  "arm64: dts: intel: Add Agilex5 SVC node with memory
> 
> There is no patch #3 now. Should be Patch #2 ?
> 
>> region" from
>> https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/
>>
>> This patch series is applied on socfpga maintainer's tree
>> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19
> 
> Given that, @Dinh Nguyen could you take the series if you are good?

This was never tested, so series cannot be taken.

NAK, Altera should test the code BEFORE sending it to upstream, not
after we say it was not tested.

Best regards,
Krzysztof

Re: [PATCH v2 0/2] Enable FPGA Manager support for Agilex5

[Romli, Khairul Anuar]

On 13/11/2025 3:13 pm, Krzysztof Kozlowski wrote:
> On 13/11/2025 07:01, Xu Yilun wrote:
>> On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote:
>>> This patch series adds device tree bindings, driver support, and DTS
>>> updates to enable FPGA Manager functionality for Intel Agilex5 SoC.
>>>
>>> These changes are intended to enable FPGA programming and management
>>> capabilities on Agilex5-based platforms.
>>>
>>> ---
>>> Notes:
>>> Patch #3 depends on  "arm64: dts: intel: Add Agilex5 SVC node with memory
>>
>> There is no patch #3 now. Should be Patch #2 ?
>>
>>> region" from
>>> https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/
>>>
>>> This patch series is applied on socfpga maintainer's tree
>>> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19
>>
>> Given that, @Dinh Nguyen could you take the series if you are good?
>
> This was never tested, so series cannot be taken.
>
> NAK, Altera should test the code BEFORE sending it to upstream, not
> after we say it was not tested.
>
> Best regards,
> Krzysztof

If you are referring to the code being tested on the Agilex5, it was
tested. I even take the measure to add the debug print the in init to
see if the fallback is working, which it did.

Of course I took clock manager patch from Dinh's clock manager driver
for Agilex5 have local defconfig instead of using default defconfig for
testing the code.

https://lore.kernel.org/all/9326ee66cb8e33c0fe83a24e9a1effc8da252ff2.1760396607.git.khairul.anuar.romli@altera.com/

Are you referring to different kind of test?

Thanks.

Best Regards,
Khairul

Re: [PATCH v2 2/2] arm64: dts: agilex5: add fpga-region and fpga-mgr nodes

[Romli, Khairul Anuar]

On 13/11/2025 3:12 pm, Krzysztof Kozlowski wrote:
> On 13/11/2025 06:55, Xu Yilun wrote:
>> On Thu, Nov 13, 2025 at 12:43:56PM +0800, Khairul Anuar Romli wrote:
>>> The Intel Agilex 5 SoC contains a programmable FPGA region that requires
>>> proper device tree description to enable FPGA manager support in the Linux
>>> kernel. Without the 'fpga-region' and 'fpga-mgr' nodes, the kernel cannot
>>> detect or manage the FPGA hardware correctly.
>>>
>>> This patch adds a 'fpga-region' node with compatible = "fpga-region", along
>>> with appropriate #address-cells and #size-cells properties, to describe the
>>> FPGA region layout.
>>>
>>> Also defines specific compatible string for Agilex5 and add Agilex string
>>> as fallback for stratix10-soc driver initialization.
>>>
>>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>>
>> Reviewed-by: Xu Yilun <yilun.xu@intel.com>
> 
> How this can be reviewed if it is completely wrong and obviously not
> matching the bindings from this patchset?
> 
> Best regards,
> Krzysztof

Could you point out which part that I need to fix?

Thanks.

Best Regards,
Khairul

Re: [PATCH v2 0/2] Enable FPGA Manager support for Agilex5

[Krzysztof Kozlowski]

On 13/11/2025 10:07, Romli, Khairul Anuar wrote:
> On 13/11/2025 3:13 pm, Krzysztof Kozlowski wrote:
>> On 13/11/2025 07:01, Xu Yilun wrote:
>>> On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote:
>>>> This patch series adds device tree bindings, driver support, and DTS
>>>> updates to enable FPGA Manager functionality for Intel Agilex5 SoC.
>>>>
>>>> These changes are intended to enable FPGA programming and management
>>>> capabilities on Agilex5-based platforms.
>>>>
>>>> ---
>>>> Notes:
>>>> Patch #3 depends on  "arm64: dts: intel: Add Agilex5 SVC node with memory
>>>
>>> There is no patch #3 now. Should be Patch #2 ?
>>>
>>>> region" from
>>>> https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/
>>>>
>>>> This patch series is applied on socfpga maintainer's tree
>>>> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19
>>>
>>> Given that, @Dinh Nguyen could you take the series if you are good?
>>
>> This was never tested, so series cannot be taken.
>>
>> NAK, Altera should test the code BEFORE sending it to upstream, not
>> after we say it was not tested.
>>
>> Best regards,
>> Krzysztof
> 
> If you are referring to the code being tested on the Agilex5, it was
> tested. I even take the measure to add the debug print the in init to
> see if the fallback is working, which it did.
> 
> Of course I took clock manager patch from Dinh's clock manager driver
> for Agilex5 have local defconfig instead of using default defconfig for
> testing the code.
> 
> https://lore.kernel.org/all/9326ee66cb8e33c0fe83a24e9a1effc8da252ff2.1760396607.git.khairul.anuar.romli@altera.com/
> 
> Are you referring to different kind of test?

Yes, test by tools, because you certainly do not want to engage
reviewers if computers do the job fine.

see any DT talk (there where like four last years!) or
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/

Best regards,
Krzysztof

Re: [PATCH v2 2/2] arm64: dts: agilex5: add fpga-region and fpga-mgr nodes

[Krzysztof Kozlowski]

On 13/11/2025 10:09, Romli, Khairul Anuar wrote:
> On 13/11/2025 3:12 pm, Krzysztof Kozlowski wrote:
>> On 13/11/2025 06:55, Xu Yilun wrote:
>>> On Thu, Nov 13, 2025 at 12:43:56PM +0800, Khairul Anuar Romli wrote:
>>>> The Intel Agilex 5 SoC contains a programmable FPGA region that requires
>>>> proper device tree description to enable FPGA manager support in the Linux
>>>> kernel. Without the 'fpga-region' and 'fpga-mgr' nodes, the kernel cannot
>>>> detect or manage the FPGA hardware correctly.
>>>>
>>>> This patch adds a 'fpga-region' node with compatible = "fpga-region", along
>>>> with appropriate #address-cells and #size-cells properties, to describe the
>>>> FPGA region layout.
>>>>
>>>> Also defines specific compatible string for Agilex5 and add Agilex string
>>>> as fallback for stratix10-soc driver initialization.
>>>>
>>>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>>>
>>> Reviewed-by: Xu Yilun <yilun.xu@intel.com>
>>
>> How this can be reviewed if it is completely wrong and obviously not
>> matching the bindings from this patchset?
>>
>> Best regards,
>> Krzysztof
> 
> Could you point out which part that I need to fix?
>

Why? Tools tell you that. Why are you expecting the community to do the
job of compiler/toolchain/toolset? We have better things to do.

Best regards,
Krzysztof

Re: [PATCH v2 0/2] Enable FPGA Manager support for Agilex5

[Romli, Khairul Anuar]

On 13/11/2025 5:10 pm, Krzysztof Kozlowski wrote:
> On 13/11/2025 10:07, Romli, Khairul Anuar wrote:
>> On 13/11/2025 3:13 pm, Krzysztof Kozlowski wrote:
>>> On 13/11/2025 07:01, Xu Yilun wrote:
>>>> On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote:
>>>>> This patch series adds device tree bindings, driver support, and DTS
>>>>> updates to enable FPGA Manager functionality for Intel Agilex5 SoC.
>>>>>
>>>>> These changes are intended to enable FPGA programming and management
>>>>> capabilities on Agilex5-based platforms.
>>>>>
>>>>> ---
>>>>> Notes:
>>>>> Patch #3 depends on  "arm64: dts: intel: Add Agilex5 SVC node with memory
>>>>
>>>> There is no patch #3 now. Should be Patch #2 ?
>>>>
>>>>> region" from
>>>>> https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/
>>>>>
>>>>> This patch series is applied on socfpga maintainer's tree
>>>>> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19
>>>>
>>>> Given that, @Dinh Nguyen could you take the series if you are good?
>>>
>>> This was never tested, so series cannot be taken.
>>>
>>> NAK, Altera should test the code BEFORE sending it to upstream, not
>>> after we say it was not tested.
>>>
>>> Best regards,
>>> Krzysztof
>>
>> If you are referring to the code being tested on the Agilex5, it was
>> tested. I even take the measure to add the debug print the in init to
>> see if the fallback is working, which it did.
>>
>> Of course I took clock manager patch from Dinh's clock manager driver
>> for Agilex5 have local defconfig instead of using default defconfig for
>> testing the code.
>>
>> https://lore.kernel.org/all/9326ee66cb8e33c0fe83a24e9a1effc8da252ff2.1760396607.git.khairul.anuar.romli@altera.com/
>>
>> Are you referring to different kind of test?
>
> Yes, test by tools, because you certainly do not want to engage
> reviewers if computers do the job fine.
>
> see any DT talk (there where like four last years!) or
> Documentation/devicetree/bindings/writing-schema.rst or
> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
>
> Best regards,
> Krzysztof

Thanks, I can see the error with make -j48 CHECK_DTBS=y
DT_SCHEMA_FILES=intel,stratix10-soc-fpga-mgr.yaml
intel/socfpga_agilex5_socdk.dtb;

If i revert back without adding "intel,agilex-soc-fpga-mgr"", the tool
is able to pass without any issue. But we need the driver entry to make
it able to load as it compare the entry from dts and the compatible
entry in the driver.

Should we add back the entry in the driver like in the v1? Or, shall we
defer the driver changes for now?

Thanks.

Best Regards,
Khairul

Re: [PATCH v2 0/2] Enable FPGA Manager support for Agilex5

[Krzysztof Kozlowski]

On 13/11/2025 10:38, Romli, Khairul Anuar wrote:
> On 13/11/2025 5:10 pm, Krzysztof Kozlowski wrote:
>> On 13/11/2025 10:07, Romli, Khairul Anuar wrote:
>>> On 13/11/2025 3:13 pm, Krzysztof Kozlowski wrote:
>>>> On 13/11/2025 07:01, Xu Yilun wrote:
>>>>> On Thu, Nov 13, 2025 at 12:43:54PM +0800, Khairul Anuar Romli wrote:
>>>>>> This patch series adds device tree bindings, driver support, and DTS
>>>>>> updates to enable FPGA Manager functionality for Intel Agilex5 SoC.
>>>>>>
>>>>>> These changes are intended to enable FPGA programming and management
>>>>>> capabilities on Agilex5-based platforms.
>>>>>>
>>>>>> ---
>>>>>> Notes:
>>>>>> Patch #3 depends on  "arm64: dts: intel: Add Agilex5 SVC node with memory
>>>>>
>>>>> There is no patch #3 now. Should be Patch #2 ?
>>>>>
>>>>>> region" from
>>>>>> https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/
>>>>>>
>>>>>> This patch series is applied on socfpga maintainer's tree
>>>>>> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19
>>>>>
>>>>> Given that, @Dinh Nguyen could you take the series if you are good?
>>>>
>>>> This was never tested, so series cannot be taken.
>>>>
>>>> NAK, Altera should test the code BEFORE sending it to upstream, not
>>>> after we say it was not tested.
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>
>>> If you are referring to the code being tested on the Agilex5, it was
>>> tested. I even take the measure to add the debug print the in init to
>>> see if the fallback is working, which it did.
>>>
>>> Of course I took clock manager patch from Dinh's clock manager driver
>>> for Agilex5 have local defconfig instead of using default defconfig for
>>> testing the code.
>>>
>>> https://lore.kernel.org/all/9326ee66cb8e33c0fe83a24e9a1effc8da252ff2.1760396607.git.khairul.anuar.romli@altera.com/
>>>
>>> Are you referring to different kind of test?
>>
>> Yes, test by tools, because you certainly do not want to engage
>> reviewers if computers do the job fine.
>>
>> see any DT talk (there where like four last years!) or
>> Documentation/devicetree/bindings/writing-schema.rst or
>> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
>>
>> Best regards,
>> Krzysztof
> 
> Thanks, I can see the error with make -j48 CHECK_DTBS=y
> DT_SCHEMA_FILES=intel,stratix10-soc-fpga-mgr.yaml
> intel/socfpga_agilex5_socdk.dtb;
> 
> If i revert back without adding "intel,agilex-soc-fpga-mgr"", the tool
> is able to pass without any issue. But we need the driver entry to make
> it able to load as it compare the entry from dts and the compatible
> entry in the driver.
> 
> Should we add back the entry in the driver like in the v1? Or, shall we
> defer the driver changes for now?

You ask now about basics of DT, so sorry but doing homework is your
task. Maybe the beginners DTS talk from this year's OSSEU will be
helpful here. Or one of many other resources...

Best regards,
Krzysztof

Re: [PATCH v2 1/2] dt-bindings: fpga: stratix10: add support for Agilex5

[Conor Dooley]

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On Thu, Nov 13, 2025 at 01:51:47PM +0800, Xu Yilun wrote:
> On Thu, Nov 13, 2025 at 12:43:55PM +0800, Khairul Anuar Romli wrote:
> > The Agilex 5 SoC FPGA manager introduces updated hardware features and
> > register maps that require explicit binding support to enable correct
> > initialization and control through the FPGA manager subsystem.
> > 
> > It allows FPGA manager drivers detect and configure Agilex 5 FPGA managers
> > properly. This changes also keep device tree bindings up to date with
> > hardware platforms changes.
> > 
> > Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> > ---
> > Changes in v2:
> > 	- No changes in this patch

Should have been changed to permit the fallback compatible as discussed.
pw-bot: changes-requested


> > ---
> >  .../devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml   | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> > index 6e536d6b28a9..b531522cca07 100644
> > --- a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> > +++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> > @@ -23,6 +23,7 @@ properties:
> >      enum:
> >        - intel,stratix10-soc-fpga-mgr
> >        - intel,agilex-soc-fpga-mgr
> > +      - intel,agilex5-soc-fpga-mgr
> 
> Reviewed-by: Xu Yilun <yilun.xu@intel.com>
> 
> >  
> >  required:
> >    - compatible
> > -- 
> > 2.43.7
> > 
> > 

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Re: [PATCH v2 1/2] dt-bindings: fpga: stratix10: add support for Agilex5

[Romli, Khairul Anuar]

On 13/11/2025 11:18 pm, Conor Dooley wrote:
> On Thu, Nov 13, 2025 at 01:51:47PM +0800, Xu Yilun wrote:
>> On Thu, Nov 13, 2025 at 12:43:55PM +0800, Khairul Anuar Romli wrote:
>>> The Agilex 5 SoC FPGA manager introduces updated hardware features and
>>> register maps that require explicit binding support to enable correct
>>> initialization and control through the FPGA manager subsystem.
>>>
>>> It allows FPGA manager drivers detect and configure Agilex 5 FPGA managers
>>> properly. This changes also keep device tree bindings up to date with
>>> hardware platforms changes.
>>>
>>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>>> ---
>>> Changes in v2:
>>> 	- No changes in this patch
> 
> Should have been changed to permit the fallback compatible as discussed.
> pw-bot: changes-requested
> 

Working on it right now. Will include the changes in the next version 
after test is done.

Thanks.

Best Regards,
Khairul
  >
>>> ---
>>>   .../devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml   | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
>>> index 6e536d6b28a9..b531522cca07 100644
>>> --- a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
>>> +++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
>>> @@ -23,6 +23,7 @@ properties:
>>>       enum:
>>>         - intel,stratix10-soc-fpga-mgr
>>>         - intel,agilex-soc-fpga-mgr
>>> +      - intel,agilex5-soc-fpga-mgr
>>
>> Reviewed-by: Xu Yilun <yilun.xu@intel.com>
>>
>>>   
>>>   required:
>>>     - compatible
>>> -- 
>>> 2.43.7
>>>
>>>

Re: [PATCH v2 2/2] arm64: dts: agilex5: add fpga-region and fpga-mgr nodes

[Xu Yilun]

On Thu, Nov 13, 2025 at 08:12:24AM +0100, Krzysztof Kozlowski wrote:
> On 13/11/2025 06:55, Xu Yilun wrote:
> > On Thu, Nov 13, 2025 at 12:43:56PM +0800, Khairul Anuar Romli wrote:
> >> The Intel Agilex 5 SoC contains a programmable FPGA region that requires
> >> proper device tree description to enable FPGA manager support in the Linux
> >> kernel. Without the 'fpga-region' and 'fpga-mgr' nodes, the kernel cannot
> >> detect or manage the FPGA hardware correctly.
> >>
> >> This patch adds a 'fpga-region' node with compatible = "fpga-region", along
> >> with appropriate #address-cells and #size-cells properties, to describe the
> >> FPGA region layout.
> >>
> >> Also defines specific compatible string for Agilex5 and add Agilex string
> >> as fallback for stratix10-soc driver initialization.
> >>
> >> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> > 
> > Reviewed-by: Xu Yilun <yilun.xu@intel.com>
> 
> How this can be reviewed if it is completely wrong and obviously not
> matching the bindings from this patchset?

I apologize. Obviously I didn't pay enough effort on DT. Thanks for
pointing out and providing the Doc.

> 
> Best regards,
> Krzysztof