From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Charles Perry <charles.perry@savoirfairelinux.com>
Cc: mdf <mdf@kernel.org>, hao wu <hao.wu@intel.com>,
yilun xu <yilun.xu@intel.com>, trix <trix@redhat.com>,
krzysztof kozlowski+dt <krzysztof.kozlowski+dt@linaro.org>,
Brian CODY <bcody@markem-imaje.com>,
Allen VANDIVER <avandiver@markem-imaje.com>,
linux-fpga <linux-fpga@vger.kernel.org>,
devicetree <devicetree@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT schema
Date: Tue, 30 Jan 2024 18:58:59 +0100 [thread overview]
Message-ID: <cee1ca11-03bf-4a0b-9ff3-490457f9fbe8@linaro.org> (raw)
In-Reply-To: <154341320.386005.1706634341891.JavaMail.zimbra@savoirfairelinux.com>
On 30/01/2024 18:05, Charles Perry wrote:
>
>
> ----- On Jan 30, 2024, at 11:05 AM, Krzysztof Kozlowski krzysztof.kozlowski@linaro.org wrote:
>
>> On 30/01/2024 16:45, Charles Perry wrote:
>>>
>>>>> +
>>>>> + reg:
>>>>> + description:
>>>>> + At least 1 byte of memory mapped IO
>>>>> + maxItems: 1
>>>>> +
>>>>> + prog_b-gpios:
>>>>
>>>>
>>>> No underscores in names.
>>>>
>>>
>>> This is heavily based on "xlnx,fpga-slave-serial.yaml" which uses an underscore.
>>> I can use a dash instead but that would make things inconsistent across the two
>>> schemas.
>>
>> Inconsistency is not a problem. Duplicating technical debt is.
>>
>>>
>>>>
>>>>> + description:
>>>>> + config pin (referred to as PROGRAM_B in the manual)
>>>>> + maxItems: 1
>>>>> +
>>>>> + done-gpios:
>>>>> + description:
>>>>> + config status pin (referred to as DONE in the manual)
>>>>> + maxItems: 1
>>>>> +
>>>>> + init-b-gpios:
>>>>
>>>> Is there init-a? Open other bindings and look how these are called there.
>>>>
>>>
>>> No, the "-b" is there to denote that the signal is active low. I think its
>>> shorthand
>>> for "bar" which is the overline (‾) that electronic engineer put on top of the
>>> name of the
>>> signal on schematics. It comes from the datasheet.
>>
>> Then just "init-gpios"
>>
>> ...
>>
>>>>> +required:
>>>>> + - compatible
>>>>> + - reg
>>>>> + - prog_b-gpios
>>>>> + - done-gpios
>>>>> + - init-b-gpios
>>>>> +
>>>>> +additionalProperties: true
>>>>
>>>> Nope, this cannot bue true.
>>>>
>>>
>>> Ok, I'll put this to false but I'm not quite sure I understand the implications.
>>>
>>> My reasoning behind assigning this to true was that the FPGA is an external
>>> device on a bus that needs to be configured by a bus controller. The bus
>>> controller
>>> would be the parent of the fpga DT node and the later would contain properties
>>> parsed by the bus controller driver.
>>
>> Which bus controller? MMIO bus does not parse children properties.
>> Anyway, if that's the case you miss $ref to respective
>> peripheral-props.yaml matching your bus and then "unevaluatedProperties:
>> false".
>
> This one: https://elixir.bootlin.com/linux/v6.8-rc2/source/Documentation/devicetree/bindings/bus/imx-weim.txt#L56
Eh, ok, so after fast check WEIM looks like some memory interface bus,
so the bus bindings should be moved to memory-controllers and converted
to YAML. Then you add child node properties to own schema and reference
in mc-peripheral-props, which is then referenced in your binding here,
as I mentioned.
Best regards,
Krzysztof
next prev parent reply other threads:[~2024-01-30 17:59 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-29 22:56 [PATCH 1/3] fpga: xilinx-spi: extract a common driver core Charles Perry
2024-01-29 22:56 ` [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT schema Charles Perry
2024-01-30 0:21 ` Rob Herring
2024-01-30 7:52 ` Krzysztof Kozlowski
2024-01-30 7:53 ` Krzysztof Kozlowski
2024-01-30 15:45 ` Charles Perry
2024-01-30 16:05 ` Krzysztof Kozlowski
2024-01-30 17:05 ` Charles Perry
2024-01-30 17:58 ` Krzysztof Kozlowski [this message]
2024-01-30 23:32 ` Charles Perry
2024-01-30 16:09 ` Krzysztof Kozlowski
2024-01-31 11:03 ` Kris Chaplin
2024-02-04 8:30 ` Xu Yilun
2024-02-13 21:54 ` Charles Perry
2024-01-29 22:56 ` [PATCH 3/3] fpga: xilinx-selectmap: add new driver Charles Perry
2024-01-30 7:56 ` Krzysztof Kozlowski
2024-01-31 23:05 ` [PATCH 0/3] " Charles Perry
2024-01-31 23:05 ` [PATCH 1/3] fpga: xilinx-spi: extract a common driver core Charles Perry
2024-02-04 8:22 ` Xu Yilun
2024-02-06 15:39 ` Charles Perry
2024-01-31 23:05 ` [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT schema Charles Perry
2024-02-01 8:07 ` Krzysztof Kozlowski
2024-02-01 18:24 ` Charles Perry
2024-02-02 10:49 ` Krzysztof Kozlowski
2024-02-02 19:52 ` Charles Perry
2024-01-31 23:05 ` [PATCH 3/3] fpga: xilinx-selectmap: add new driver Charles Perry
2024-02-04 8:10 ` Xu Yilun
2024-02-06 15:48 ` Charles Perry
2024-02-02 20:16 ` [PATCH 0/3] " Rob Herring
2024-02-02 20:53 ` Charles Perry
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