[PATCH v5 0/2] Enable FPGA Manager support for Agilex5

[PATCH v5 0/2] Enable FPGA Manager support for Agilex5

[Khairul Anuar Romli]

This patch series adds device tree bindings, driver and DTS updates to
enable FPGA Manager functionality for Intel Agilex5 SoC.

These changes are intended to enable FPGA programming and FPGA management
capabilities on Agilex5-based platforms.

---
Notes:
Patch #2 depends on  "arm64: dts: intel: Add Agilex5 SVC node with memory
region" from
https://lore.kernel.org/all/3381ef56c1ff34a0b54cf76010889b5523ead825.1762387665.git.khairul.anuar.romli@altera.com/

This patch series is applied on socfpga maintainer's tree
https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19

Changes in v5:
	- Revert back to oneOf and use enum without items.
Changes in v4:
	- Simplify the compatible property to use enum without items.
	- Use contains instead of oneOf due to the use of enum without items.
Changes in v3:
	- Add fallback in altera's soc fpga manager compatible properties.
	- Validate with make CHECK_DBTS=y on:
	  - intel/socfpga_agilex5_socdk.dtb (fallback)
          - intel/socfpga_agilex_socdk.dtb (non-fallback)
          - altera/socfpga_stratix10_socdk.dtb (non-fallback)

Changes in v2:
	- Drop "fpga: stratix10-soc: Add support for Agilex5"
	- Add fallback compatible in DT
---
Khairul Anuar Romli (2):
  dt-bindings: fpga: stratix10: add support for Agilex5
  arm64: dts: agilex5: add fpga-region and fpga-mgr nodes

 .../bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml  | 10 +++++++---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi       | 12 ++++++++++++
 2 files changed, 19 insertions(+), 3 deletions(-)

-- 
2.43.7

[PATCH v5 1/2] dt-bindings: fpga: stratix10: add support for Agilex5

[Khairul Anuar Romli]

Agilex5 introduces changes in how reserved memory is mapped and accessed
compared to previous SoC generations. Agilex5 compatible allows stratix10-
FPGA manager driver to handle these changes.

Fallback is added for driver probe and init that rely on matching of table
and DT node.

Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v5:
	- Revert to oneOf and use enum without items.
Changes in v4:
	- Remove redundant "items - enum" as suggested in v3.
	- Simplify compatible property to use contains instead of oneOf.
	- Validate fallback and non-fallback DT. Also validate binding with
          dt_binding_check.
Changes in v3:
	- Add description for Agilex5 Device
	- Add and define fallback to "intel,agilex-soc-fpga-mgr"
	- Validate against Agilex and Stratix10 (non-fallback) and Agilex5
	  (fallback)
Changes in v2:
	- No changes in this patch
---
 .../bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml    | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
index 6e536d6b28a9..14437dfc47a4 100644
--- a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
+++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
@@ -20,9 +20,13 @@ description:
 
 properties:
   compatible:
-    enum:
-      - intel,stratix10-soc-fpga-mgr
-      - intel,agilex-soc-fpga-mgr
+    oneOf:
+      - enum:
+          - intel,stratix10-soc-fpga-mgr
+          - intel,agilex-soc-fpga-mgr
+      - enum:
+          - intel,agilex5-soc-fpga-mgr
+        const: intel,agilex-soc-fpga-mgr
 
 required:
   - compatible
-- 
2.43.7

Re: [PATCH v5 1/2] dt-bindings: fpga: stratix10: add support for Agilex5

[Conor Dooley]

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On Wed, Nov 19, 2025 at 07:34:18AM +0800, Khairul Anuar Romli wrote:
> Agilex5 introduces changes in how reserved memory is mapped and accessed
> compared to previous SoC generations. Agilex5 compatible allows stratix10-
> FPGA manager driver to handle these changes.
> 
> Fallback is added for driver probe and init that rely on matching of table
> and DT node.
> 
> Reviewed-by: Xu Yilun <yilun.xu@intel.com>
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v5:
> 	- Revert to oneOf and use enum without items.
> Changes in v4:
> 	- Remove redundant "items - enum" as suggested in v3.
> 	- Simplify compatible property to use contains instead of oneOf.
> 	- Validate fallback and non-fallback DT. Also validate binding with
>           dt_binding_check.
> Changes in v3:
> 	- Add description for Agilex5 Device
> 	- Add and define fallback to "intel,agilex-soc-fpga-mgr"
> 	- Validate against Agilex and Stratix10 (non-fallback) and Agilex5
> 	  (fallback)
> Changes in v2:
> 	- No changes in this patch
> ---
>  .../bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml    | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> index 6e536d6b28a9..14437dfc47a4 100644
> --- a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> +++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
> @@ -20,9 +20,13 @@ description:
>  
>  properties:
>    compatible:
> -    enum:
> -      - intel,stratix10-soc-fpga-mgr
> -      - intel,agilex-soc-fpga-mgr
> +    oneOf:
> +      - enum:
> +          - intel,stratix10-soc-fpga-mgr
> +          - intel,agilex-soc-fpga-mgr

Great, you've fixed this part.

> +      - enum:
> +          - intel,agilex5-soc-fpga-mgr
> +        const: intel,agilex-soc-fpga-mgr

But unfortunately this is wrong, and you should have noticed it
because the dts patch you have will produce a warning.
This one actually does need the items, you had it right in v3.
You'll note that my v3 feedback specifically said "this construct" and
was inserted at the point of the redundant single item items list:
https://lore.kernel.org/all/20251114-countless-vantage-6e18528d2e31@spud/

pw-bot: changes-requested

Please take some time to both test and understand the change you are
making.

Thanks,
Conor.

>  
>  required:
>    - compatible
> -- 
> 2.43.7
> 

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Re: [PATCH v5 1/2] dt-bindings: fpga: stratix10: add support for Agilex5

[Romli, Khairul Anuar]

On 19/11/2025 9:20 am, Conor Dooley wrote:
> On Wed, Nov 19, 2025 at 07:34:18AM +0800, Khairul Anuar Romli wrote:
>> Agilex5 introduces changes in how reserved memory is mapped and accessed
>> compared to previous SoC generations. Agilex5 compatible allows stratix10-
>> FPGA manager driver to handle these changes.
>>
>> Fallback is added for driver probe and init that rely on matching of table
>> and DT node.
>>
>> Reviewed-by: Xu Yilun <yilun.xu@intel.com>
>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>> ---
>> Changes in v5:
>> 	- Revert to oneOf and use enum without items.
>> Changes in v4:
>> 	- Remove redundant "items - enum" as suggested in v3.
>> 	- Simplify compatible property to use contains instead of oneOf.
>> 	- Validate fallback and non-fallback DT. Also validate binding with
>>            dt_binding_check.
>> Changes in v3:
>> 	- Add description for Agilex5 Device
>> 	- Add and define fallback to "intel,agilex-soc-fpga-mgr"
>> 	- Validate against Agilex and Stratix10 (non-fallback) and Agilex5
>> 	  (fallback)
>> Changes in v2:
>> 	- No changes in this patch
>> ---
>>   .../bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml    | 10 +++++++---
>>   1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
>> index 6e536d6b28a9..14437dfc47a4 100644
>> --- a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
>> +++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.yaml
>> @@ -20,9 +20,13 @@ description:
>>   
>>   properties:
>>     compatible:
>> -    enum:
>> -      - intel,stratix10-soc-fpga-mgr
>> -      - intel,agilex-soc-fpga-mgr
>> +    oneOf:
>> +      - enum:
>> +          - intel,stratix10-soc-fpga-mgr
>> +          - intel,agilex-soc-fpga-mgr
> 
> Great, you've fixed this part.
> 
>> +      - enum:
>> +          - intel,agilex5-soc-fpga-mgr
>> +        const: intel,agilex-soc-fpga-mgr
> 
> But unfortunately this is wrong, and you should have noticed it
> because the dts patch you have will produce a warning.
> This one actually does need the items, you had it right in v3.
> You'll note that my v3 feedback specifically said "this construct" and
> was inserted at the point of the redundant single item items list:
> https://lore.kernel.org/all/20251114-countless-vantage-6e18528d2e31@spud/
> 
> pw-bot: changes-requested
> 
> Please take some time to both test and understand the change you are
> making.
> 
> Thanks,
> Conor.
> 

Yeap, this is the part that I am seeing warning during the test and I am 
trying to resolved it now.

I will go through other bindings with rg --multiline that you shared and 
will send next version after all the test is done.

Thank You.

Best Regards,
Khairul

>>   
>>   required:
>>     - compatible
>> -- 
>> 2.43.7
>>

Re: [PATCH v5 1/2] dt-bindings: fpga: stratix10: add support for Agilex5

[Conor Dooley]

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On Wed, Nov 19, 2025 at 01:45:03AM +0000, Romli, Khairul Anuar wrote:

> I will go through other bindings with rg --multiline that you shared and 
> will send next version after all the test is done.

Unless you're planning on fixing the ones that should not have contains,
that comment was only for Krzysztof.

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[PATCH v5 2/2] arm64: dts: agilex5: add fpga-region and fpga-mgr nodes

[Khairul Anuar Romli]

The Intel Agilex 5 SoC contains a programmable FPGA region that requires
proper device tree description to enable FPGA manager support in the Linux
kernel.

The fpga-region node is introduced to support FPGA partial reconfiguration
through the FPGA Manager framework. This node defines a region in the
device tree that can be dynamically programmed at runtime.

Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v5:
	- No change.
Changes in v4:
	- No changes.
	- Validated with CHECK_DTBS=y as standalone and with
          intel,stratix10-soc-fpga-mgr.yaml
Changes in v3:
	- tested with intel,stratix10-soc-fpga-mgr.yaml
	- Rephrase commit message to make it more concise.
Changes in v2:
	- All fallback compatible string to ensure driver is still able to
	  initialize without new compatible string added in the driver.
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a5c2025a616e..1f5d560f97b2 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -85,9 +85,21 @@ svc {
 			method = "smc";
 			memory-region = <&service_reserved>;
 			iommus = <&smmu 10>;
+
+			fpga_mgr: fpga-mgr {
+				compatible = "intel,agilex5-soc-fpga-mgr",
+					     "intel,agilex-soc-fpga-mgr";
+			};
 		};
 	};
 
+	fpga-region {
+		compatible = "fpga-region";
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		fpga-mgr = <&fpga_mgr>;
+	};
+
 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";
-- 
2.43.7