[PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[Michal Simek]

Convert the generic fpga bridge DT binding to json-schema.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 .../devicetree/bindings/fpga/fpga-bridge.txt  | 13 --------
 .../devicetree/bindings/fpga/fpga-bridge.yaml | 30 +++++++++++++++++++
 .../bindings/fpga/xlnx,pr-decoupler.yaml      |  5 +++-
 3 files changed, 34 insertions(+), 14 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/fpga/fpga-bridge.txt
 create mode 100644 Documentation/devicetree/bindings/fpga/fpga-bridge.yaml

diff --git a/Documentation/devicetree/bindings/fpga/fpga-bridge.txt b/Documentation/devicetree/bindings/fpga/fpga-bridge.txt
deleted file mode 100644
index 72e06917288a..000000000000
--- a/Documentation/devicetree/bindings/fpga/fpga-bridge.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-FPGA Bridge Device Tree Binding
-
-Optional properties:
-- bridge-enable		: 0 if driver should disable bridge at startup
-			  1 if driver should enable bridge at startup
-			  Default is to leave bridge in current state.
-
-Example:
-	fpga_bridge3: fpga-bridge@ffc25080 {
-		compatible = "altr,socfpga-fpga2sdram-bridge";
-		reg = <0xffc25080 0x4>;
-		bridge-enable = <0>;
-	};
diff --git a/Documentation/devicetree/bindings/fpga/fpga-bridge.yaml b/Documentation/devicetree/bindings/fpga/fpga-bridge.yaml
new file mode 100644
index 000000000000..248639c6b560
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/fpga-bridge.yaml
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FPGA Bridge
+
+maintainers:
+  - Michal Simek <michal.simek@amd.com>
+
+properties:
+  $nodename:
+    pattern: "^fpga-bridge(@.*)?$"
+
+  bridge-enable:
+    description: |
+      0 if driver should disable bridge at startup
+      1 if driver should enable bridge at startup
+      Default is to leave bridge in current state.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 0, 1 ]
+
+additionalProperties: true
+
+examples:
+  - |
+    fpga-bridge {
+        bridge-enable = <0>;
+    };
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml b/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml
index a7d4b8e59e19..5bf731f9d99a 100644
--- a/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml
+++ b/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml
@@ -9,6 +9,9 @@ title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
 maintainers:
   - Nava kishore Manne <nava.kishore.manne@amd.com>
 
+allOf:
+  - $ref: fpga-bridge.yaml#
+
 description: |
   The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more
   decouplers/fpga bridges. The controller can decouple/disable the bridges
@@ -51,7 +54,7 @@ required:
   - clocks
   - clock-names
 
-additionalProperties: false
+unevaluatedProperties: false
 
 examples:
   - |
-- 
2.36.1

[PATCH 2/2] dt-bindings: fpga: altera: Convert bridge bindings to yaml

[Michal Simek]

Convert Altera's bridges to yaml with using fpga-bridge.yaml.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 .../fpga/altera-fpga2sdram-bridge.txt         | 13 ----
 .../fpga/altera-fpga2sdram-bridge.yaml        | 34 ++++++++++
 .../bindings/fpga/altera-freeze-bridge.txt    | 20 ------
 .../bindings/fpga/altera-freeze-bridge.yaml   | 41 ++++++++++++
 .../bindings/fpga/altera-hps2fpga-bridge.txt  | 36 -----------
 .../bindings/fpga/altera-hps2fpga-bridge.yaml | 63 +++++++++++++++++++
 6 files changed, 138 insertions(+), 69 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
 delete mode 100644 Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml
 delete mode 100644 Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml

diff --git a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
deleted file mode 100644
index 5dd0ff0f7b4e..000000000000
--- a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-Altera FPGA To SDRAM Bridge Driver
-
-Required properties:
-- compatible		: Should contain "altr,socfpga-fpga2sdram-bridge"
-
-See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
-
-Example:
-	fpga_bridge3: fpga-bridge@ffc25080 {
-		compatible = "altr,socfpga-fpga2sdram-bridge";
-		reg = <0xffc25080 0x4>;
-		bridge-enable = <0>;
-	};
diff --git a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
new file mode 100644
index 000000000000..a3f3fe2729f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/altera-fpga2sdram-bridge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera FPGA To SDRAM Bridge
+
+maintainers:
+  - Xu Yilun <yilun.xu@intel.com>
+
+allOf:
+  - $ref: fpga-bridge.yaml#
+
+properties:
+  compatible:
+    const: altr,socfpga-fpga2sdram-bridge
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    fpga-bridge@ffc25080 {
+        compatible = "altr,socfpga-fpga2sdram-bridge";
+        reg = <0xffc25080 0x4>;
+        bridge-enable = <0>;
+    };
diff --git a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
deleted file mode 100644
index 8b26fbcff3c6..000000000000
--- a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Altera Freeze Bridge Controller Driver
-
-The Altera Freeze Bridge Controller manages one or more freeze bridges.
-The controller can freeze/disable the bridges which prevents signal
-changes from passing through the bridge.  The controller can also
-unfreeze/enable the bridges which allows traffic to pass through the
-bridge normally.
-
-Required properties:
-- compatible		: Should contain "altr,freeze-bridge-controller"
-- regs			: base address and size for freeze bridge module
-
-See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
-
-Example:
-	freeze-controller@100000450 {
-		compatible = "altr,freeze-bridge-controller";
-		regs = <0x1000 0x10>;
-		bridge-enable = <0>;
-	};
diff --git a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml
new file mode 100644
index 000000000000..4a89e3980669
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/altera-freeze-bridge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera Freeze Bridge Controller
+
+description: |
+  The Altera Freeze Bridge Controller manages one or more freeze bridges.
+  The controller can freeze/disable the bridges which prevents signal
+  changes from passing through the bridge. The controller can also
+  unfreeze/enable the bridges which allows traffic to pass through the bridge
+  normally.
+
+maintainers:
+  - Xu Yilun <yilun.xu@intel.com>
+
+allOf:
+  - $ref: fpga-bridge.yaml#
+
+properties:
+  compatible:
+    const: altr,freeze-bridge-controller
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    fpga-bridge@100000450 {
+        compatible = "altr,freeze-bridge-controller";
+        reg = <0x1000 0x10>;
+        bridge-enable = <0>;
+    };
diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
deleted file mode 100644
index 68cce3945b10..000000000000
--- a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Altera FPGA/HPS Bridge Driver
-
-Required properties:
-- regs		: base address and size for AXI bridge module
-- compatible	: Should contain one of:
-		  "altr,socfpga-lwhps2fpga-bridge",
-		  "altr,socfpga-hps2fpga-bridge", or
-		  "altr,socfpga-fpga2hps-bridge"
-- resets	: Phandle and reset specifier for this bridge's reset
-- clocks	: Clocks used by this module.
-
-See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
-
-Example:
-	fpga_bridge0: fpga-bridge@ff400000 {
-		compatible = "altr,socfpga-lwhps2fpga-bridge";
-		reg = <0xff400000 0x100000>;
-		resets = <&rst LWHPS2FPGA_RESET>;
-		clocks = <&l4_main_clk>;
-		bridge-enable = <0>;
-	};
-
-	fpga_bridge1: fpga-bridge@ff500000 {
-		compatible = "altr,socfpga-hps2fpga-bridge";
-		reg = <0xff500000 0x10000>;
-		resets = <&rst HPS2FPGA_RESET>;
-		clocks = <&l4_main_clk>;
-		bridge-enable = <1>;
-	};
-
-	fpga_bridge2: fpga-bridge@ff600000 {
-		compatible = "altr,socfpga-fpga2hps-bridge";
-		reg = <0xff600000 0x100000>;
-		resets = <&rst FPGA2HPS_RESET>;
-		clocks = <&l4_main_clk>;
-	};
diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml
new file mode 100644
index 000000000000..f8210449dfed
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml
@@ -0,0 +1,63 @@
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/altera-hps2fpga-bridge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera FPGA/HPS Bridge
+
+maintainers:
+  - Xu Yilun <yilun.xu@intel.com>
+
+allOf:
+  - $ref: fpga-bridge.yaml#
+
+properties:
+  compatible:
+    enum:
+      - altr,socfpga-lwhps2fpga-bridge
+      - altr,socfpga-hps2fpga-bridge
+      - altr,socfpga-fpga2hps-bridge
+
+  reg:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/reset/altr,rst-mgr.h>
+
+    fpga-bridge@ff400000 {
+      compatible = "altr,socfpga-lwhps2fpga-bridge";
+      reg = <0xff400000 0x100000>;
+      bridge-enable = <0>;
+      clocks = <&l4_main_clk>;
+      resets = <&rst LWHPS2FPGA_RESET>;
+    };
+
+    fpga_bridge1: fpga-bridge@ff500000 {
+      compatible = "altr,socfpga-hps2fpga-bridge";
+      reg = <0xff500000 0x10000>;
+      bridge-enable = <1>;
+      clocks = <&l4_main_clk>;
+      resets = <&rst HPS2FPGA_RESET>;
+    };
+
+    fpga_bridge2: fpga-bridge@ff600000 {
+      compatible = "altr,socfpga-fpga2hps-bridge";
+      reg = <0xff600000 0x100000>;
+      clocks = <&l4_main_clk>;
+      resets = <&rst FPGA2HPS_RESET>;
+    };
-- 
2.36.1

Re: [PATCH 2/2] dt-bindings: fpga: altera: Convert bridge bindings to yaml

[Xu Yilun]

On Fri, Jan 05, 2024 at 05:04:31PM +0100, Michal Simek wrote:
> Convert Altera's bridges to yaml with using fpga-bridge.yaml.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
>  .../fpga/altera-fpga2sdram-bridge.txt         | 13 ----
>  .../fpga/altera-fpga2sdram-bridge.yaml        | 34 ++++++++++
>  .../bindings/fpga/altera-freeze-bridge.txt    | 20 ------
>  .../bindings/fpga/altera-freeze-bridge.yaml   | 41 ++++++++++++
>  .../bindings/fpga/altera-hps2fpga-bridge.txt  | 36 -----------
>  .../bindings/fpga/altera-hps2fpga-bridge.yaml | 63 +++++++++++++++++++
>  6 files changed, 138 insertions(+), 69 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
>  delete mode 100644 Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml
>  delete mode 100644 Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml
> 
> diff --git a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
> deleted file mode 100644
> index 5dd0ff0f7b4e..000000000000
> --- a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -Altera FPGA To SDRAM Bridge Driver
> -
> -Required properties:
> -- compatible		: Should contain "altr,socfpga-fpga2sdram-bridge"
> -
> -See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
> -
> -Example:
> -	fpga_bridge3: fpga-bridge@ffc25080 {
> -		compatible = "altr,socfpga-fpga2sdram-bridge";
> -		reg = <0xffc25080 0x4>;
> -		bridge-enable = <0>;
> -	};
> diff --git a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
> new file mode 100644
> index 000000000000..a3f3fe2729f2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/altera-fpga2sdram-bridge.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera FPGA To SDRAM Bridge
> +
> +maintainers:
> +  - Xu Yilun <yilun.xu@intel.com>
> +
> +allOf:
> +  - $ref: fpga-bridge.yaml#
> +
> +properties:
> +  compatible:
> +    const: altr,socfpga-fpga2sdram-bridge
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg

Is the 'reg' required? I didn't see it in original txt.

> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    fpga-bridge@ffc25080 {
> +        compatible = "altr,socfpga-fpga2sdram-bridge";
> +        reg = <0xffc25080 0x4>;
> +        bridge-enable = <0>;
> +    };
> diff --git a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
> deleted file mode 100644
> index 8b26fbcff3c6..000000000000
> --- a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -Altera Freeze Bridge Controller Driver
> -
> -The Altera Freeze Bridge Controller manages one or more freeze bridges.
> -The controller can freeze/disable the bridges which prevents signal
> -changes from passing through the bridge.  The controller can also
> -unfreeze/enable the bridges which allows traffic to pass through the
> -bridge normally.
> -
> -Required properties:
> -- compatible		: Should contain "altr,freeze-bridge-controller"
> -- regs			: base address and size for freeze bridge module
> -
> -See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
> -
> -Example:
> -	freeze-controller@100000450 {
> -		compatible = "altr,freeze-bridge-controller";
> -		regs = <0x1000 0x10>;
> -		bridge-enable = <0>;
> -	};
> diff --git a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml
> new file mode 100644
> index 000000000000..4a89e3980669
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/altera-freeze-bridge.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera Freeze Bridge Controller
> +
> +description: |
> +  The Altera Freeze Bridge Controller manages one or more freeze bridges.
> +  The controller can freeze/disable the bridges which prevents signal
> +  changes from passing through the bridge. The controller can also
> +  unfreeze/enable the bridges which allows traffic to pass through the bridge
> +  normally.
> +
> +maintainers:
> +  - Xu Yilun <yilun.xu@intel.com>
> +
> +allOf:
> +  - $ref: fpga-bridge.yaml#
> +
> +properties:
> +  compatible:
> +    const: altr,freeze-bridge-controller
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    fpga-bridge@100000450 {
> +        compatible = "altr,freeze-bridge-controller";
> +        reg = <0x1000 0x10>;
> +        bridge-enable = <0>;
> +    };
> diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
> deleted file mode 100644
> index 68cce3945b10..000000000000
> --- a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -Altera FPGA/HPS Bridge Driver
> -
> -Required properties:
> -- regs		: base address and size for AXI bridge module
> -- compatible	: Should contain one of:
> -		  "altr,socfpga-lwhps2fpga-bridge",
> -		  "altr,socfpga-hps2fpga-bridge", or
> -		  "altr,socfpga-fpga2hps-bridge"
> -- resets	: Phandle and reset specifier for this bridge's reset
> -- clocks	: Clocks used by this module.
> -
> -See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
> -
> -Example:
> -	fpga_bridge0: fpga-bridge@ff400000 {
> -		compatible = "altr,socfpga-lwhps2fpga-bridge";
> -		reg = <0xff400000 0x100000>;
> -		resets = <&rst LWHPS2FPGA_RESET>;
> -		clocks = <&l4_main_clk>;
> -		bridge-enable = <0>;
> -	};
> -
> -	fpga_bridge1: fpga-bridge@ff500000 {
> -		compatible = "altr,socfpga-hps2fpga-bridge";
> -		reg = <0xff500000 0x10000>;
> -		resets = <&rst HPS2FPGA_RESET>;
> -		clocks = <&l4_main_clk>;
> -		bridge-enable = <1>;
> -	};
> -
> -	fpga_bridge2: fpga-bridge@ff600000 {
> -		compatible = "altr,socfpga-fpga2hps-bridge";
> -		reg = <0xff600000 0x100000>;
> -		resets = <&rst FPGA2HPS_RESET>;
> -		clocks = <&l4_main_clk>;
> -	};
> diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml
> new file mode 100644
> index 000000000000..f8210449dfed
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml
> @@ -0,0 +1,63 @@

Is the License identifier also needed?


Otherwise, Reviewed-by: Xu Yilun <yilun.xu@intel.com>

Thanks

> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/altera-hps2fpga-bridge.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera FPGA/HPS Bridge
> +
> +maintainers:
> +  - Xu Yilun <yilun.xu@intel.com>
> +
> +allOf:
> +  - $ref: fpga-bridge.yaml#
> +
> +properties:
> +  compatible:
> +    enum:
> +      - altr,socfpga-lwhps2fpga-bridge
> +      - altr,socfpga-hps2fpga-bridge
> +      - altr,socfpga-fpga2hps-bridge
> +
> +  reg:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - resets
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/reset/altr,rst-mgr.h>
> +
> +    fpga-bridge@ff400000 {
> +      compatible = "altr,socfpga-lwhps2fpga-bridge";
> +      reg = <0xff400000 0x100000>;
> +      bridge-enable = <0>;
> +      clocks = <&l4_main_clk>;
> +      resets = <&rst LWHPS2FPGA_RESET>;
> +    };
> +
> +    fpga_bridge1: fpga-bridge@ff500000 {
> +      compatible = "altr,socfpga-hps2fpga-bridge";
> +      reg = <0xff500000 0x10000>;
> +      bridge-enable = <1>;
> +      clocks = <&l4_main_clk>;
> +      resets = <&rst HPS2FPGA_RESET>;
> +    };
> +
> +    fpga_bridge2: fpga-bridge@ff600000 {
> +      compatible = "altr,socfpga-fpga2hps-bridge";
> +      reg = <0xff600000 0x100000>;
> +      clocks = <&l4_main_clk>;
> +      resets = <&rst FPGA2HPS_RESET>;
> +    };
> -- 
> 2.36.1
> 
> 

Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[Xu Yilun]

On Fri, Jan 05, 2024 at 05:04:30PM +0100, Michal Simek wrote:
> Convert the generic fpga bridge DT binding to json-schema.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>

Reviewed-by: Xu Yilun <yilun.xu@intel.com>

Thanks

> ---
> 
>  .../devicetree/bindings/fpga/fpga-bridge.txt  | 13 --------
>  .../devicetree/bindings/fpga/fpga-bridge.yaml | 30 +++++++++++++++++++
>  .../bindings/fpga/xlnx,pr-decoupler.yaml      |  5 +++-
>  3 files changed, 34 insertions(+), 14 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/fpga/fpga-bridge.txt
>  create mode 100644 Documentation/devicetree/bindings/fpga/fpga-bridge.yaml
> 
> diff --git a/Documentation/devicetree/bindings/fpga/fpga-bridge.txt b/Documentation/devicetree/bindings/fpga/fpga-bridge.txt
> deleted file mode 100644
> index 72e06917288a..000000000000
> --- a/Documentation/devicetree/bindings/fpga/fpga-bridge.txt
> +++ /dev/null
> @@ -1,13 +0,0 @@
> -FPGA Bridge Device Tree Binding
> -
> -Optional properties:
> -- bridge-enable		: 0 if driver should disable bridge at startup
> -			  1 if driver should enable bridge at startup
> -			  Default is to leave bridge in current state.
> -
> -Example:
> -	fpga_bridge3: fpga-bridge@ffc25080 {
> -		compatible = "altr,socfpga-fpga2sdram-bridge";
> -		reg = <0xffc25080 0x4>;
> -		bridge-enable = <0>;
> -	};
> diff --git a/Documentation/devicetree/bindings/fpga/fpga-bridge.yaml b/Documentation/devicetree/bindings/fpga/fpga-bridge.yaml
> new file mode 100644
> index 000000000000..248639c6b560
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/fpga-bridge.yaml
> @@ -0,0 +1,30 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: FPGA Bridge
> +
> +maintainers:
> +  - Michal Simek <michal.simek@amd.com>
> +
> +properties:
> +  $nodename:
> +    pattern: "^fpga-bridge(@.*)?$"
> +
> +  bridge-enable:
> +    description: |
> +      0 if driver should disable bridge at startup
> +      1 if driver should enable bridge at startup
> +      Default is to leave bridge in current state.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 0, 1 ]
> +
> +additionalProperties: true
> +
> +examples:
> +  - |
> +    fpga-bridge {
> +        bridge-enable = <0>;
> +    };
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml b/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml
> index a7d4b8e59e19..5bf731f9d99a 100644
> --- a/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml
> @@ -9,6 +9,9 @@ title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
>  maintainers:
>    - Nava kishore Manne <nava.kishore.manne@amd.com>
>  
> +allOf:
> +  - $ref: fpga-bridge.yaml#
> +
>  description: |
>    The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more
>    decouplers/fpga bridges. The controller can decouple/disable the bridges
> @@ -51,7 +54,7 @@ required:
>    - clocks
>    - clock-names
>  
> -additionalProperties: false
> +unevaluatedProperties: false
>  
>  examples:
>    - |
> -- 
> 2.36.1
> 
> 

Re: [PATCH 2/2] dt-bindings: fpga: altera: Convert bridge bindings to yaml

[Michal Simek]

On 1/8/24 08:46, Xu Yilun wrote:
> On Fri, Jan 05, 2024 at 05:04:31PM +0100, Michal Simek wrote:
>> Convert Altera's bridges to yaml with using fpga-bridge.yaml.
>>
>> Signed-off-by: Michal Simek <michal.simek@amd.com>
>> ---
>>
>>   .../fpga/altera-fpga2sdram-bridge.txt         | 13 ----
>>   .../fpga/altera-fpga2sdram-bridge.yaml        | 34 ++++++++++
>>   .../bindings/fpga/altera-freeze-bridge.txt    | 20 ------
>>   .../bindings/fpga/altera-freeze-bridge.yaml   | 41 ++++++++++++
>>   .../bindings/fpga/altera-hps2fpga-bridge.txt  | 36 -----------
>>   .../bindings/fpga/altera-hps2fpga-bridge.yaml | 63 +++++++++++++++++++
>>   6 files changed, 138 insertions(+), 69 deletions(-)
>>   delete mode 100644 Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
>>   create mode 100644 Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
>>   delete mode 100644 Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
>>   create mode 100644 Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml
>>   delete mode 100644 Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
>>   create mode 100644 Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
>> deleted file mode 100644
>> index 5dd0ff0f7b4e..000000000000
>> --- a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
>> +++ /dev/null
>> @@ -1,13 +0,0 @@
>> -Altera FPGA To SDRAM Bridge Driver
>> -
>> -Required properties:
>> -- compatible		: Should contain "altr,socfpga-fpga2sdram-bridge"
>> -
>> -See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
>> -
>> -Example:
>> -	fpga_bridge3: fpga-bridge@ffc25080 {
>> -		compatible = "altr,socfpga-fpga2sdram-bridge";
>> -		reg = <0xffc25080 0x4>;
>> -		bridge-enable = <0>;
>> -	};
>> diff --git a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
>> new file mode 100644
>> index 000000000000..a3f3fe2729f2
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
>> @@ -0,0 +1,34 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/fpga/altera-fpga2sdram-bridge.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Altera FPGA To SDRAM Bridge
>> +
>> +maintainers:
>> +  - Xu Yilun <yilun.xu@intel.com>
>> +
>> +allOf:
>> +  - $ref: fpga-bridge.yaml#
>> +
>> +properties:
>> +  compatible:
>> +    const: altr,socfpga-fpga2sdram-bridge
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
> 
> Is the 'reg' required? I didn't see it in original txt.

you tell me. It was in example that's why I made it mandatory.

> 
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> +  - |
>> +    fpga-bridge@ffc25080 {
>> +        compatible = "altr,socfpga-fpga2sdram-bridge";
>> +        reg = <0xffc25080 0x4>;
>> +        bridge-enable = <0>;
>> +    };
>> diff --git a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
>> deleted file mode 100644
>> index 8b26fbcff3c6..000000000000
>> --- a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
>> +++ /dev/null
>> @@ -1,20 +0,0 @@
>> -Altera Freeze Bridge Controller Driver
>> -
>> -The Altera Freeze Bridge Controller manages one or more freeze bridges.
>> -The controller can freeze/disable the bridges which prevents signal
>> -changes from passing through the bridge.  The controller can also
>> -unfreeze/enable the bridges which allows traffic to pass through the
>> -bridge normally.
>> -
>> -Required properties:
>> -- compatible		: Should contain "altr,freeze-bridge-controller"
>> -- regs			: base address and size for freeze bridge module
>> -
>> -See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
>> -
>> -Example:
>> -	freeze-controller@100000450 {
>> -		compatible = "altr,freeze-bridge-controller";
>> -		regs = <0x1000 0x10>;
>> -		bridge-enable = <0>;
>> -	};
>> diff --git a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml
>> new file mode 100644
>> index 000000000000..4a89e3980669
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml
>> @@ -0,0 +1,41 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/fpga/altera-freeze-bridge.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Altera Freeze Bridge Controller
>> +
>> +description: |
>> +  The Altera Freeze Bridge Controller manages one or more freeze bridges.
>> +  The controller can freeze/disable the bridges which prevents signal
>> +  changes from passing through the bridge. The controller can also
>> +  unfreeze/enable the bridges which allows traffic to pass through the bridge
>> +  normally.
>> +
>> +maintainers:
>> +  - Xu Yilun <yilun.xu@intel.com>
>> +
>> +allOf:
>> +  - $ref: fpga-bridge.yaml#
>> +
>> +properties:
>> +  compatible:
>> +    const: altr,freeze-bridge-controller
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> +  - |
>> +    fpga-bridge@100000450 {
>> +        compatible = "altr,freeze-bridge-controller";
>> +        reg = <0x1000 0x10>;
>> +        bridge-enable = <0>;
>> +    };
>> diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
>> deleted file mode 100644
>> index 68cce3945b10..000000000000
>> --- a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
>> +++ /dev/null
>> @@ -1,36 +0,0 @@
>> -Altera FPGA/HPS Bridge Driver
>> -
>> -Required properties:
>> -- regs		: base address and size for AXI bridge module
>> -- compatible	: Should contain one of:
>> -		  "altr,socfpga-lwhps2fpga-bridge",
>> -		  "altr,socfpga-hps2fpga-bridge", or
>> -		  "altr,socfpga-fpga2hps-bridge"
>> -- resets	: Phandle and reset specifier for this bridge's reset
>> -- clocks	: Clocks used by this module.
>> -
>> -See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
>> -
>> -Example:
>> -	fpga_bridge0: fpga-bridge@ff400000 {
>> -		compatible = "altr,socfpga-lwhps2fpga-bridge";
>> -		reg = <0xff400000 0x100000>;
>> -		resets = <&rst LWHPS2FPGA_RESET>;
>> -		clocks = <&l4_main_clk>;
>> -		bridge-enable = <0>;
>> -	};
>> -
>> -	fpga_bridge1: fpga-bridge@ff500000 {
>> -		compatible = "altr,socfpga-hps2fpga-bridge";
>> -		reg = <0xff500000 0x10000>;
>> -		resets = <&rst HPS2FPGA_RESET>;
>> -		clocks = <&l4_main_clk>;
>> -		bridge-enable = <1>;
>> -	};
>> -
>> -	fpga_bridge2: fpga-bridge@ff600000 {
>> -		compatible = "altr,socfpga-fpga2hps-bridge";
>> -		reg = <0xff600000 0x100000>;
>> -		resets = <&rst FPGA2HPS_RESET>;
>> -		clocks = <&l4_main_clk>;
>> -	};
>> diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml
>> new file mode 100644
>> index 000000000000..f8210449dfed
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml
>> @@ -0,0 +1,63 @@
> 
> Is the License identifier also needed?

yes it is. Will add in v2. Checkpatch didn't catch it. :-(

Thanks,
Michal

Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[Krzysztof Kozlowski]

On 05/01/2024 17:04, Michal Simek wrote:
> Convert the generic fpga bridge DT binding to json-schema.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>

> +$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: FPGA Bridge
> +
> +maintainers:
> +  - Michal Simek <michal.simek@amd.com>
> +
> +properties:
> +  $nodename:
> +    pattern: "^fpga-bridge(@.*)?$"

Not sure, but maybe we need to allow fpga-bridge-1? Could we have more
than one bridge on given system?

Anyway, looks fine:

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 2/2] dt-bindings: fpga: altera: Convert bridge bindings to yaml

[Krzysztof Kozlowski]

On 05/01/2024 17:04, Michal Simek wrote:
> Convert Altera's bridges to yaml with using fpga-bridge.yaml.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---

Thank you for your patch. There is something to discuss/improve.


> -Example:
> -	fpga_bridge3: fpga-bridge@ffc25080 {
> -		compatible = "altr,socfpga-fpga2sdram-bridge";
> -		reg = <0xffc25080 0x4>;
> -		bridge-enable = <0>;
> -	};
> diff --git a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
> new file mode 100644
> index 000000000000..a3f3fe2729f2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml

altr,socfpga-fpga2sdram-bridge.yaml

> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/altera-fpga2sdram-bridge.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera FPGA To SDRAM Bridge
> +
> +maintainers:
> +  - Xu Yilun <yilun.xu@intel.com>
> +
> +allOf:
> +  - $ref: fpga-bridge.yaml#
> +
> +properties:
> +  compatible:
> +    const: altr,socfpga-fpga2sdram-bridge
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    fpga-bridge@ffc25080 {
> +        compatible = "altr,socfpga-fpga2sdram-bridge";
> +        reg = <0xffc25080 0x4>;
> +        bridge-enable = <0>;
> +    };
> diff --git a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
> deleted file mode 100644
> index 8b26fbcff3c6..000000000000
> --- a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
> +++ /dev/null
> @@ -1,20 +0,0 @@
> -Altera Freeze Bridge Controller Driver
> -
> -The Altera Freeze Bridge Controller manages one or more freeze bridges.
> -The controller can freeze/disable the bridges which prevents signal
> -changes from passing through the bridge.  The controller can also
> -unfreeze/enable the bridges which allows traffic to pass through the
> -bridge normally.
> -
> -Required properties:
> -- compatible		: Should contain "altr,freeze-bridge-controller"
> -- regs			: base address and size for freeze bridge module
> -
> -See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
> -
> -Example:
> -	freeze-controller@100000450 {
> -		compatible = "altr,freeze-bridge-controller";
> -		regs = <0x1000 0x10>;
> -		bridge-enable = <0>;
> -	};
> diff --git a/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml
> new file mode 100644
> index 000000000000..4a89e3980669
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml


altr,freeze-bridge-controller.yaml

> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/altera-freeze-bridge.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera Freeze Bridge Controller
> +
> +description: |

Do not need '|' unless you need to preserve formatting.

> +  The Altera Freeze Bridge Controller manages one or more freeze bridges.
> +  The controller can freeze/disable the bridges which prevents signal
> +  changes from passing through the bridge. The controller can also
> +  unfreeze/enable the bridges which allows traffic to pass through the bridge
> +  normally.
> +
> +maintainers:
> +  - Xu Yilun <yilun.xu@intel.com>
> +
> +allOf:
> +  - $ref: fpga-bridge.yaml#
> +
> +properties:
> +  compatible:
> +    const: altr,freeze-bridge-controller
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    fpga-bridge@100000450 {
> +        compatible = "altr,freeze-bridge-controller";
> +        reg = <0x1000 0x10>;
> +        bridge-enable = <0>;
> +    };
> diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
> deleted file mode 100644
> index 68cce3945b10..000000000000
> --- a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -Altera FPGA/HPS Bridge Driver
> -
> -Required properties:
> -- regs		: base address and size for AXI bridge module
> -- compatible	: Should contain one of:
> -		  "altr,socfpga-lwhps2fpga-bridge",
> -		  "altr,socfpga-hps2fpga-bridge", or
> -		  "altr,socfpga-fpga2hps-bridge"
> -- resets	: Phandle and reset specifier for this bridge's reset
> -- clocks	: Clocks used by this module.
> -
> -See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
> -
> -Example:
> -	fpga_bridge0: fpga-bridge@ff400000 {
> -		compatible = "altr,socfpga-lwhps2fpga-bridge";
> -		reg = <0xff400000 0x100000>;
> -		resets = <&rst LWHPS2FPGA_RESET>;
> -		clocks = <&l4_main_clk>;
> -		bridge-enable = <0>;
> -	};
> -
> -	fpga_bridge1: fpga-bridge@ff500000 {
> -		compatible = "altr,socfpga-hps2fpga-bridge";
> -		reg = <0xff500000 0x10000>;
> -		resets = <&rst HPS2FPGA_RESET>;
> -		clocks = <&l4_main_clk>;
> -		bridge-enable = <1>;
> -	};
> -
> -	fpga_bridge2: fpga-bridge@ff600000 {
> -		compatible = "altr,socfpga-fpga2hps-bridge";
> -		reg = <0xff600000 0x100000>;
> -		resets = <&rst FPGA2HPS_RESET>;
> -		clocks = <&l4_main_clk>;
> -	};
> diff --git a/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml
> new file mode 100644
> index 000000000000..f8210449dfed
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml

altr,socfpga-hps2fpga-bridge.yaml

> @@ -0,0 +1,63 @@
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/altera-hps2fpga-bridge.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera FPGA/HPS Bridge
> +
> +maintainers:
> +  - Xu Yilun <yilun.xu@intel.com>
> +
> +allOf:
> +  - $ref: fpga-bridge.yaml#
> +
> +properties:
> +  compatible:
> +    enum:
> +      - altr,socfpga-lwhps2fpga-bridge
> +      - altr,socfpga-hps2fpga-bridge
> +      - altr,socfpga-fpga2hps-bridge
> +
> +  reg:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - resets
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/reset/altr,rst-mgr.h>
> +
> +    fpga-bridge@ff400000 {
> +      compatible = "altr,socfpga-lwhps2fpga-bridge";
> +      reg = <0xff400000 0x100000>;
> +      bridge-enable = <0>;
> +      clocks = <&l4_main_clk>;
> +      resets = <&rst LWHPS2FPGA_RESET>;
> +    };
> +
> +    fpga_bridge1: fpga-bridge@ff500000 {
> +      compatible = "altr,socfpga-hps2fpga-bridge";

Just keep one example. They are all "the same".

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[Michal Simek]

On 1/8/24 10:09, Krzysztof Kozlowski wrote:
> On 05/01/2024 17:04, Michal Simek wrote:
>> Convert the generic fpga bridge DT binding to json-schema.
>>
>> Signed-off-by: Michal Simek <michal.simek@amd.com>
> 
>> +$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: FPGA Bridge
>> +
>> +maintainers:
>> +  - Michal Simek <michal.simek@amd.com>
>> +
>> +properties:
>> +  $nodename:
>> +    pattern: "^fpga-bridge(@.*)?$"
> 
> Not sure, but maybe we need to allow fpga-bridge-1? Could we have more
> than one bridge on given system?

Yilun: Any comment on this?

> 
> Anyway, looks fine:
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Thanks,
Michal

Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[Xu Yilun]

On Mon, Jan 08, 2024 at 10:16:17AM +0100, Michal Simek wrote:
> 
> 
> On 1/8/24 10:09, Krzysztof Kozlowski wrote:
> > On 05/01/2024 17:04, Michal Simek wrote:
> > > Convert the generic fpga bridge DT binding to json-schema.
> > > 
> > > Signed-off-by: Michal Simek <michal.simek@amd.com>
> > 
> > > +$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: FPGA Bridge
> > > +
> > > +maintainers:
> > > +  - Michal Simek <michal.simek@amd.com>
> > > +
> > > +properties:
> > > +  $nodename:
> > > +    pattern: "^fpga-bridge(@.*)?$"
> > 
> > Not sure, but maybe we need to allow fpga-bridge-1? Could we have more
> > than one bridge on given system?
> 
> Yilun: Any comment on this?

We can have more bridges, but IIUC people use fpga-bridge@0, fpga-bridge@0
to identify them. So the expression is OK to me.

Thanks,
Yilun

> 
> > 
> > Anyway, looks fine:
> > 
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> Thanks,
> Michal
> 

Re: [PATCH 2/2] dt-bindings: fpga: altera: Convert bridge bindings to yaml

[Xu Yilun]

On Mon, Jan 08, 2024 at 09:12:21AM +0100, Michal Simek wrote:
> 
> 
> On 1/8/24 08:46, Xu Yilun wrote:
> > On Fri, Jan 05, 2024 at 05:04:31PM +0100, Michal Simek wrote:
> > > Convert Altera's bridges to yaml with using fpga-bridge.yaml.
> > > 
> > > Signed-off-by: Michal Simek <michal.simek@amd.com>
> > > ---
> > > 
> > >   .../fpga/altera-fpga2sdram-bridge.txt         | 13 ----
> > >   .../fpga/altera-fpga2sdram-bridge.yaml        | 34 ++++++++++
> > >   .../bindings/fpga/altera-freeze-bridge.txt    | 20 ------
> > >   .../bindings/fpga/altera-freeze-bridge.yaml   | 41 ++++++++++++
> > >   .../bindings/fpga/altera-hps2fpga-bridge.txt  | 36 -----------
> > >   .../bindings/fpga/altera-hps2fpga-bridge.yaml | 63 +++++++++++++++++++
> > >   6 files changed, 138 insertions(+), 69 deletions(-)
> > >   delete mode 100644 Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
> > >   create mode 100644 Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
> > >   delete mode 100644 Documentation/devicetree/bindings/fpga/altera-freeze-bridge.txt
> > >   create mode 100644 Documentation/devicetree/bindings/fpga/altera-freeze-bridge.yaml
> > >   delete mode 100644 Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
> > >   create mode 100644 Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.yaml
> > > 
> > > diff --git a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
> > > deleted file mode 100644
> > > index 5dd0ff0f7b4e..000000000000
> > > --- a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
> > > +++ /dev/null
> > > @@ -1,13 +0,0 @@
> > > -Altera FPGA To SDRAM Bridge Driver
> > > -
> > > -Required properties:
> > > -- compatible		: Should contain "altr,socfpga-fpga2sdram-bridge"
> > > -
> > > -See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
> > > -
> > > -Example:
> > > -	fpga_bridge3: fpga-bridge@ffc25080 {
> > > -		compatible = "altr,socfpga-fpga2sdram-bridge";
> > > -		reg = <0xffc25080 0x4>;
> > > -		bridge-enable = <0>;
> > > -	};
> > > diff --git a/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
> > > new file mode 100644
> > > index 000000000000..a3f3fe2729f2
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.yaml
> > > @@ -0,0 +1,34 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/fpga/altera-fpga2sdram-bridge.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Altera FPGA To SDRAM Bridge
> > > +
> > > +maintainers:
> > > +  - Xu Yilun <yilun.xu@intel.com>
> > > +
> > > +allOf:
> > > +  - $ref: fpga-bridge.yaml#
> > > +
> > > +properties:
> > > +  compatible:
> > > +    const: altr,socfpga-fpga2sdram-bridge
> > > +
> > > +  reg:
> > > +    maxItems: 1
> > > +
> > > +required:
> > > +  - compatible
> > > +  - reg
> > 
> > Is the 'reg' required? I didn't see it in original txt.
> 
> you tell me. It was in example that's why I made it mandatory.

In original txt, 'reg' is not listed as required but in Example. I
searched the code but didn't see 'reg' useful. So lets delete it
from 'required:'

Thanks,
Yilun

Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[Krzysztof Kozlowski]

On 09/01/2024 04:53, Xu Yilun wrote:
> On Mon, Jan 08, 2024 at 10:16:17AM +0100, Michal Simek wrote:
>>
>>
>> On 1/8/24 10:09, Krzysztof Kozlowski wrote:
>>> On 05/01/2024 17:04, Michal Simek wrote:
>>>> Convert the generic fpga bridge DT binding to json-schema.
>>>>
>>>> Signed-off-by: Michal Simek <michal.simek@amd.com>
>>>
>>>> +$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: FPGA Bridge
>>>> +
>>>> +maintainers:
>>>> +  - Michal Simek <michal.simek@amd.com>
>>>> +
>>>> +properties:
>>>> +  $nodename:
>>>> +    pattern: "^fpga-bridge(@.*)?$"
>>>
>>> Not sure, but maybe we need to allow fpga-bridge-1? Could we have more
>>> than one bridge on given system?
>>
>> Yilun: Any comment on this?
> 
> We can have more bridges, but IIUC people use fpga-bridge@0, fpga-bridge@0
> to identify them. So the expression is OK to me.

So you claim unit address thus reg with some sort of bus address is a
requirement? Then "?" is not correct in that pattern.

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[Michal Simek]

On 1/9/24 09:00, Krzysztof Kozlowski wrote:
> On 09/01/2024 04:53, Xu Yilun wrote:
>> On Mon, Jan 08, 2024 at 10:16:17AM +0100, Michal Simek wrote:
>>>
>>>
>>> On 1/8/24 10:09, Krzysztof Kozlowski wrote:
>>>> On 05/01/2024 17:04, Michal Simek wrote:
>>>>> Convert the generic fpga bridge DT binding to json-schema.
>>>>>
>>>>> Signed-off-by: Michal Simek <michal.simek@amd.com>
>>>>
>>>>> +$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: FPGA Bridge
>>>>> +
>>>>> +maintainers:
>>>>> +  - Michal Simek <michal.simek@amd.com>
>>>>> +
>>>>> +properties:
>>>>> +  $nodename:
>>>>> +    pattern: "^fpga-bridge(@.*)?$"
>>>>
>>>> Not sure, but maybe we need to allow fpga-bridge-1? Could we have more
>>>> than one bridge on given system?
>>>
>>> Yilun: Any comment on this?
>>
>> We can have more bridges, but IIUC people use fpga-bridge@0, fpga-bridge@0
>> to identify them. So the expression is OK to me.
> 
> So you claim unit address thus reg with some sort of bus address is a
> requirement? Then "?" is not correct in that pattern.

I expect it is about that people are using fpga-bridge@0 but bridge is not on 
the bus. Yilun said that reg property in altr,socfpga-fpga2sdram-bridge.yaml is 
optional which means no reg property no @XXX in node name.
That's why I think that expression is correct. If there are more bridges without 
reg property then I expect we need to get more examples to align expression.

Thanks,
Michal

Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[Krzysztof Kozlowski]

On 09/01/2024 09:06, Michal Simek wrote:
> 
> 
> On 1/9/24 09:00, Krzysztof Kozlowski wrote:
>> On 09/01/2024 04:53, Xu Yilun wrote:
>>> On Mon, Jan 08, 2024 at 10:16:17AM +0100, Michal Simek wrote:
>>>>
>>>>
>>>> On 1/8/24 10:09, Krzysztof Kozlowski wrote:
>>>>> On 05/01/2024 17:04, Michal Simek wrote:
>>>>>> Convert the generic fpga bridge DT binding to json-schema.
>>>>>>
>>>>>> Signed-off-by: Michal Simek <michal.simek@amd.com>
>>>>>
>>>>>> +$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>>> +
>>>>>> +title: FPGA Bridge
>>>>>> +
>>>>>> +maintainers:
>>>>>> +  - Michal Simek <michal.simek@amd.com>
>>>>>> +
>>>>>> +properties:
>>>>>> +  $nodename:
>>>>>> +    pattern: "^fpga-bridge(@.*)?$"
>>>>>
>>>>> Not sure, but maybe we need to allow fpga-bridge-1? Could we have more
>>>>> than one bridge on given system?
>>>>
>>>> Yilun: Any comment on this?
>>>
>>> We can have more bridges, but IIUC people use fpga-bridge@0, fpga-bridge@0
>>> to identify them. So the expression is OK to me.
>>
>> So you claim unit address thus reg with some sort of bus address is a
>> requirement? Then "?" is not correct in that pattern.
> 
> I expect it is about that people are using fpga-bridge@0 but bridge is not on 
> the bus. Yilun said that reg property in altr,socfpga-fpga2sdram-bridge.yaml is 
> optional which means no reg property no @XXX in node name.
> That's why I think that expression is correct. If there are more bridges without 
> reg property then I expect we need to get more examples to align expression.

If we allow node name without unit address, thus not being part of any
bus, then the only question is whether it is possible to have system
with more than two FPGA bridges. If the answer is "yes", which I think
is the case, then the pattern should already allow it:

(@[0-9a-f]+|-[0-9]+)?

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[Krzysztof Kozlowski]

On 09/01/2024 09:15, Krzysztof Kozlowski wrote:
>>>>>>> +properties:
>>>>>>> +  $nodename:
>>>>>>> +    pattern: "^fpga-bridge(@.*)?$"
>>>>>>
>>>>>> Not sure, but maybe we need to allow fpga-bridge-1? Could we have more
>>>>>> than one bridge on given system?
>>>>>
>>>>> Yilun: Any comment on this?
>>>>
>>>> We can have more bridges, but IIUC people use fpga-bridge@0, fpga-bridge@0
>>>> to identify them. So the expression is OK to me.
>>>
>>> So you claim unit address thus reg with some sort of bus address is a
>>> requirement? Then "?" is not correct in that pattern.
>>
>> I expect it is about that people are using fpga-bridge@0 but bridge is not on 
>> the bus. Yilun said that reg property in altr,socfpga-fpga2sdram-bridge.yaml is 
>> optional which means no reg property no @XXX in node name.
>> That's why I think that expression is correct. If there are more bridges without 
>> reg property then I expect we need to get more examples to align expression.
> 
> If we allow node name without unit address, thus not being part of any
> bus, then the only question is whether it is possible to have system
> with more than two FPGA bridges. If the answer is "yes", which I think
> is the case, then the pattern should already allow it:
> 
> (@[0-9a-f]+|-[0-9]+)?

Or better go with what I used recently for narrowed choices:

(@.*|-([0-9]|[1-9][0-9]+))?

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[Michal Simek]

On 1/9/24 09:15, Krzysztof Kozlowski wrote:
> On 09/01/2024 09:06, Michal Simek wrote:
>>
>>
>> On 1/9/24 09:00, Krzysztof Kozlowski wrote:
>>> On 09/01/2024 04:53, Xu Yilun wrote:
>>>> On Mon, Jan 08, 2024 at 10:16:17AM +0100, Michal Simek wrote:
>>>>>
>>>>>
>>>>> On 1/8/24 10:09, Krzysztof Kozlowski wrote:
>>>>>> On 05/01/2024 17:04, Michal Simek wrote:
>>>>>>> Convert the generic fpga bridge DT binding to json-schema.
>>>>>>>
>>>>>>> Signed-off-by: Michal Simek <michal.simek@amd.com>
>>>>>>
>>>>>>> +$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
>>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>>>> +
>>>>>>> +title: FPGA Bridge
>>>>>>> +
>>>>>>> +maintainers:
>>>>>>> +  - Michal Simek <michal.simek@amd.com>
>>>>>>> +
>>>>>>> +properties:
>>>>>>> +  $nodename:
>>>>>>> +    pattern: "^fpga-bridge(@.*)?$"
>>>>>>
>>>>>> Not sure, but maybe we need to allow fpga-bridge-1? Could we have more
>>>>>> than one bridge on given system?
>>>>>
>>>>> Yilun: Any comment on this?
>>>>
>>>> We can have more bridges, but IIUC people use fpga-bridge@0, fpga-bridge@0
>>>> to identify them. So the expression is OK to me.
>>>
>>> So you claim unit address thus reg with some sort of bus address is a
>>> requirement? Then "?" is not correct in that pattern.
>>
>> I expect it is about that people are using fpga-bridge@0 but bridge is not on
>> the bus. Yilun said that reg property in altr,socfpga-fpga2sdram-bridge.yaml is
>> optional which means no reg property no @XXX in node name.
>> That's why I think that expression is correct. If there are more bridges without
>> reg property then I expect we need to get more examples to align expression.
> 
> If we allow node name without unit address, thus not being part of any
> bus, then the only question is whether it is possible to have system
> with more than two FPGA bridges. If the answer is "yes", which I think
> is the case, then the pattern should already allow it:
> 
> (@[0-9a-f]+|-[0-9]+)?

Let's see what Yilun says. I am happy to align it. IIRC in our case bridge 
doesn't need to have reg interface because it can be handled via gpio.
You can have multiple of them but doesn't make sense to allocate multiple gpios 
to handle it because they can connected in a chain that one gpio drives all of 
them (And I don't think we have ever been requested to write a driver for it).

Thanks,
Michal

Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[Xu Yilun]

On Tue, Jan 09, 2024 at 09:16:33AM +0100, Krzysztof Kozlowski wrote:
> On 09/01/2024 09:15, Krzysztof Kozlowski wrote:
> >>>>>>> +properties:
> >>>>>>> +  $nodename:
> >>>>>>> +    pattern: "^fpga-bridge(@.*)?$"
> >>>>>>
> >>>>>> Not sure, but maybe we need to allow fpga-bridge-1? Could we have more
> >>>>>> than one bridge on given system?
> >>>>>
> >>>>> Yilun: Any comment on this?
> >>>>
> >>>> We can have more bridges, but IIUC people use fpga-bridge@0, fpga-bridge@0
> >>>> to identify them. So the expression is OK to me.
> >>>
> >>> So you claim unit address thus reg with some sort of bus address is a
> >>> requirement? Then "?" is not correct in that pattern.
> >>
> >> I expect it is about that people are using fpga-bridge@0 but bridge is not on 
> >> the bus. Yilun said that reg property in altr,socfpga-fpga2sdram-bridge.yaml is 
> >> optional which means no reg property no @XXX in node name.
> >> That's why I think that expression is correct. If there are more bridges without 
> >> reg property then I expect we need to get more examples to align expression.
> > 
> > If we allow node name without unit address, thus not being part of any

This is valid usecase.

> > bus, then the only question is whether it is possible to have system
> > with more than two FPGA bridges. If the answer is "yes", which I think

The answer is yes.

> > is the case, then the pattern should already allow it:
> > 
> > (@[0-9a-f]+|-[0-9]+)?
> 
> Or better go with what I used recently for narrowed choices:
> 
> (@.*|-([0-9]|[1-9][0-9]+))?

It is good to me.

I actually didn't know much about DTS & its Schema, thanks for all your
input.

> 
> Best regards,
> Krzysztof
> 
> 

Re: [PATCH 1/2] dt-bindings: fpga: Convert bridge binding to yaml

[Michal Simek]

On 1/9/24 11:22, Xu Yilun wrote:
> On Tue, Jan 09, 2024 at 09:16:33AM +0100, Krzysztof Kozlowski wrote:
>> On 09/01/2024 09:15, Krzysztof Kozlowski wrote:
>>>>>>>>> +properties:
>>>>>>>>> +  $nodename:
>>>>>>>>> +    pattern: "^fpga-bridge(@.*)?$"
>>>>>>>>
>>>>>>>> Not sure, but maybe we need to allow fpga-bridge-1? Could we have more
>>>>>>>> than one bridge on given system?
>>>>>>>
>>>>>>> Yilun: Any comment on this?
>>>>>>
>>>>>> We can have more bridges, but IIUC people use fpga-bridge@0, fpga-bridge@0
>>>>>> to identify them. So the expression is OK to me.
>>>>>
>>>>> So you claim unit address thus reg with some sort of bus address is a
>>>>> requirement? Then "?" is not correct in that pattern.
>>>>
>>>> I expect it is about that people are using fpga-bridge@0 but bridge is not on
>>>> the bus. Yilun said that reg property in altr,socfpga-fpga2sdram-bridge.yaml is
>>>> optional which means no reg property no @XXX in node name.
>>>> That's why I think that expression is correct. If there are more bridges without
>>>> reg property then I expect we need to get more examples to align expression.
>>>
>>> If we allow node name without unit address, thus not being part of any
> 
> This is valid usecase.
> 
>>> bus, then the only question is whether it is possible to have system
>>> with more than two FPGA bridges. If the answer is "yes", which I think
> 
> The answer is yes.
> 
>>> is the case, then the pattern should already allow it:
>>>
>>> (@[0-9a-f]+|-[0-9]+)?
>>
>> Or better go with what I used recently for narrowed choices:
>>
>> (@.*|-([0-9]|[1-9][0-9]+))?
> 
> It is good to me.
> 
> I actually didn't know much about DTS & its Schema, thanks for all your
> input.

Ok. Will send v3 with it.

Thanks,
Michal