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From: Russ Weight <russell.h.weight@intel.com>
To: Moritz Fischer <mdf@kernel.org>
Cc: lee.jones@linaro.org, linux-fpga@vger.kernel.org,
	linux-kernel@vger.kernel.org, trix@redhat.com,
	lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com,
	matthew.gerlach@intel.com
Subject: Re: [PATCH v5 3/6] fpga: m10bmc-sec: expose max10 flash update count
Date: Tue, 17 Nov 2020 15:45:27 -0800	[thread overview]
Message-ID: <d99a7077-18cc-f08a-b3a3-a66301cf814d@intel.com> (raw)
In-Reply-To: <20201115200330.GA284619@epycbox.lan>



On 11/15/20 12:03 PM, Moritz Fischer wrote:
> On Fri, Nov 13, 2020 at 04:55:56PM -0800, Russ Weight wrote:
>> Extend the MAX10 BMC Secure Update driver to provide a
>> sysfs file to expose the flash update count for the FPGA
>> user image.
>>
>> Signed-off-by: Russ Weight <russell.h.weight@intel.com>
>> Reviewed-by: Tom Rix <trix@redhat.com>
>> ---
>> v5:
>>   - Renamed sysfs node user_flash_count to flash_count and updated the
>>     sysfs documentation accordingly.
>> v4:
>>   - Moved the sysfs file for displaying the flash count from the
>>     FPGA Security Manager class driver to here. The
>>     m10bmc_user_flash_count() function is removed and the
>>     functionality is moved into a user_flash_count_show()
>>     function.
>>   - Added ABI documentation for the new sysfs entry
>> v3:
>>   - Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_
>>   - Changed "MAX10 BMC Secure Engine driver" to "MAX10 BMC Secure Update
>>     driver"
>>   - Removed wrapper functions (m10bmc_raw_*, m10bmc_sys_*). The
>>     underlying functions are now called directly.
>> v2:
>>   - Renamed get_qspi_flash_count() to m10bmc_user_flash_count()
>>   - Minor code cleanup per review comments
>>   - Added m10bmc_ prefix to functions in m10bmc_iops structure
>> ---
>>  .../testing/sysfs-driver-intel-m10-bmc-secure |  8 +++++
>>  drivers/fpga/intel-m10-bmc-secure.c           | 34 +++++++++++++++++++
>>  2 files changed, 42 insertions(+)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-secure b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-secure
>> index 2992488b717a..73a3aba750e8 100644
>> --- a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-secure
>> +++ b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-secure
>> @@ -27,3 +27,11 @@ Description:	Read only. Returns the root entry hash for the BMC image
>>  		"hash not programmed".  This file is only visible if the
>>  		underlying device supports it.
>>  		Format: "0x%x".
>> +
>> +What:		/sys/bus/platform/devices/n3000bmc-secure.*.auto/security/flash_count
>> +Date:		Oct 2020
>> +KernelVersion:  5.11
>> +Contact:	Russ Weight <russell.h.weight@intel.com>
>> +Description:	Read only. Returns number of times the secure update
>> +		staging area has been flashed.
>> +		Format: "%u".
>> diff --git a/drivers/fpga/intel-m10-bmc-secure.c b/drivers/fpga/intel-m10-bmc-secure.c
>> index 198bc8273d6b..6ad897001086 100644
>> --- a/drivers/fpga/intel-m10-bmc-secure.c
>> +++ b/drivers/fpga/intel-m10-bmc-secure.c
>> @@ -11,6 +11,7 @@
>>  #include <linux/mfd/intel-m10-bmc.h>
>>  #include <linux/module.h>
>>  #include <linux/platform_device.h>
>> +#include <linux/slab.h>
>>  
>>  struct m10bmc_sec {
>>  	struct device *dev;
>> @@ -77,7 +78,40 @@ DEVICE_ATTR_SEC_REH_RO(bmc, BMC_PROG_MAGIC, BMC_PROG_ADDR, BMC_REH_ADDR);
>>  DEVICE_ATTR_SEC_REH_RO(sr, SR_PROG_MAGIC, SR_PROG_ADDR, SR_REH_ADDR);
>>  DEVICE_ATTR_SEC_REH_RO(pr, PR_PROG_MAGIC, PR_PROG_ADDR, PR_REH_ADDR);
>>  
>> +#define FLASH_COUNT_SIZE 4096	/* count stored as inverted bit vector */
>> +
>> +static ssize_t flash_count_show(struct device *dev,
>> +				struct device_attribute *attr, char *buf)
>> +{
>> +	struct m10bmc_sec *sec = dev_get_drvdata(dev);
>> +	unsigned int stride = regmap_get_reg_stride(sec->m10bmc->regmap);
>> +	unsigned int num_bits = FLASH_COUNT_SIZE * 8;
>> +	u8 *flash_buf;
>> +	int cnt, ret;
> (Nit) Can you make this:
>
> 	struct m10bmc_sec *sec = dev_get_drvdata(dev);
> 	unsigned int stride, num_bits;
> 	u8 *flash_buf;
> 	int cnt, ret;
>
> 	stride = regmap_get_reg_stride(sec->m10bmc->regmap);
> 	num_bits = FLASH_COUNT_SIZE * 8;

Sure - I'll make the change. Thanks,

- Russ
>
>
>> +
>> +	flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL);
>> +	if (!flash_buf)
>> +		return -ENOMEM;
>> +
>> +	ret = regmap_bulk_read(sec->m10bmc->regmap, STAGING_FLASH_COUNT,
>> +			       flash_buf, FLASH_COUNT_SIZE / stride);
>> +	if (ret) {
>> +		dev_err(sec->dev,
>> +			"failed to read flash count: %x cnt %x: %d\n",
>> +			STAGING_FLASH_COUNT, FLASH_COUNT_SIZE / stride, ret);
>> +		goto exit_free;
>> +	}
>> +	cnt = num_bits - bitmap_weight((unsigned long *)flash_buf, num_bits);
>> +
>> +exit_free:
>> +	kfree(flash_buf);
>> +
>> +	return ret ? : sysfs_emit(buf, "%u\n", cnt);
>> +}
>> +static DEVICE_ATTR_RO(flash_count);
>> +
>>  static struct attribute *m10bmc_security_attrs[] = {
>> +	&dev_attr_flash_count.attr,
>>  	&dev_attr_bmc_root_entry_hash.attr,
>>  	&dev_attr_sr_root_entry_hash.attr,
>>  	&dev_attr_pr_root_entry_hash.attr,
>> -- 
>> 2.25.1
>>
> Otherwise looks good to me,
>
> - Moritz


  reply	other threads:[~2020-11-17 23:45 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-14  0:55 [PATCH v5 0/6] Intel MAX10 BMC Secure Update Driver Russ Weight
2020-11-14  0:55 ` [PATCH v5 1/6] mfd: intel-m10-bmc: support for MAX10 BMC Secure Updates Russ Weight
2020-11-14  0:55 ` [PATCH v5 2/6] fpga: m10bmc-sec: create max10 bmc secure update driver Russ Weight
2020-11-15 13:44   ` Tom Rix
2020-11-17 23:38     ` Russ Weight
2020-11-18 15:47       ` Tom Rix
2020-11-14  0:55 ` [PATCH v5 3/6] fpga: m10bmc-sec: expose max10 flash update count Russ Weight
2020-11-15 20:03   ` Moritz Fischer
2020-11-17 23:45     ` Russ Weight [this message]
2020-11-14  0:55 ` [PATCH v5 4/6] fpga: m10bmc-sec: expose max10 canceled keys in sysfs Russ Weight
2020-11-14  0:55 ` [PATCH v5 5/6] fpga: m10bmc-sec: add max10 secure update functions Russ Weight
2020-11-15 14:17   ` Tom Rix
2020-11-18  0:10     ` Russ Weight
2020-11-18 15:57       ` Tom Rix
2020-11-14  0:55 ` [PATCH v5 6/6] fpga: m10bmc-sec: add max10 get_hw_errinfo callback func Russ Weight
2020-11-15 14:20   ` Tom Rix
2020-11-18  0:16     ` Russ Weight

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