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[24.205.208.113]) by smtp.gmail.com with ESMTPSA id 6-20020ac85646000000b003a6947863e1sm11466198qtt.11.2022.12.29.07.31.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Dec 2022 07:31:49 -0800 (PST) Subject: Re: [PATCH v8 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 To: matthew.gerlach@linux.intel.com, hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de, ilpo.jarvinen@linux.intel.com, marpagan@redhat.com, bagasdotme@gmail.com References: <20221228181624.1793433-1-matthew.gerlach@linux.intel.com> <20221228181624.1793433-2-matthew.gerlach@linux.intel.com> From: Tom Rix Message-ID: Date: Thu, 29 Dec 2022 07:31:44 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <20221228181624.1793433-2-matthew.gerlach@linux.intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org On 12/28/22 10:16 AM, matthew.gerlach@linux.intel.com wrote: > From: Matthew Gerlach > > Add documentation describing the extensions provided by Version > 1 of the Device Feature Header (DFHv1). > > Signed-off-by: Matthew Gerlach > Reviewed-by: Ilpo Järvinen > --- > v8: fix section titles > > v7: shorten long lines and wording suggestions by bagasdotme@gmail.com > > v6: no change > > v5: use nested list for field descriptions > clean up prose > add reviewed-by and comments from Ilpo Järvinen > > v4: Remove marketing speak and separate v0 and v1 descriptions. > Fix errors reported by "make htmldocs". > > v3: no change > > v2: s/GUILD/GUID/ > add picture > --- > Documentation/fpga/dfl.rst | 112 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 112 insertions(+) > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > index 15b670926084..264b476fc6ac 100644 > --- a/Documentation/fpga/dfl.rst > +++ b/Documentation/fpga/dfl.rst > @@ -561,6 +561,118 @@ new DFL feature via UIO direct access, its feature id should be added to the > driver's id_table. > > I think a better location for this section would be in the beginning after the Device Feature List (DFL) Overview The reader will be looking for the details of the Header once they have read the overview. It would be handy if they were next > +Device Feature Header - Version 0 > +================================= > +Version 0 (DFHv0) is the original version of the Device Feature Header. > +The format of DFHv0 is shown below:: > + > + +-----------------------------------------------------------------------+ > + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| 0x00 > + +-----------------------------------------------------------------------+ > + |63 GUID_L 0| 0x08 > + +-----------------------------------------------------------------------+ > + |63 GUID_H 0| 0x10 > + +-----------------------------------------------------------------------+ > + > +- Offset 0x00 > + > + * Type - The type of DFH (e.g. FME, AFU, or private feature). > + * DFH VER - The version of the DFH. > + * Rsvd - Currently unused. > + * EOL - Set if the DFH is the end of the Device Feature List (DFL). > + * Next - The offset of the next DFH in the DFL from the DFH start. > + If EOL is set, Next is the size of MMIO of the last feature in the list. Missed describing feature revision bits 12-15 There as two VER's, it would be clearer if they were different. maybe REV for bits 12-15 Similar below. > + * ID - The feature ID if Type is private feature. > + > +- Offset 0x08 > + > + * GUID_L - Least significant 64 bits of a 128-bit Globally Unique Identifier > + (present only if Type is FME or AFU). > + > +- Offset 0x10 > + > + * GUID_H - Most significant 64 bits of a 128-bit Globally Unique Identifier > + (present only if Type is FME or AFU). > + > + > +Device Feature Header - Version 1 > +================================= > +Version 1 (DFHv1) of the Device Feature Header adds the following functionality: > + > +* Provides a standardized mechanism for features to describe > + parameters/capabilities to software. > +* Standardize the use of a GUID for all DFHv1 types. > +* Decouples the DFH location from the register space of the feature itself. > + > +The format of Version 1 of the Device Feature Header (DFH) is shown below:: > + > + +-----------------------------------------------------------------------+ > + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| 0x00 > + +-----------------------------------------------------------------------+ > + |63 GUID_L 0| 0x08 > + +-----------------------------------------------------------------------+ > + |63 GUID_H 0| 0x10 > + +-----------------------------------------------------------------------+ > + |63 Reg Address/Offset 1| Rel 0| 0x18 > + +-----------------------------------------------------------------------+ > + |63 Reg Size 32|Params 31|30 Group 16|15 Instance 0| 0x20 > + +-----------------------------------------------------------------------+ > + |63 Next 35|34RSV33|EOP32|31 Param Version 16|15 Param ID 0| 0x28 > + +-----------------------------------------------------------------------+ > + |63 Parameter Data 0| 0x30 > + +-----------------------------------------------------------------------+ > + > + ... > + > + +-----------------------------------------------------------------------+ > + |63 Next 35|34RSV33|EOP32|31 Param Version 16|15 Param ID 0| > + +-----------------------------------------------------------------------+ > + |63 Parameter Data 0| > + +-----------------------------------------------------------------------+ > + > +- Offset 0x00 > + > + * Type - The type of DFH (e.g. FME, AFU, or private feature). > + * DFH VER - The version of the DFH. > + * Rsvd - Currently unused. > + * EOL - Set if the DFH is the end of the Device Feature List (DFL). > + * Next - The offset of the next DFH in the DFL from the DFH start. > + If EOL is set, Next is the size of MMIO of the last feature in the list. Units of size ? Tom > + * ID - The feature ID if Type is private feature. > + > +- Offset 0x08 > + > + * GUID_L - Least significant 64 bits of a 128-bit Globally Unique Identifier. > + > +- Offset 0x10 > + > + * GUID_H - Most significant 64 bits of a 128-bit Globally Unique Identifier. > + > +- Offset 0x18 > + > + * Reg Address/Offset - If Rel bit is set, then the value is the high 63 bits > + of a 16-bit aligned absolute address of the feature's registers. Otherwise > + the value is the offset from the start of the DFH of the feature's registers. > + > +- Offset 0x20 > + > + * Reg Size - Size of feature's register set in bytes. > + * Params - Set if DFH has a list of parameter blocks. > + * Group - Id of group if feature is part of a group. > + * Instance - Id of feature instance within a group. > + > +- Offset 0x28 if feature has parameters > + > + * Next - Offset to the next parameter block in 8 byte words. If EOP set, > + size in 8 byte words of last parameter. > + * Param Version - Version of Param ID. > + * Param ID - ID of parameter. > + > +- Offset 0x30 > + > + * Parameter Data - Parameter data whose size and format is defined by > + version and ID of the parameter. > + > Open discussion > =============== > FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration