[PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver

[PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver

[iansdannapel]

From: Ian Dannapel <iansdannapel@gmail.com>

Add a new driver for loading binary firmware to volatile
configuration RAM using "SPI passive programming" on Efinix FPGAs.

Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
---
 drivers/fpga/Kconfig                    |  10 ++
 drivers/fpga/Makefile                   |   1 +
 drivers/fpga/efinix-trion-spi-passive.c | 211 ++++++++++++++++++++++++
 3 files changed, 222 insertions(+)
 create mode 100644 drivers/fpga/efinix-trion-spi-passive.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 37b35f58f0df..eb1e44c4e3e0 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -83,6 +83,16 @@ config FPGA_MGR_XILINX_SPI
 	  FPGA manager driver support for Xilinx FPGA configuration
 	  over slave serial interface.
 
+config FPGA_MGR_EFINIX_SPI
+	tristate "Efinix FPGA configuration over SPI passive"
+	depends on SPI
+	help
+	  This option enables support for the FPGA manager driver to
+	  configure Efinix Trion and Titanium Series FPGAs over SPI
+	  using passive serial mode.
+	  Warning: Do not activate this if there are other SPI devices
+	  on the same bus as it might interfere with the transmission.
+
 config FPGA_MGR_ICE40_SPI
 	tristate "Lattice iCE40 SPI"
 	depends on OF && SPI
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index aeb89bb13517..1a95124ff847 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
 obj-$(CONFIG_FPGA_MGR_XILINX_CORE)	+= xilinx-core.o
 obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP)	+= xilinx-selectmap.o
 obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
+obj-$(CONFIG_FPGA_MGR_EFINIX_SPI)	+= efinix-trion-spi-passive.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
 obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
 obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)	+= versal-fpga.o
diff --git a/drivers/fpga/efinix-trion-spi-passive.c b/drivers/fpga/efinix-trion-spi-passive.c
new file mode 100644
index 000000000000..87ff645265ca
--- /dev/null
+++ b/drivers/fpga/efinix-trion-spi-passive.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Trion and Titanium Series FPGA SPI Passive Programming Driver
+ *
+ * Copyright (C) 2024 iris-GmbH infrared & intelligent sensors
+ *
+ * Ian Dannapel <iansdannapel@gmail.com>
+ *
+ * Manage Efinix FPGA firmware that is loaded over SPI using
+ * the serial configuration interface.
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/spi/spi.h>
+#include <linux/sizes.h>
+
+struct efinix_spi_conf {
+	struct spi_device *spi;
+	struct gpio_desc *cdone;
+	struct gpio_desc *creset;
+	struct gpio_desc *cs;
+};
+
+static int efinix_spi_get_cdone_gpio(struct efinix_spi_conf *conf)
+{
+	int ret;
+
+	ret = gpiod_get_value(conf->cdone);
+	return ret;
+}
+
+static void efinix_spi_reset(struct efinix_spi_conf *conf)
+{
+	gpiod_set_value(conf->creset, 1);
+	/* wait tCRESET_N */
+	usleep_range(5, 15);
+	gpiod_set_value(conf->creset, 0);
+}
+
+static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr)
+{
+	struct efinix_spi_conf *conf = mgr->priv;
+
+	if (conf->cdone && efinix_spi_get_cdone_gpio(conf) == 1)
+		return FPGA_MGR_STATE_OPERATING;
+
+	return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int efinix_spi_apply_clk_cycles(struct efinix_spi_conf *conf)
+{
+	char data[13] = {0};
+
+	return spi_write(conf->spi, data, sizeof(data));
+}
+
+static int efinix_spi_write_init(struct fpga_manager *mgr,
+				 struct fpga_image_info *info,
+				 const char *buf, size_t count)
+{
+	struct efinix_spi_conf *conf = mgr->priv;
+
+	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
+		dev_err(&mgr->dev, "Partial reconfiguration not supported\n");
+		return -EINVAL;
+	}
+
+	/* reset with chip select active */
+	gpiod_set_value(conf->cs, 1);
+	usleep_range(5, 15);
+	efinix_spi_reset(conf);
+
+	/* wait tDMIN */
+	usleep_range(100, 150);
+
+	return 0;
+}
+
+static int efinix_spi_write(struct fpga_manager *mgr, const char *buf,
+			    size_t count)
+{
+	struct efinix_spi_conf *conf = mgr->priv;
+	int ret;
+
+	ret = spi_write(conf->spi, buf, count);
+	if (ret) {
+		dev_err(&mgr->dev, "SPI error in firmware write: %d\n",
+			ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int efinix_spi_write_complete(struct fpga_manager *mgr,
+				     struct fpga_image_info *info)
+{
+	struct efinix_spi_conf *conf = mgr->priv;
+	unsigned long timeout =
+		jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
+	bool expired = false;
+	int done;
+
+	/* append at least 100 clock cycles */
+	efinix_spi_apply_clk_cycles(conf);
+
+	/* release chip select */
+	gpiod_set_value(conf->cs, 0);
+
+	if (conf->cdone) {
+		while (!expired) {
+			expired = time_after(jiffies, timeout);
+
+			done = efinix_spi_get_cdone_gpio(conf);
+			if (done < 0)
+				return done;
+
+			if (done)
+				break;
+		}
+	}
+
+	if (expired)
+		return -ETIMEDOUT;
+
+	/* wait tUSER */
+	usleep_range(75, 125);
+
+	return 0;
+}
+
+static const struct fpga_manager_ops efinix_spi_ops = {
+	.state = efinix_spi_state,
+	.write_init = efinix_spi_write_init,
+	.write = efinix_spi_write,
+	.write_complete = efinix_spi_write_complete,
+};
+
+static int efinix_spi_probe(struct spi_device *spi)
+{
+	struct efinix_spi_conf *conf;
+	struct fpga_manager *mgr;
+
+	conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
+	if (!conf)
+		return -ENOMEM;
+
+	conf->spi = spi;
+
+	conf->creset = devm_gpiod_get(&spi->dev, "creset", GPIOD_OUT_HIGH);
+	if (IS_ERR(conf->creset))
+		return dev_err_probe(&spi->dev, PTR_ERR(conf->creset),
+				"Failed to get RESET gpio\n");
+
+	conf->cs = devm_gpiod_get(&spi->dev, "cs", GPIOD_OUT_HIGH);
+	if (IS_ERR(conf->cs))
+		return dev_err_probe(&spi->dev, PTR_ERR(conf->cs),
+				"Failed to get CHIP_SELECT gpio\n");
+
+	if (!(spi->mode & SPI_CPHA) || !(spi->mode & SPI_CPOL))
+		return dev_err_probe(&spi->dev, -EINVAL,
+				"Unsupported SPI mode, set CPHA and CPOL\n");
+
+	conf->cdone = devm_gpiod_get_optional(&spi->dev, "cdone", GPIOD_IN);
+	if (IS_ERR(conf->cdone))
+		return dev_err_probe(&spi->dev, PTR_ERR(conf->cdone),
+				"Failed to get CDONE gpio\n");
+
+	mgr = devm_fpga_mgr_register(&spi->dev,
+				"Efinix SPI Passive Programming FPGA Manager",
+					&efinix_spi_ops, conf);
+
+	return PTR_ERR_OR_ZERO(mgr);
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id efinix_spi_of_match[] = {
+	{ .compatible = "efinix,trion-spi-passive", },
+	{ .compatible = "efinix,titanium-spi-passive", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, efinix_spi_of_match);
+#endif
+
+static const struct spi_device_id efinix_ids[] = {
+	{ "trion-spi-passive", 0 },
+	{ "titanium-spi-passive", 0 },
+	{},
+};
+MODULE_DEVICE_TABLE(spi, efinix_ids);
+
+static struct spi_driver efinix_spi_passive_driver = {
+	.driver = {
+		.name = "efinix-fpga-spi-passive",
+		.of_match_table = of_match_ptr(efinix_spi_of_match),
+	},
+	.probe = efinix_spi_probe,
+	.id_table = efinix_ids,
+};
+
+module_spi_driver(efinix_spi_passive_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Ian Dannapel <iansdannapel@gmail.com>");
+MODULE_DESCRIPTION("Load Efinix FPGA firmware over SPI passive");
-- 
2.34.1

[PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings

[iansdannapel]

From: Ian Dannapel <iansdannapel@gmail.com>

Add device tree binding documentation for configuring Efinix FPGA
using serial SPI passive programming mode.

Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
---
 .../fpga/efinix,trion-spi-passive.yaml        | 85 +++++++++++++++++++
 1 file changed, 85 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml

diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
new file mode 100644
index 000000000000..ec6697fa6f44
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Efinix SPI FPGA Manager
+
+maintainers:
+  - Ian Dannapel <iansdannapel@gmail.com>
+
+description: |
+  Efinix Trion and Titanium Series FPGAs support a method of loading the
+  bitstream over what is referred to as "SPI Passive Programming".
+  Only serial (1x bus width) is supported, setting the programming mode
+  is not in the scope the this manager and must be done elsewhere.
+
+  Warning: The slave serial link is not technically SPI and therefore it is
+  not recommended to have other devices on the same bus since it might
+  interfere or be interfered by other transmissions.
+
+  References:
+  - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf
+  - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+  compatible:
+    enum:
+      - efinix,trion-spi-passive
+      - efinix,titanium-spi-passive
+
+  spi-cpha: true
+
+  spi-cpol: true
+
+  spi-max-frequency:
+    maximum: 25000000
+
+  reg:
+    maxItems: 1
+
+  creset-gpios:
+    description:
+      reset and re-configuration trigger pin (low active)
+    maxItems: 1
+
+  cs-gpios:
+    description:
+      chip-select pin (low active)
+    maxItems: 1
+
+  cdone-gpios:
+    description:
+      optional configuration done status pin (high active)
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - creset-gpios
+  - cs-gpios
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    spi {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      fpga-mgr@0 {
+        compatible = "efinix,trion-spi-passive";
+        reg = <0>;
+        spi-max-frequency = <25000000>;
+        spi-cpha;
+        spi-cpol;
+        creset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+        cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+        cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+      };
+    };
+...
-- 
2.34.1

[PATCH 3/3] dt-bindings: vendor-prefix: Add prefix for Efinix, Inc.

[iansdannapel]

From: Ian Dannapel <iansdannapel@gmail.com>

Add entry for Efinix, Inc. (https://www.efinixinc.com/)

Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index b320a39de7fe..cb92df951fa7 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -430,6 +430,8 @@ patternProperties:
     description: Emtop Embedded Solutions
   "^eeti,.*":
     description: eGalax_eMPIA Technology Inc
+  "^efinix,.*":
+    description: Efinix, Inc.
   "^einfochips,.*":
     description: Einfochips
   "^eink,.*":
-- 
2.34.1

[PATCH v3 0/3] Summary of changes

[iansdannapel]

Dear Linux FPGA Maintainers,

I did not found a way to use the struct spi_transfer to manage the chip
select the way this fpga programming requires. Since the chip select is 
managed by this driver alone, it may interfere with the communication 
with other devices on the bus, which I tried to make clear in the 
documentation.

Patch 1:
- improved kconfig help: added warning on spi interference
- fixed: efinix_spi_probe() warn: passing zero to 'PTR_ERR'
- improved function naming: efinix_spi_*()
- fixed: fpga_manager_ops.write could be called multiple times during 
one time reprogramming
[attached: v3-0001-fpga-Add-Efinix-Trion-Titanium-serial-SPI-program.patch]

Patch 2:
- added warning on spi interference
- removed unused label on example
[attached: v3-0003-dt-bindings-fpga-Add-Efinix-serial-SPI-programmin.patch]

Patch 3:
- no changes
[attached: v3-0003-dt-bindings-vendor-prefix-Add-prefix-for-Efinix-I.patch]

Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>

Re: [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver

[Krzysztof Kozlowski]

On 27/09/2024 16:14, iansdannapel@gmail.com wrote:
> From: Ian Dannapel <iansdannapel@gmail.com>
> 
> Add a new driver for loading binary firmware to volatile
> configuration RAM using "SPI passive programming" on Efinix FPGAs.
> 
> Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>

Thank you for your patch. There is something to discuss/improve.

> ---
>  drivers/fpga/Kconfig                    |  10 ++
>  drivers/fpga/Makefile                   |   1 +
>  drivers/fpga/efinix-trion-spi-passive.c | 211 ++++++++++++++++++++++++
>  3 files changed, 222 insertions(+)
>  create mode 100644 drivers/fpga/efinix-trion-spi-passive.c
> 
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 37b35f58f0df..eb1e44c4e3e0 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -83,6 +83,16 @@ config FPGA_MGR_XILINX_SPI
>  	  FPGA manager driver support for Xilinx FPGA configuration
>  	  over slave serial interface.
>  
> +config FPGA_MGR_EFINIX_SPI
> +	tristate "Efinix FPGA configuration over SPI passive"
> +	depends on SPI
> +	help
> +	  This option enables support for the FPGA manager driver to
> +	  configure Efinix Trion and Titanium Series FPGAs over SPI
> +	  using passive serial mode.
> +	  Warning: Do not activate this if there are other SPI devices
> +	  on the same bus as it might interfere with the transmission.
> +
>  config FPGA_MGR_ICE40_SPI
>  	tristate "Lattice iCE40 SPI"
>  	depends on OF && SPI
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index aeb89bb13517..1a95124ff847 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX)		+= ts73xx-fpga.o
>  obj-$(CONFIG_FPGA_MGR_XILINX_CORE)	+= xilinx-core.o
>  obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP)	+= xilinx-selectmap.o
>  obj-$(CONFIG_FPGA_MGR_XILINX_SPI)	+= xilinx-spi.o
> +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI)	+= efinix-trion-spi-passive.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)	+= zynq-fpga.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA)	+= zynqmp-fpga.o
>  obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA)	+= versal-fpga.o
> diff --git a/drivers/fpga/efinix-trion-spi-passive.c b/drivers/fpga/efinix-trion-spi-passive.c
> new file mode 100644
> index 000000000000..87ff645265ca
> --- /dev/null
> +++ b/drivers/fpga/efinix-trion-spi-passive.c
> @@ -0,0 +1,211 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Trion and Titanium Series FPGA SPI Passive Programming Driver
> + *
> + * Copyright (C) 2024 iris-GmbH infrared & intelligent sensors
> + *
> + * Ian Dannapel <iansdannapel@gmail.com>
> + *
> + * Manage Efinix FPGA firmware that is loaded over SPI using
> + * the serial configuration interface.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/fpga/fpga-mgr.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/of.h>
> +#include <linux/spi/spi.h>
> +#include <linux/sizes.h>
> +
> +struct efinix_spi_conf {
> +	struct spi_device *spi;
> +	struct gpio_desc *cdone;
> +	struct gpio_desc *creset;
> +	struct gpio_desc *cs;
> +};
> +
> +static int efinix_spi_get_cdone_gpio(struct efinix_spi_conf *conf)
> +{
> +	int ret;
> +
> +	ret = gpiod_get_value(conf->cdone);

This should be just return gpiod_get_value()... but then it's quite
simple wrapper, so just use it directly.

> +	return ret;
> +}
> +
> +static void efinix_spi_reset(struct efinix_spi_conf *conf)
> +{
> +	gpiod_set_value(conf->creset, 1);
> +	/* wait tCRESET_N */
> +	usleep_range(5, 15);
> +	gpiod_set_value(conf->creset, 0);
> +}
> +
> +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr)
> +{
> +	struct efinix_spi_conf *conf = mgr->priv;
> +
> +	if (conf->cdone && efinix_spi_get_cdone_gpio(conf) == 1)
> +		return FPGA_MGR_STATE_OPERATING;
> +
> +	return FPGA_MGR_STATE_UNKNOWN;
> +}
> +
> +static int efinix_spi_apply_clk_cycles(struct efinix_spi_conf *conf)
> +{
> +	char data[13] = {0};
> +
> +	return spi_write(conf->spi, data, sizeof(data));

Hm, aren't buffers from stack discouraged? spi-summary explicitly
mentions this case or I am getting this wrong?

> +}
> +
> +static int efinix_spi_write_init(struct fpga_manager *mgr,
> +				 struct fpga_image_info *info,
> +				 const char *buf, size_t count)
> +{
> +	struct efinix_spi_conf *conf = mgr->priv;
> +
> +	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
> +		dev_err(&mgr->dev, "Partial reconfiguration not supported\n");
> +		return -EINVAL;
> +	}
> +
> +	/* reset with chip select active */
> +	gpiod_set_value(conf->cs, 1);
> +	usleep_range(5, 15);
> +	efinix_spi_reset(conf);
> +
> +	/* wait tDMIN */
> +	usleep_range(100, 150);
> +
> +	return 0;
> +}
> +
> +static int efinix_spi_write(struct fpga_manager *mgr, const char *buf,
> +			    size_t count)
> +{
> +	struct efinix_spi_conf *conf = mgr->priv;
> +	int ret;
> +
> +	ret = spi_write(conf->spi, buf, count);
> +	if (ret) {
> +		dev_err(&mgr->dev, "SPI error in firmware write: %d\n",
> +			ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int efinix_spi_write_complete(struct fpga_manager *mgr,
> +				     struct fpga_image_info *info)
> +{
> +	struct efinix_spi_conf *conf = mgr->priv;
> +	unsigned long timeout =
> +		jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
> +	bool expired = false;
> +	int done;
> +
> +	/* append at least 100 clock cycles */
> +	efinix_spi_apply_clk_cycles(conf);
> +
> +	/* release chip select */
> +	gpiod_set_value(conf->cs, 0);
> +
> +	if (conf->cdone) {
> +		while (!expired) {
> +			expired = time_after(jiffies, timeout);
> +
> +			done = efinix_spi_get_cdone_gpio(conf);
> +			if (done < 0)
> +				return done;
> +
> +			if (done)
> +				break;
> +		}
> +	}
> +
> +	if (expired)
> +		return -ETIMEDOUT;
> +
> +	/* wait tUSER */
> +	usleep_range(75, 125);
> +
> +	return 0;
> +}
> +
> +static const struct fpga_manager_ops efinix_spi_ops = {
> +	.state = efinix_spi_state,
> +	.write_init = efinix_spi_write_init,
> +	.write = efinix_spi_write,
> +	.write_complete = efinix_spi_write_complete,
> +};
> +
> +static int efinix_spi_probe(struct spi_device *spi)
> +{
> +	struct efinix_spi_conf *conf;
> +	struct fpga_manager *mgr;
> +
> +	conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
> +	if (!conf)
> +		return -ENOMEM;
> +
> +	conf->spi = spi;
> +
> +	conf->creset = devm_gpiod_get(&spi->dev, "creset", GPIOD_OUT_HIGH);
> +	if (IS_ERR(conf->creset))
> +		return dev_err_probe(&spi->dev, PTR_ERR(conf->creset),
> +				"Failed to get RESET gpio\n");
> +
> +	conf->cs = devm_gpiod_get(&spi->dev, "cs", GPIOD_OUT_HIGH);
> +	if (IS_ERR(conf->cs))
> +		return dev_err_probe(&spi->dev, PTR_ERR(conf->cs),
> +				"Failed to get CHIP_SELECT gpio\n");
> +
> +	if (!(spi->mode & SPI_CPHA) || !(spi->mode & SPI_CPOL))
> +		return dev_err_probe(&spi->dev, -EINVAL,
> +				"Unsupported SPI mode, set CPHA and CPOL\n");
> +
> +	conf->cdone = devm_gpiod_get_optional(&spi->dev, "cdone", GPIOD_IN);
> +	if (IS_ERR(conf->cdone))
> +		return dev_err_probe(&spi->dev, PTR_ERR(conf->cdone),
> +				"Failed to get CDONE gpio\n");
> +
> +	mgr = devm_fpga_mgr_register(&spi->dev,
> +				"Efinix SPI Passive Programming FPGA Manager",
> +					&efinix_spi_ops, conf);
> +
> +	return PTR_ERR_OR_ZERO(mgr);
> +}
> +
> +#ifdef CONFIG_OF

Drop

> +static const struct of_device_id efinix_spi_of_match[] = {
> +	{ .compatible = "efinix,trion-spi-passive", },
> +	{ .compatible = "efinix,titanium-spi-passive", },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, efinix_spi_of_match);
> +#endif
> +
> +static const struct spi_device_id efinix_ids[] = {
> +	{ "trion-spi-passive", 0 },
> +	{ "titanium-spi-passive", 0 },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(spi, efinix_ids);
> +
> +static struct spi_driver efinix_spi_passive_driver = {
> +	.driver = {
> +		.name = "efinix-fpga-spi-passive",
> +		.of_match_table = of_match_ptr(efinix_spi_of_match),

Drop of_match_ptr


Best regards,
Krzysztof

Re: [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings

[Krzysztof Kozlowski]

On 27/09/2024 16:14, iansdannapel@gmail.com wrote:
> From: Ian Dannapel <iansdannapel@gmail.com>
> 
> Add device tree binding documentation for configuring Efinix FPGA
> using serial SPI passive programming mode.
> 
> Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
> ---
>  .../fpga/efinix,trion-spi-passive.yaml        | 85 +++++++++++++++++++
>  1 file changed, 85 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
> 
> diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
> new file mode 100644
> index 000000000000..ec6697fa6f44
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Efinix SPI FPGA Manager
> +
> +maintainers:
> +  - Ian Dannapel <iansdannapel@gmail.com>
> +
> +description: |
> +  Efinix Trion and Titanium Series FPGAs support a method of loading the
> +  bitstream over what is referred to as "SPI Passive Programming".
> +  Only serial (1x bus width) is supported, setting the programming mode
> +  is not in the scope the this manager and must be done elsewhere.
> +
> +  Warning: The slave serial link is not technically SPI and therefore it is
> +  not recommended to have other devices on the same bus since it might
> +  interfere or be interfered by other transmissions.
> +
> +  References:
> +  - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf
> +  - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf
> +
> +allOf:
> +  - $ref: /schemas/spi/spi-peripheral-props.yaml#
> +
> +properties:
> +  compatible:
> +    enum:
> +      - efinix,trion-spi-passive
> +      - efinix,titanium-spi-passive

1. Your driver suggests these are compatible, so make them compatible
with using fallback.

2. What is "spi-passive"? Compatible is supposed to be the name of the
device, so I assume this is "trion"? Can trion be anything else than fpga?

> +
> +  spi-cpha: true
> +
> +  spi-cpol: true
> +
> +  spi-max-frequency:
> +    maximum: 25000000
> +
> +  reg:
> +    maxItems: 1
> +
> +  creset-gpios:

reset-gpios

Do not invent own properties.

> +    description:
> +      reset and re-configuration trigger pin (low active)
> +    maxItems: 1
> +
> +  cs-gpios:
> +    description:
> +      chip-select pin (low active)

Eee? That's a property of controller, not child. Aren't you duplicating
existing controller property?

> +    maxItems: 1
> +
> +  cdone-gpios:
> +    description:
> +      optional configuration done status pin (high active)
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - creset-gpios
> +  - cs-gpios
> +
> +additionalProperties: false

unevaluatedProperties instead

> +



Best regards,
Krzysztof

Re: [PATCH 3/3] dt-bindings: vendor-prefix: Add prefix for Efinix, Inc.

[Krzysztof Kozlowski]

On 27/09/2024 16:14, iansdannapel@gmail.com wrote:
> From: Ian Dannapel <iansdannapel@gmail.com>
> 
> Add entry for Efinix, Inc. (https://www.efinixinc.com/)
> 
> Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Wrong order, this is supposed to be before first user.

BTW, same comment for device bindings - entire order is mixed up.
Bindings come before users.

Best regards,
Krzysztof

Re: [PATCH v3 0/3] Summary of changes

[Krzysztof Kozlowski]

On 27/09/2024 16:14, iansdannapel@gmail.com wrote:
> Dear Linux FPGA Maintainers,
> 
> I did not found a way to use the struct spi_transfer to manage the chip
> select the way this fpga programming requires. Since the chip select is 
> managed by this driver alone, it may interfere with the communication 
> with other devices on the bus, which I tried to make clear in 

Start using b4... or use proper --cover-letter argument for git
format-patch. Your patchset is not correctly threaded.

Best regards,
Krzysztof

Re: [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings

[Ian Dannapel]

Thanks for the review Krzysztof.

Am Fr., 27. Sept. 2024 um 16:26 Uhr schrieb Krzysztof Kozlowski
<krzk@kernel.org>:
>
> On 27/09/2024 16:14, iansdannapel@gmail.com wrote:
> > From: Ian Dannapel <iansdannapel@gmail.com>
> >
> > Add device tree binding documentation for configuring Efinix FPGA
> > using serial SPI passive programming mode.
> >
> > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
> > ---
> >  .../fpga/efinix,trion-spi-passive.yaml        | 85 +++++++++++++++++++
> >  1 file changed, 85 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
> > new file mode 100644
> > index 000000000000..ec6697fa6f44
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
> > @@ -0,0 +1,85 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Efinix SPI FPGA Manager
> > +
> > +maintainers:
> > +  - Ian Dannapel <iansdannapel@gmail.com>
> > +
> > +description: |
> > +  Efinix Trion and Titanium Series FPGAs support a method of loading the
> > +  bitstream over what is referred to as "SPI Passive Programming".
> > +  Only serial (1x bus width) is supported, setting the programming mode
> > +  is not in the scope the this manager and must be done elsewhere.
> > +
> > +  Warning: The slave serial link is not technically SPI and therefore it is
> > +  not recommended to have other devices on the same bus since it might
> > +  interfere or be interfered by other transmissions.
> > +
> > +  References:
> > +  - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf
> > +  - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf
> > +
> > +allOf:
> > +  - $ref: /schemas/spi/spi-peripheral-props.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - efinix,trion-spi-passive
> > +      - efinix,titanium-spi-passive
>
> 1. Your driver suggests these are compatible, so make them compatible
> with using fallback.
>
> 2. What is "spi-passive"? Compatible is supposed to be the name of the
> device, so I assume this is "trion"? Can trion be anything else than fpga?
spi-passive is the programming mode, where the device is in slave
mode. There are also other modes, but not supported by this driver.
The name was inspired by similar drivers (spi-xilinx.c). Isn't just
"efinix,trion"/"efinix,titanium" too generic?
>
> > +
> > +  spi-cpha: true
> > +
> > +  spi-cpol: true
> > +
> > +  spi-max-frequency:
> > +    maximum: 25000000
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  creset-gpios:
>
> reset-gpios
>
> Do not invent own properties.
>
> > +    description:
> > +      reset and re-configuration trigger pin (low active)
> > +    maxItems: 1
> > +
> > +  cs-gpios:
> > +    description:
> > +      chip-select pin (low active)
>
> Eee? That's a property of controller, not child. Aren't you duplicating
> existing controller property?
This device uses this pin in combination with the reset to enter the
programming mode. Also, the driver must guarantee that the pin is
active for the whole transfer process, including ending dummy bits.
This is why I added a warning to NOT use this driver with other
devices on the same bus.
>
> > +    maxItems: 1
> > +
> > +  cdone-gpios:
> > +    description:
> > +      optional configuration done status pin (high active)
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - creset-gpios
> > +  - cs-gpios
> > +
> > +additionalProperties: false
>
> unevaluatedProperties instead
>
> > +
>
>
>
> Best regards,
> Krzysztof
>

Best regards,
Ian

Re: [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings

[Krzysztof Kozlowski]

On 27/09/2024 17:34, Ian Dannapel wrote:
> Thanks for the review Krzysztof.
> 
> Am Fr., 27. Sept. 2024 um 16:26 Uhr schrieb Krzysztof Kozlowski
> <krzk@kernel.org>:
>>
>> On 27/09/2024 16:14, iansdannapel@gmail.com wrote:
>>> From: Ian Dannapel <iansdannapel@gmail.com>
>>>
>>> Add device tree binding documentation for configuring Efinix FPGA
>>> using serial SPI passive programming mode.
>>>
>>> Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
>>> ---
>>>  .../fpga/efinix,trion-spi-passive.yaml        | 85 +++++++++++++++++++
>>>  1 file changed, 85 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
>>> new file mode 100644
>>> index 000000000000..ec6697fa6f44
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
>>> @@ -0,0 +1,85 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Efinix SPI FPGA Manager
>>> +
>>> +maintainers:
>>> +  - Ian Dannapel <iansdannapel@gmail.com>
>>> +
>>> +description: |
>>> +  Efinix Trion and Titanium Series FPGAs support a method of loading the
>>> +  bitstream over what is referred to as "SPI Passive Programming".
>>> +  Only serial (1x bus width) is supported, setting the programming mode
>>> +  is not in the scope the this manager and must be done elsewhere.
>>> +
>>> +  Warning: The slave serial link is not technically SPI and therefore it is
>>> +  not recommended to have other devices on the same bus since it might
>>> +  interfere or be interfered by other transmissions.
>>> +
>>> +  References:
>>> +  - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf
>>> +  - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf
>>> +
>>> +allOf:
>>> +  - $ref: /schemas/spi/spi-peripheral-props.yaml#
>>> +
>>> +properties:
>>> +  compatible:
>>> +    enum:
>>> +      - efinix,trion-spi-passive
>>> +      - efinix,titanium-spi-passive
>>
>> 1. Your driver suggests these are compatible, so make them compatible
>> with using fallback.
>>
>> 2. What is "spi-passive"? Compatible is supposed to be the name of the
>> device, so I assume this is "trion"? Can trion be anything else than fpga?
> spi-passive is the programming mode, where the device is in slave
> mode. There are also other modes, but not supported by this driver.

But we do no describe here drivers, so it does no matter what it supports.

> The name was inspired by similar drivers (spi-xilinx.c). Isn't just
> "efinix,trion"/"efinix,titanium" too generic?

What do you mean too generic? What else could it be? BTW, that was my
question, which you did not answer. Bindings describe hardware, so
describe here hardware.

>>
>>> +
>>> +  spi-cpha: true
>>> +
>>> +  spi-cpol: true
>>> +
>>> +  spi-max-frequency:
>>> +    maximum: 25000000
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +  creset-gpios:
>>
>> reset-gpios
>>
>> Do not invent own properties.
>>
>>> +    description:
>>> +      reset and re-configuration trigger pin (low active)
>>> +    maxItems: 1
>>> +
>>> +  cs-gpios:
>>> +    description:
>>> +      chip-select pin (low active)
>>
>> Eee? That's a property of controller, not child. Aren't you duplicating
>> existing controller property?
> This device uses this pin in combination with the reset to enter the
> programming mode. Also, the driver must guarantee that the pin is

Isn't this the same on every SPI device?

> active for the whole transfer process, including ending dummy bits.
> This is why I added a warning to NOT use this driver with other
> devices on the same bus.

Not really related. None of this grants exception from duplicating
controller's property.

How do you think it will even work in Linux, if same GPIO is requested
twice (imagine controller also has it)? Till now, this would be -EBUSY.

But regardless of implementation, I still do not understand why do you
need duplicate same chip-select. Maybe just the naming is the confusion,
dunno.


Best regards,
Krzysztof

Re: [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings

[Ian Dannapel]

Am Sa., 28. Sept. 2024 um 09:31 Uhr schrieb Krzysztof Kozlowski
<krzk@kernel.org>:
>
> On 27/09/2024 17:34, Ian Dannapel wrote:
> > Thanks for the review Krzysztof.
> >
> > Am Fr., 27. Sept. 2024 um 16:26 Uhr schrieb Krzysztof Kozlowski
> > <krzk@kernel.org>:
> >>
> >> On 27/09/2024 16:14, iansdannapel@gmail.com wrote:
> >>> From: Ian Dannapel <iansdannapel@gmail.com>
> >>>
> >>> Add device tree binding documentation for configuring Efinix FPGA
> >>> using serial SPI passive programming mode.
> >>>
> >>> Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
> >>> ---
> >>>  .../fpga/efinix,trion-spi-passive.yaml        | 85 +++++++++++++++++++
> >>>  1 file changed, 85 insertions(+)
> >>>  create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
> >>> new file mode 100644
> >>> index 000000000000..ec6697fa6f44
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml
> >>> @@ -0,0 +1,85 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Efinix SPI FPGA Manager
> >>> +
> >>> +maintainers:
> >>> +  - Ian Dannapel <iansdannapel@gmail.com>
> >>> +
> >>> +description: |
> >>> +  Efinix Trion and Titanium Series FPGAs support a method of loading the
> >>> +  bitstream over what is referred to as "SPI Passive Programming".
> >>> +  Only serial (1x bus width) is supported, setting the programming mode
> >>> +  is not in the scope the this manager and must be done elsewhere.
> >>> +
> >>> +  Warning: The slave serial link is not technically SPI and therefore it is
> >>> +  not recommended to have other devices on the same bus since it might
> >>> +  interfere or be interfered by other transmissions.
> >>> +
> >>> +  References:
> >>> +  - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf
> >>> +  - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf
> >>> +
> >>> +allOf:
> >>> +  - $ref: /schemas/spi/spi-peripheral-props.yaml#
> >>> +
> >>> +properties:
> >>> +  compatible:
> >>> +    enum:
> >>> +      - efinix,trion-spi-passive
> >>> +      - efinix,titanium-spi-passive
> >>
> >> 1. Your driver suggests these are compatible, so make them compatible
> >> with using fallback.
> >>
> >> 2. What is "spi-passive"? Compatible is supposed to be the name of the
> >> device, so I assume this is "trion"? Can trion be anything else than fpga?
> > spi-passive is the programming mode, where the device is in slave
> > mode. There are also other modes, but not supported by this driver.
>
> But we do no describe here drivers, so it does no matter what it supports.
>
> > The name was inspired by similar drivers (spi-xilinx.c). Isn't just
> > "efinix,trion"/"efinix,titanium" too generic?
>
> What do you mean too generic? What else could it be? BTW, that was my
> question, which you did not answer. Bindings describe hardware, so
> describe here hardware.
>
> >>
> >>> +
> >>> +  spi-cpha: true
> >>> +
> >>> +  spi-cpol: true
> >>> +
> >>> +  spi-max-frequency:
> >>> +    maximum: 25000000
> >>> +
> >>> +  reg:
> >>> +    maxItems: 1
> >>> +
> >>> +  creset-gpios:
> >>
> >> reset-gpios
> >>
> >> Do not invent own properties.
> >>
> >>> +    description:
> >>> +      reset and re-configuration trigger pin (low active)
> >>> +    maxItems: 1
> >>> +
> >>> +  cs-gpios:
> >>> +    description:
> >>> +      chip-select pin (low active)
> >>
> >> Eee? That's a property of controller, not child. Aren't you duplicating
> >> existing controller property?
> > This device uses this pin in combination with the reset to enter the
> > programming mode. Also, the driver must guarantee that the pin is
>
> Isn't this the same on every SPI device?
Yes, but I was not very clear. In this case the pin must be hold
active including entering the programming mode. And if the controller
transfers the data in bursts, the pin is also not allowed to go
inactive between transfer bursts.
>
> > active for the whole transfer process, including ending dummy bits.
> > This is why I added a warning to NOT use this driver with other
> > devices on the same bus.
>
> Not really related. None of this grants exception from duplicating
> controller's property.
>
> How do you think it will even work in Linux, if same GPIO is requested
> twice (imagine controller also has it)? Till now, this would be -EBUSY.
I expected that the controller is not able request the same gpio. From
the controller point of view, it is a device that does not have a chip
select. Not sure if the controller would be able to get to this gpio
if it is not explicitly given.
>
> But regardless of implementation, I still do not understand why do you
> need duplicate same chip-select. Maybe just the naming is the confusion,
> dunno.
This could be an option to make the difference to a "real chip-select"
clear, but it would drift away from the datasheet naming. Eg,
prog-select?
>
>
> Best regards,
> Krzysztof
>

Regards,
Ian

Re: [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings

[Krzysztof Kozlowski]

On 28/09/2024 14:33, Ian Dannapel wrote:
>>>>
>>>>> +
>>>>> +  spi-cpha: true
>>>>> +
>>>>> +  spi-cpol: true
>>>>> +
>>>>> +  spi-max-frequency:
>>>>> +    maximum: 25000000
>>>>> +
>>>>> +  reg:
>>>>> +    maxItems: 1
>>>>> +
>>>>> +  creset-gpios:
>>>>
>>>> reset-gpios
>>>>
>>>> Do not invent own properties.
>>>>
>>>>> +    description:
>>>>> +      reset and re-configuration trigger pin (low active)
>>>>> +    maxItems: 1
>>>>> +
>>>>> +  cs-gpios:
>>>>> +    description:
>>>>> +      chip-select pin (low active)
>>>>
>>>> Eee? That's a property of controller, not child. Aren't you duplicating
>>>> existing controller property?
>>> This device uses this pin in combination with the reset to enter the
>>> programming mode. Also, the driver must guarantee that the pin is
>>
>> Isn't this the same on every SPI device?
> Yes, but I was not very clear. In this case the pin must be hold
> active including entering the programming mode. And if the controller

Just like every CS, no?

The only difference is that you must send entire programming sequence
without releasing the CS.

> transfers the data in bursts, the pin is also not allowed to go
> inactive between transfer bursts.
>>
>>> active for the whole transfer process, including ending dummy bits.
>>> This is why I added a warning to NOT use this driver with other
>>> devices on the same bus.
>>
>> Not really related. None of this grants exception from duplicating
>> controller's property.
>>
>> How do you think it will even work in Linux, if same GPIO is requested
>> twice (imagine controller also has it)? Till now, this would be -EBUSY.
> I expected that the controller is not able request the same gpio. From
> the controller point of view, it is a device that does not have a chip
> select. Not sure if the controller would be able to get to this gpio
> if it is not explicitly given.

But it could be given. Don't think only about your case.

Your description earlier clearly suggests it is CS. Description here
suggests it is not a CS.

No clue then.

>>
>> But regardless of implementation, I still do not understand why do you
>> need duplicate same chip-select. Maybe just the naming is the confusion,
>> dunno.
> This could be an option to make the difference to a "real chip-select"
> clear, but it would drift away from the datasheet naming. Eg,
> prog-select?

Please go back to datasheet. Which pin is this? CS, yes or not? If not,
then which other pin is CS?

Best regards,
Krzysztof

Re: [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings

[Ian Dannapel]

Am Sa., 28. Sept. 2024 um 14:53 Uhr schrieb Krzysztof Kozlowski
<krzk@kernel.org>:
>
> On 28/09/2024 14:33, Ian Dannapel wrote:
> >>>>
> >>>>> +
> >>>>> +  spi-cpha: true
> >>>>> +
> >>>>> +  spi-cpol: true
> >>>>> +
> >>>>> +  spi-max-frequency:
> >>>>> +    maximum: 25000000
> >>>>> +
> >>>>> +  reg:
> >>>>> +    maxItems: 1
> >>>>> +
> >>>>> +  creset-gpios:
> >>>>
> >>>> reset-gpios
> >>>>
> >>>> Do not invent own properties.
> >>>>
> >>>>> +    description:
> >>>>> +      reset and re-configuration trigger pin (low active)
> >>>>> +    maxItems: 1
> >>>>> +
> >>>>> +  cs-gpios:
> >>>>> +    description:
> >>>>> +      chip-select pin (low active)
> >>>>
> >>>> Eee? That's a property of controller, not child. Aren't you duplicating
> >>>> existing controller property?
> >>> This device uses this pin in combination with the reset to enter the
> >>> programming mode. Also, the driver must guarantee that the pin is
> >>
> >> Isn't this the same on every SPI device?
> > Yes, but I was not very clear. In this case the pin must be hold
> > active including entering the programming mode. And if the controller
>
> Just like every CS, no?
>
> The only difference is that you must send entire programming sequence
> without releasing the CS.
>
> > transfers the data in bursts, the pin is also not allowed to go
> > inactive between transfer bursts.
> >>
> >>> active for the whole transfer process, including ending dummy bits.
> >>> This is why I added a warning to NOT use this driver with other
> >>> devices on the same bus.
> >>
> >> Not really related. None of this grants exception from duplicating
> >> controller's property.
> >>
> >> How do you think it will even work in Linux, if same GPIO is requested
> >> twice (imagine controller also has it)? Till now, this would be -EBUSY.
> > I expected that the controller is not able request the same gpio. From
> > the controller point of view, it is a device that does not have a chip
> > select. Not sure if the controller would be able to get to this gpio
> > if it is not explicitly given.
>
> But it could be given. Don't think only about your case.
it won't work if the controller also may request this gpio or interfere with it.
>
> Your description earlier clearly suggests it is CS. Description here
> suggests it is not a CS.
>
> No clue then.
>
> >>
> >> But regardless of implementation, I still do not understand why do you
> >> need duplicate same chip-select. Maybe just the naming is the confusion,
> >> dunno.
> > This could be an option to make the difference to a "real chip-select"
> > clear, but it would drift away from the datasheet naming. Eg,
> > prog-select?
>
> Please go back to datasheet. Which pin is this? CS, yes or not? If not,
> then which other pin is CS?
Yes, this pin in question is referred to as the Chip Select (CS) or
Slave Select in the datasheet and pinout.
It is used in combination with the reset for entering the programming
mode and then used for the SPI data transfer to the FPGA’s volatile
configuration RAM.
There must be no state change on this CS pin between entering
programming mode and the completion of the SPI transfer.
Since the controller chip-select functionality can't fulfill these
requirements for this device, the proposed solution is to move this
pin from the controller to the child driver.
>
> Best regards,
> Krzysztof
>
Best regards
Ian

Re: [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings

[Krzysztof Kozlowski]

On Sat, Sep 28, 2024 at 04:26:03PM +0200, Ian Dannapel wrote:
> Am Sa., 28. Sept. 2024 um 14:53 Uhr schrieb Krzysztof Kozlowski
> <krzk@kernel.org>:
> >
> > On 28/09/2024 14:33, Ian Dannapel wrote:
> > >>>>
> > >>>>> +
> > >>>>> +  spi-cpha: true
> > >>>>> +
> > >>>>> +  spi-cpol: true
> > >>>>> +
> > >>>>> +  spi-max-frequency:
> > >>>>> +    maximum: 25000000
> > >>>>> +
> > >>>>> +  reg:
> > >>>>> +    maxItems: 1
> > >>>>> +
> > >>>>> +  creset-gpios:
> > >>>>
> > >>>> reset-gpios
> > >>>>
> > >>>> Do not invent own properties.
> > >>>>
> > >>>>> +    description:
> > >>>>> +      reset and re-configuration trigger pin (low active)
> > >>>>> +    maxItems: 1
> > >>>>> +
> > >>>>> +  cs-gpios:
> > >>>>> +    description:
> > >>>>> +      chip-select pin (low active)
> > >>>>
> > >>>> Eee? That's a property of controller, not child. Aren't you duplicating
> > >>>> existing controller property?
> > >>> This device uses this pin in combination with the reset to enter the
> > >>> programming mode. Also, the driver must guarantee that the pin is
> > >>
> > >> Isn't this the same on every SPI device?
> > > Yes, but I was not very clear. In this case the pin must be hold
> > > active including entering the programming mode. And if the controller
> >
> > Just like every CS, no?
> >
> > The only difference is that you must send entire programming sequence
> > without releasing the CS.
> >
> > > transfers the data in bursts, the pin is also not allowed to go
> > > inactive between transfer bursts.
> > >>
> > >>> active for the whole transfer process, including ending dummy bits.
> > >>> This is why I added a warning to NOT use this driver with other
> > >>> devices on the same bus.
> > >>
> > >> Not really related. None of this grants exception from duplicating
> > >> controller's property.
> > >>
> > >> How do you think it will even work in Linux, if same GPIO is requested
> > >> twice (imagine controller also has it)? Till now, this would be -EBUSY.
> > > I expected that the controller is not able request the same gpio. From
> > > the controller point of view, it is a device that does not have a chip
> > > select. Not sure if the controller would be able to get to this gpio
> > > if it is not explicitly given.
> >
> > But it could be given. Don't think only about your case.
> it won't work if the controller also may request this gpio or interfere with it.

Then your binding is incomplete, I would say. What stops anyone from
providing the same GPIO for CS in controller node, like typical bindings
expect?

> >
> > Your description earlier clearly suggests it is CS. Description here
> > suggests it is not a CS.
> >
> > No clue then.
> >
> > >>
> > >> But regardless of implementation, I still do not understand why do you
> > >> need duplicate same chip-select. Maybe just the naming is the confusion,
> > >> dunno.
> > > This could be an option to make the difference to a "real chip-select"
> > > clear, but it would drift away from the datasheet naming. Eg,
> > > prog-select?
> >
> > Please go back to datasheet. Which pin is this? CS, yes or not? If not,
> > then which other pin is CS?
> Yes, this pin in question is referred to as the Chip Select (CS) or
> Slave Select in the datasheet and pinout.
> It is used in combination with the reset for entering the programming
> mode and then used for the SPI data transfer to the FPGA’s volatile
> configuration RAM.
> There must be no state change on this CS pin between entering
> programming mode and the completion of the SPI transfer.

You just described CS gpio in parent controller node.

> Since the controller chip-select functionality can't fulfill these
> requirements for this device, the proposed solution is to move this
> pin from the controller to the child driver.

You mix two different things. Where the property should be described and
how it should be handled. child driver is not the matter of bindings.

Best regards,
Krzysztof

Re: [PATCH 3/3] dt-bindings: vendor-prefix: Add prefix for Efinix, Inc.

[Alexander Dahl]

Hello Ian,

Am Fri, Sep 27, 2024 at 04:14:44PM +0200 schrieb iansdannapel@gmail.com:
> From: Ian Dannapel <iansdannapel@gmail.com>
> 
> Add entry for Efinix, Inc. (https://www.efinixinc.com/)
> 
> Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index b320a39de7fe..cb92df951fa7 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -430,6 +430,8 @@ patternProperties:
>      description: Emtop Embedded Solutions
>    "^eeti,.*":
>      description: eGalax_eMPIA Technology Inc
> +  "^efinix,.*":
> +    description: Efinix, Inc.
>    "^einfochips,.*":
>      description: Einfochips
>    "^eink,.*":

Acked-by: Alexander Dahl <ada@thorsis.com>

Greets
Alex

Re: [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver

[Xu Yilun]

> > +static int efinix_spi_apply_clk_cycles(struct efinix_spi_conf *conf)
> > +{
> > +	char data[13] = {0};
> > +
> > +	return spi_write(conf->spi, data, sizeof(data));
> 
> Hm, aren't buffers from stack discouraged? spi-summary explicitly
> mentions this case or I am getting this wrong?

You are right. And there were already some fixes for this issue in FPGA. E.g.

https://lore.kernel.org/all/20221230092922.18822-2-i.bornyakov@metrotek.ru/

Thanks,
Yilun

Re: [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver

[Xu Yilun]

On Fri, Sep 27, 2024 at 04:14:42PM +0200, iansdannapel@gmail.com wrote:
> From: Ian Dannapel <iansdannapel@gmail.com>
> 
> Add a new driver for loading binary firmware to volatile
> configuration RAM using "SPI passive programming" on Efinix FPGAs.
> 
> Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
> ---
>  drivers/fpga/Kconfig                    |  10 ++
>  drivers/fpga/Makefile                   |   1 +
>  drivers/fpga/efinix-trion-spi-passive.c | 211 ++++++++++++++++++++++++
>  3 files changed, 222 insertions(+)
>  create mode 100644 drivers/fpga/efinix-trion-spi-passive.c
> 
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 37b35f58f0df..eb1e44c4e3e0 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -83,6 +83,16 @@ config FPGA_MGR_XILINX_SPI
>  	  FPGA manager driver support for Xilinx FPGA configuration
>  	  over slave serial interface.
>  
> +config FPGA_MGR_EFINIX_SPI
> +	tristate "Efinix FPGA configuration over SPI passive"
> +	depends on SPI
> +	help
> +	  This option enables support for the FPGA manager driver to
> +	  configure Efinix Trion and Titanium Series FPGAs over SPI
> +	  using passive serial mode.
> +	  Warning: Do not activate this if there are other SPI devices
> +	  on the same bus as it might interfere with the transmission.

Sorry, this won't work. As you can see, the conflict usage of CS causes
several concerns. Just a text here is far from enough.

You need to actively work with SPI core/controller drivers to find a
solution that coordinate the usage of this pin.

Thanks
Yilun

Re: [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2031 bytes --]

On Fri, Oct 18, 2024 at 09:37:22AM +0800, Xu Yilun wrote:
> On Fri, Sep 27, 2024 at 04:14:42PM +0200, iansdannapel@gmail.com wrote:
> > From: Ian Dannapel <iansdannapel@gmail.com>
> > 
> > Add a new driver for loading binary firmware to volatile
> > configuration RAM using "SPI passive programming" on Efinix FPGAs.
> > 
> > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
> > ---
> >  drivers/fpga/Kconfig                    |  10 ++
> >  drivers/fpga/Makefile                   |   1 +
> >  drivers/fpga/efinix-trion-spi-passive.c | 211 ++++++++++++++++++++++++
> >  3 files changed, 222 insertions(+)
> >  create mode 100644 drivers/fpga/efinix-trion-spi-passive.c
> > 
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > index 37b35f58f0df..eb1e44c4e3e0 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -83,6 +83,16 @@ config FPGA_MGR_XILINX_SPI
> >  	  FPGA manager driver support for Xilinx FPGA configuration
> >  	  over slave serial interface.
> >  
> > +config FPGA_MGR_EFINIX_SPI
> > +	tristate "Efinix FPGA configuration over SPI passive"
> > +	depends on SPI
> > +	help
> > +	  This option enables support for the FPGA manager driver to
> > +	  configure Efinix Trion and Titanium Series FPGAs over SPI
> > +	  using passive serial mode.
> > +	  Warning: Do not activate this if there are other SPI devices
> > +	  on the same bus as it might interfere with the transmission.
> 
> Sorry, this won't work. As you can see, the conflict usage of CS causes
> several concerns. Just a text here is far from enough.
> 
> You need to actively work with SPI core/controller drivers to find a
> solution that coordinate the usage of this pin.

Why does it even impact other SPI devices on the bus? It's not /their/
CS line that is being modified here, it is the line for the FPGA's
programming interface, right?
What am I missing here that makes it any different to any other SPI
device that may need it's CS toggled?

Cheers,
Conor.

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Re: [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver

[Xu Yilun]

On Fri, Oct 18, 2024 at 05:58:44PM +0100, Conor Dooley wrote:
> On Fri, Oct 18, 2024 at 09:37:22AM +0800, Xu Yilun wrote:
> > On Fri, Sep 27, 2024 at 04:14:42PM +0200, iansdannapel@gmail.com wrote:
> > > From: Ian Dannapel <iansdannapel@gmail.com>
> > > 
> > > Add a new driver for loading binary firmware to volatile
> > > configuration RAM using "SPI passive programming" on Efinix FPGAs.
> > > 
> > > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
> > > ---
> > >  drivers/fpga/Kconfig                    |  10 ++
> > >  drivers/fpga/Makefile                   |   1 +
> > >  drivers/fpga/efinix-trion-spi-passive.c | 211 ++++++++++++++++++++++++
> > >  3 files changed, 222 insertions(+)
> > >  create mode 100644 drivers/fpga/efinix-trion-spi-passive.c
> > > 
> > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > index 37b35f58f0df..eb1e44c4e3e0 100644
> > > --- a/drivers/fpga/Kconfig
> > > +++ b/drivers/fpga/Kconfig
> > > @@ -83,6 +83,16 @@ config FPGA_MGR_XILINX_SPI
> > >  	  FPGA manager driver support for Xilinx FPGA configuration
> > >  	  over slave serial interface.
> > >  
> > > +config FPGA_MGR_EFINIX_SPI
> > > +	tristate "Efinix FPGA configuration over SPI passive"
> > > +	depends on SPI
> > > +	help
> > > +	  This option enables support for the FPGA manager driver to
> > > +	  configure Efinix Trion and Titanium Series FPGAs over SPI
> > > +	  using passive serial mode.
> > > +	  Warning: Do not activate this if there are other SPI devices
> > > +	  on the same bus as it might interfere with the transmission.
> > 
> > Sorry, this won't work. As you can see, the conflict usage of CS causes
> > several concerns. Just a text here is far from enough.
> > 
> > You need to actively work with SPI core/controller drivers to find a
> > solution that coordinate the usage of this pin.
> 
> Why does it even impact other SPI devices on the bus? It's not /their/
> CS line that is being modified here, it is the line for the FPGA's
> programming interface, right?
> What am I missing here that makes it any different to any other SPI
> device that may need it's CS toggled?

IIUC, now spi core or controller driver should fully responsible for
HW operations of CS. And every good behaved spi device driver should
declare their logical CS index defined by SPI controller and let SPI
core/controller driver to proxy the CS change.

But if this spi device driver directly aquires CS, it conflicts with
the controller and just fails.

Thanks,
Yilun

> 
> Cheers,
> Conor.

Re: [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3049 bytes --]

On Mon, Oct 21, 2024 at 10:10:20AM +0800, Xu Yilun wrote:
> On Fri, Oct 18, 2024 at 05:58:44PM +0100, Conor Dooley wrote:
> > On Fri, Oct 18, 2024 at 09:37:22AM +0800, Xu Yilun wrote:
> > > On Fri, Sep 27, 2024 at 04:14:42PM +0200, iansdannapel@gmail.com wrote:
> > > > From: Ian Dannapel <iansdannapel@gmail.com>
> > > > 
> > > > Add a new driver for loading binary firmware to volatile
> > > > configuration RAM using "SPI passive programming" on Efinix FPGAs.
> > > > 
> > > > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
> > > > ---
> > > >  drivers/fpga/Kconfig                    |  10 ++
> > > >  drivers/fpga/Makefile                   |   1 +
> > > >  drivers/fpga/efinix-trion-spi-passive.c | 211 ++++++++++++++++++++++++
> > > >  3 files changed, 222 insertions(+)
> > > >  create mode 100644 drivers/fpga/efinix-trion-spi-passive.c
> > > > 
> > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > index 37b35f58f0df..eb1e44c4e3e0 100644
> > > > --- a/drivers/fpga/Kconfig
> > > > +++ b/drivers/fpga/Kconfig
> > > > @@ -83,6 +83,16 @@ config FPGA_MGR_XILINX_SPI
> > > >  	  FPGA manager driver support for Xilinx FPGA configuration
> > > >  	  over slave serial interface.
> > > >  
> > > > +config FPGA_MGR_EFINIX_SPI
> > > > +	tristate "Efinix FPGA configuration over SPI passive"
> > > > +	depends on SPI
> > > > +	help
> > > > +	  This option enables support for the FPGA manager driver to
> > > > +	  configure Efinix Trion and Titanium Series FPGAs over SPI
> > > > +	  using passive serial mode.
> > > > +	  Warning: Do not activate this if there are other SPI devices
> > > > +	  on the same bus as it might interfere with the transmission.
> > > 
> > > Sorry, this won't work. As you can see, the conflict usage of CS causes
> > > several concerns. Just a text here is far from enough.
> > > 
> > > You need to actively work with SPI core/controller drivers to find a
> > > solution that coordinate the usage of this pin.
> > 
> > Why does it even impact other SPI devices on the bus? It's not /their/
> > CS line that is being modified here, it is the line for the FPGA's
> > programming interface, right?
> > What am I missing here that makes it any different to any other SPI
> > device that may need it's CS toggled?
> 
> IIUC, now spi core or controller driver should fully responsible for
> HW operations of CS. And every good behaved spi device driver should
> declare their logical CS index defined by SPI controller and let SPI
> core/controller driver to proxy the CS change.
> 
> But if this spi device driver directly aquires CS, it conflicts with
> the controller and just fails.

Right, I don't think you answered my question here at all, but just
reading over the kconfig text again I think I understand what it means.
I'd interpreted this as other devices being impacted by what this driver
is doing, but actually it is talking about other devices on the bus
interfering with this one because of how it handles the chip select.

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Re: [PATCH 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver

[Ian Dannapel]

Am Mo., 21. Okt. 2024 um 14:18 Uhr schrieb Conor Dooley <conor@kernel.org>:
>
> On Mon, Oct 21, 2024 at 10:10:20AM +0800, Xu Yilun wrote:
> > On Fri, Oct 18, 2024 at 05:58:44PM +0100, Conor Dooley wrote:
> > > On Fri, Oct 18, 2024 at 09:37:22AM +0800, Xu Yilun wrote:
> > > > On Fri, Sep 27, 2024 at 04:14:42PM +0200, iansdannapel@gmail.com wrote:
> > > > > From: Ian Dannapel <iansdannapel@gmail.com>
> > > > >
> > > > > Add a new driver for loading binary firmware to volatile
> > > > > configuration RAM using "SPI passive programming" on Efinix FPGAs.
> > > > >
> > > > > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com>
> > > > > ---
> > > > >  drivers/fpga/Kconfig                    |  10 ++
> > > > >  drivers/fpga/Makefile                   |   1 +
> > > > >  drivers/fpga/efinix-trion-spi-passive.c | 211 ++++++++++++++++++++++++
> > > > >  3 files changed, 222 insertions(+)
> > > > >  create mode 100644 drivers/fpga/efinix-trion-spi-passive.c
> > > > >
> > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > index 37b35f58f0df..eb1e44c4e3e0 100644
> > > > > --- a/drivers/fpga/Kconfig
> > > > > +++ b/drivers/fpga/Kconfig
> > > > > @@ -83,6 +83,16 @@ config FPGA_MGR_XILINX_SPI
> > > > >           FPGA manager driver support for Xilinx FPGA configuration
> > > > >           over slave serial interface.
> > > > >
> > > > > +config FPGA_MGR_EFINIX_SPI
> > > > > +       tristate "Efinix FPGA configuration over SPI passive"
> > > > > +       depends on SPI
> > > > > +       help
> > > > > +         This option enables support for the FPGA manager driver to
> > > > > +         configure Efinix Trion and Titanium Series FPGAs over SPI
> > > > > +         using passive serial mode.
> > > > > +         Warning: Do not activate this if there are other SPI devices
> > > > > +         on the same bus as it might interfere with the transmission.
> > > >
> > > > Sorry, this won't work. As you can see, the conflict usage of CS causes
> > > > several concerns. Just a text here is far from enough.
> > > >
> > > > You need to actively work with SPI core/controller drivers to find a
> > > > solution that coordinate the usage of this pin.
> > >
> > > Why does it even impact other SPI devices on the bus? It's not /their/
> > > CS line that is being modified here, it is the line for the FPGA's
> > > programming interface, right?
> > > What am I missing here that makes it any different to any other SPI
> > > device that may need it's CS toggled?
> >
> > IIUC, now spi core or controller driver should fully responsible for
> > HW operations of CS. And every good behaved spi device driver should
> > declare their logical CS index defined by SPI controller and let SPI
> > core/controller driver to proxy the CS change.
> >
> > But if this spi device driver directly aquires CS, it conflicts with
> > the controller and just fails.
>
> Right, I don't think you answered my question here at all, but just
> reading over the kconfig text again I think I understand what it means.
> I'd interpreted this as other devices being impacted by what this driver
> is doing, but actually it is talking about other devices on the bus
> interfering with this one because of how it handles the chip select.

Correct, the problem lies when other devices initiate a transfer in
between the device programming:
If the CS goes inactive in between, the fpga won't be programmed
correctly since it requires that all bytes are transferred within the
same CS active.
If the CS remains active, the fpga will be programmed with random payloads.

But I might have found a solution to coordinate the CS with the
controller (set_cs in struct spi_controller), since the cs state must
be set before any transfer to enter the programming mode.

Regards,
Ian