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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id i127sm15204292pfe.2.2021.11.15.10.28.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Nov 2021 10:28:34 -0800 (PST) Subject: Re: [PATCH] fpga: dfl: pci: generalize find_dfls_by_vsec() To: Xu Yilun Cc: hao.wu@intel.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org References: <20211113221252.4062704-1-trix@redhat.com> <20211115012516.GA288162@yilunxu-OptiPlex-7050> From: Tom Rix Message-ID: Date: Mon, 15 Nov 2021 10:28:32 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20211115012516.GA288162@yilunxu-OptiPlex-7050> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org On 11/14/21 5:25 PM, Xu Yilun wrote: > On Sat, Nov 13, 2021 at 02:12:52PM -0800, trix@redhat.com wrote: >> From: Tom Rix >> >> find_dfls_by_vsec() is a general dfl function. >> Although dfl has multiple vendors, only Intel is supported. >> Move vsec and vendor id to an array variable. >> Other vendors can append the array to enable their support. > As Hao mentioned, DVSEC could be a better solution if DFL should be > present in components by a variety of vendors. This is not finally > determined, but I think we should not add new features for VSEC now. Can you expand what you mean by this ? I am considering the n5010 usecase, the vendor is not intel and will go through this dfl function and always fail. This is broken. Either the function should be generalized or moved to an intel specific call. Tom > > Thanks, > Yilun > >> Signed-off-by: Tom Rix >> --- >> drivers/fpga/dfl-pci.c | 31 ++++++++++++++++++++++++------- >> 1 file changed, 24 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c >> index 4d68719e608f..9dc0815c8274 100644 >> --- a/drivers/fpga/dfl-pci.c >> +++ b/drivers/fpga/dfl-pci.c >> @@ -136,19 +136,36 @@ static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec) >> return table; >> } >> >> -static int find_dfls_by_vsec(struct pci_dev *pcidev, struct dfl_fpga_enum_info *info) >> +struct dfl_vsec { >> + u16 vendor; >> + u16 id; >> +}; >> + >> +static struct dfl_vsec vsecs[] = { >> + { PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_DFLS }, >> +}; >> + >> +static int find_dfls_by_vsec(struct pci_dev *pcidev, >> + struct dfl_fpga_enum_info *info) >> { >> u32 bir, offset, vndr_hdr, dfl_cnt, dfl_res; >> int dfl_res_off, i, bars, voff = 0; >> resource_size_t start, len; >> >> - while ((voff = pci_find_next_ext_capability(pcidev, voff, PCI_EXT_CAP_ID_VNDR))) { >> - vndr_hdr = 0; >> - pci_read_config_dword(pcidev, voff + PCI_VNDR_HEADER, &vndr_hdr); >> + for (i = 0; i < ARRAY_SIZE(vsecs); i++) { >> + if (pcidev->vendor != vsecs[i].vendor) >> + continue; >> + >> + while ((voff = >> + pci_find_next_ext_capability(pcidev, voff, >> + PCI_EXT_CAP_ID_VNDR))) { >> + vndr_hdr = 0; >> + pci_read_config_dword(pcidev, voff + PCI_VNDR_HEADER, >> + &vndr_hdr); >> >> - if (PCI_VNDR_HEADER_ID(vndr_hdr) == PCI_VSEC_ID_INTEL_DFLS && >> - pcidev->vendor == PCI_VENDOR_ID_INTEL) >> - break; >> + if (PCI_VNDR_HEADER_ID(vndr_hdr) == vsecs[i].id) >> + break; >> + } >> } >> >> if (!voff) { >> -- >> 2.26.3