From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_NONE autolearn=no autolearn_force=no version=3.4.0 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by sandeen.net (Postfix) with ESMTP id 50FE47880 for ; Wed, 11 Mar 2020 11:30:27 -0500 (CDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730122AbgCKQbJ (ORCPT ); Wed, 11 Mar 2020 12:31:09 -0400 Received: from foss.arm.com ([217.140.110.172]:51686 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730052AbgCKQbJ (ORCPT ); Wed, 11 Mar 2020 12:31:09 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E968E31B; Wed, 11 Mar 2020 09:31:08 -0700 (PDT) Received: from arrakis.emea.arm.com (arrakis.cambridge.arm.com [10.1.196.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D8A643F6CF; Wed, 11 Mar 2020 09:31:05 -0700 (PDT) Date: Wed, 11 Mar 2020 16:31:03 +0000 From: Catalin Marinas To: Mark Brown Cc: Will Deacon , Alexander Viro , Paul Elliott , Peter Zijlstra , Yu-cheng Yu , Amit Kachhap , Vincenzo Frascino , Marc Zyngier , Eugene Syromiatnikov , Szabolcs Nagy , "H . J . Lu " , Andrew Jones , Kees Cook , Arnd Bergmann , Jann Horn , Richard Henderson , Kristina =?utf-8?Q?Mart=C5=A1enko?= , Thomas Gleixner , Florian Weimer , Sudakshina Das , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-fsdevel@vger.kernel.org, Dave Martin Subject: Re: [PATCH v8 03/11] arm64: Basic Branch Target Identification support Message-ID: <20200311163103.GL3216816@arrakis.emea.arm.com> References: <20200227174417.23722-1-broonie@kernel.org> <20200227174417.23722-4-broonie@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200227174417.23722-4-broonie@kernel.org> Sender: linux-fsdevel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fsdevel@vger.kernel.org On Thu, Feb 27, 2020 at 05:44:09PM +0000, Mark Brown wrote: > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 0b30e884e088..e37f4f07b990 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -1519,6 +1519,28 @@ endmenu > > menu "ARMv8.5 architectural features" > > +config ARM64_BTI > + bool "Branch Target Identification support" > + default y > + help > + Branch Target Identification (part of the ARMv8.5 Extensions) > + provides a mechanism to limit the set of locations to which computed > + branch instructions such as BR or BLR can jump. > + > + To make use of BTI on CPUs that support it, say Y. > + > + BTI is intended to provide complementary protection to other control > + flow integrity protection mechanisms, such as the Pointer > + authentication mechanism provided as part of the ARMv8.3 Extensions. > + For this reason, it does not make sense to enable this option without > + also enabling support for pointer authentication. Thus, when > + enabling this option you should also select ARM64_PTR_AUTH=y. > + > + Userspace binaries must also be specifically compiled to make use of > + this mechanism. If you say N here or the hardware does not support > + BTI, such binaries can still run, but you get no additional > + enforcement of branch destinations. To keep the series bisectable, I'd move the Kconfig into a separate patch towards the end. It looks like the feature is only partially supported after patch 3, so let's not advertise it here. -- Catalin