linux-fsdevel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Joey Gouly <joey.gouly@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: nd@arm.com, akpm@linux-foundation.org, aneesh.kumar@kernel.org,
	aneesh.kumar@linux.ibm.com, anshuman.khandual@arm.com,
	bp@alien8.de, broonie@kernel.org, catalin.marinas@arm.com,
	christophe.leroy@csgroup.eu, dave.hansen@linux.intel.com,
	hpa@zytor.com, joey.gouly@arm.com, linux-fsdevel@vger.kernel.org,
	linux-mm@kvack.org, linuxppc-dev@lists.ozlabs.org,
	maz@kernel.org, mingo@redhat.com, mpe@ellerman.id.au,
	naveen.n.rao@linux.ibm.com, npiggin@gmail.com,
	oliver.upton@linux.dev, shuah@kernel.org,
	skhan@linuxfoundation.org, szabolcs.nagy@arm.com,
	tglx@linutronix.de, will@kernel.org, x86@kernel.org,
	kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org
Subject: [PATCH v5 11/30] arm64: enable the Permission Overlay Extension for EL0
Date: Thu, 22 Aug 2024 16:10:54 +0100	[thread overview]
Message-ID: <20240822151113.1479789-12-joey.gouly@arm.com> (raw)
In-Reply-To: <20240822151113.1479789-1-joey.gouly@arm.com>

Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to
check if the CPU supports the feature.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 Documentation/arch/arm64/elf_hwcaps.rst |  2 ++
 arch/arm64/include/asm/hwcap.h          |  1 +
 arch/arm64/include/uapi/asm/hwcap.h     |  1 +
 arch/arm64/kernel/cpufeature.c          | 14 ++++++++++++++
 arch/arm64/kernel/cpuinfo.c             |  1 +
 5 files changed, 19 insertions(+)

diff --git Documentation/arch/arm64/elf_hwcaps.rst Documentation/arch/arm64/elf_hwcaps.rst
index 448c1664879b..694f67fa07d1 100644
--- Documentation/arch/arm64/elf_hwcaps.rst
+++ Documentation/arch/arm64/elf_hwcaps.rst
@@ -365,6 +365,8 @@ HWCAP2_SME_SF8DP2
 HWCAP2_SME_SF8DP4
     Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1.
 
+HWCAP2_POE
+    Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001.
 
 4. Unused AT_HWCAP bits
 -----------------------
diff --git arch/arm64/include/asm/hwcap.h arch/arm64/include/asm/hwcap.h
index 4edd3b61df11..a775adddecf2 100644
--- arch/arm64/include/asm/hwcap.h
+++ arch/arm64/include/asm/hwcap.h
@@ -157,6 +157,7 @@
 #define KERNEL_HWCAP_SME_SF8FMA		__khwcap2_feature(SME_SF8FMA)
 #define KERNEL_HWCAP_SME_SF8DP4		__khwcap2_feature(SME_SF8DP4)
 #define KERNEL_HWCAP_SME_SF8DP2		__khwcap2_feature(SME_SF8DP2)
+#define KERNEL_HWCAP_POE		__khwcap2_feature(POE)
 
 /*
  * This yields a mask that user programs can use to figure out what
diff --git arch/arm64/include/uapi/asm/hwcap.h arch/arm64/include/uapi/asm/hwcap.h
index 285610e626f5..055381b2c615 100644
--- arch/arm64/include/uapi/asm/hwcap.h
+++ arch/arm64/include/uapi/asm/hwcap.h
@@ -122,5 +122,6 @@
 #define HWCAP2_SME_SF8FMA	(1UL << 60)
 #define HWCAP2_SME_SF8DP4	(1UL << 61)
 #define HWCAP2_SME_SF8DP2	(1UL << 62)
+#define HWCAP2_POE		(1UL << 63)
 
 #endif /* _UAPI__ASM_HWCAP_H */
diff --git arch/arm64/kernel/cpufeature.c arch/arm64/kernel/cpufeature.c
index 2daf5597cd65..718728a85430 100644
--- arch/arm64/kernel/cpufeature.c
+++ arch/arm64/kernel/cpufeature.c
@@ -466,6 +466,8 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {
+	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE),
+		       FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),
 	ARM64_FTR_END,
@@ -2348,6 +2350,14 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused)
 	sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn);
 }
 
+#ifdef CONFIG_ARM64_POE
+static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused)
+{
+	sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE);
+	sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE);
+}
+#endif
+
 /* Internal helper functions to match cpu capability type */
 static bool
 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
@@ -2876,6 +2886,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.capability = ARM64_HAS_S1POE,
 		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
 		.matches = has_cpuid_feature,
+		.cpu_enable = cpu_enable_poe,
 		ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP)
 	},
 #endif
@@ -3043,6 +3054,9 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 	HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2),
 	HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3),
 	HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2),
+#ifdef CONFIG_ARM64_POE
+	HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE),
+#endif
 	{},
 };
 
diff --git arch/arm64/kernel/cpuinfo.c arch/arm64/kernel/cpuinfo.c
index 09eeaa24d456..b9db812082b3 100644
--- arch/arm64/kernel/cpuinfo.c
+++ arch/arm64/kernel/cpuinfo.c
@@ -143,6 +143,7 @@ static const char *const hwcap_str[] = {
 	[KERNEL_HWCAP_SME_SF8FMA]	= "smesf8fma",
 	[KERNEL_HWCAP_SME_SF8DP4]	= "smesf8dp4",
 	[KERNEL_HWCAP_SME_SF8DP2]	= "smesf8dp2",
+	[KERNEL_HWCAP_POE]		= "poe",
 };
 
 #ifdef CONFIG_COMPAT
-- 
2.25.1


  parent reply	other threads:[~2024-08-22 15:12 UTC|newest]

Thread overview: 77+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-22 15:10 [PATCH v5 00/30] Permission Overlay Extension Joey Gouly
2024-08-22 15:10 ` [PATCH v5 01/30] powerpc/mm: add ARCH_PKEY_BITS to Kconfig Joey Gouly
2024-08-22 15:10 ` [PATCH v5 02/30] x86/mm: " Joey Gouly
2024-08-22 15:10 ` [PATCH v5 03/30] mm: use ARCH_PKEY_BITS to define VM_PKEY_BITN Joey Gouly
2024-08-22 15:10 ` [PATCH v5 04/30] arm64: disable trapping of POR_EL0 to EL2 Joey Gouly
2024-08-23 13:42   ` Will Deacon
2024-08-22 15:10 ` [PATCH v5 05/30] arm64: cpufeature: add Permission Overlay Extension cpucap Joey Gouly
2024-08-22 15:10 ` [PATCH v5 06/30] arm64: context switch POR_EL0 register Joey Gouly
2024-08-23 14:45   ` Will Deacon
2024-08-23 16:41     ` Catalin Marinas
2024-08-23 17:08       ` Will Deacon
2024-08-23 18:40         ` Catalin Marinas
2024-08-27 11:38           ` Will Deacon
2024-09-02 19:08             ` Catalin Marinas
2024-09-03 14:54               ` Joey Gouly
2024-09-04 10:22                 ` Will Deacon
2024-09-04 11:32                   ` Joey Gouly
2024-09-04 11:43                     ` Will Deacon
2024-09-04 12:55                       ` Joey Gouly
2024-09-04 16:17                         ` Will Deacon
2024-09-04 17:05                           ` Marc Zyngier
2024-09-05 10:36                           ` Joey Gouly
2024-09-04 11:38                   ` Catalin Marinas
2024-09-11 15:01   ` Kevin Brodsky
2024-09-11 15:33     ` Dave Hansen
2024-09-12 10:50       ` Will Deacon
2024-09-12 12:48         ` Joey Gouly
2024-09-13 15:14           ` Will Deacon
2024-09-22  5:49       ` Aneesh Kumar K.V
2024-08-22 15:10 ` [PATCH v5 07/30] KVM: arm64: Save/restore POE registers Joey Gouly
2024-08-22 15:10 ` [PATCH v5 08/30] KVM: arm64: make kvm_at() take an OP_AT_* Joey Gouly
2024-08-23 13:48   ` Will Deacon
2024-08-23 14:24     ` Marc Zyngier
2024-08-30  8:01     ` Marc Zyngier
2024-08-30  9:05       ` Will Deacon
2024-08-30 11:58         ` Marc Zyngier
2024-08-30  9:25   ` Will Deacon
2024-08-30 11:23     ` Marc Zyngier
2024-08-30 11:35       ` Joey Gouly
2024-08-22 15:10 ` [PATCH v5 09/30] KVM: arm64: use `at s1e1a` for POE Joey Gouly
2024-08-22 15:10 ` [PATCH v5 10/30] KVM: arm64: Sanitise ID_AA64MMFR3_EL1 Joey Gouly
2024-08-22 15:10 ` Joey Gouly [this message]
2024-08-22 15:10 ` [PATCH v5 12/30] arm64: re-order MTE VM_ flags Joey Gouly
2024-08-22 15:10 ` [PATCH v5 13/30] arm64: add POIndex defines Joey Gouly
2024-08-22 15:10 ` [PATCH v5 14/30] arm64: convert protection key into vm_flags and pgprot values Joey Gouly
2024-08-22 15:10 ` [PATCH v5 15/30] arm64: mask out POIndex when modifying a PTE Joey Gouly
2024-08-22 15:10 ` [PATCH v5 16/30] arm64: handle PKEY/POE faults Joey Gouly
2024-08-29 17:55   ` Mark Brown
2024-09-03 14:50     ` Joey Gouly
2024-09-03 15:29       ` Joey Gouly
2024-08-22 15:11 ` [PATCH v5 17/30] arm64: add pte_access_permitted_no_overlay() Joey Gouly
2024-08-22 15:11 ` [PATCH v5 18/30] arm64: implement PKEYS support Joey Gouly
2024-08-22 15:11 ` [PATCH v5 19/30] arm64: add POE signal support Joey Gouly
2024-09-24 11:27   ` Kevin Brodsky
2024-09-24 15:04     ` Dave Martin
2024-10-09 14:43     ` Will Deacon
2024-10-14 17:10       ` Will Deacon
2024-10-15  9:59         ` Joey Gouly
2024-10-15 11:37           ` Mark Brown
2024-10-15 11:41           ` Will Deacon
2024-10-15 12:25             ` Joey Gouly
2024-10-15 13:26               ` Mark Brown
2024-10-17  7:44               ` Kevin Brodsky
2024-10-15 13:39             ` Dave Martin
2024-10-15 15:01             ` Catalin Marinas
2024-10-17 14:00               ` Kevin Brodsky
2024-08-22 15:11 ` [PATCH v5 20/30] arm64/ptrace: add support for FEAT_POE Joey Gouly
2024-08-22 15:11 ` [PATCH v5 21/30] arm64: enable POE and PIE to coexist Joey Gouly
2024-08-22 15:11 ` [PATCH v5 22/30] arm64: enable PKEY support for CPUs with S1POE Joey Gouly
2024-08-22 15:11 ` [PATCH v5 23/30] arm64: add Permission Overlay Extension Kconfig Joey Gouly
2024-08-22 15:11 ` [PATCH v5 24/30] kselftest/arm64: move get_header() Joey Gouly
2024-08-22 15:11 ` [PATCH v5 25/30] selftests: mm: move fpregs printing Joey Gouly
2024-08-22 15:11 ` [PATCH v5 26/30] selftests: mm: make protection_keys test work on arm64 Joey Gouly
2024-08-22 15:11 ` [PATCH v5 27/30] kselftest/arm64: add HWCAP test for FEAT_S1POE Joey Gouly
2024-08-22 15:11 ` [PATCH v5 28/30] kselftest/arm64: parse POE_MAGIC in a signal frame Joey Gouly
2024-08-22 15:11 ` [PATCH v5 29/30] kselftest/arm64: Add test case for POR_EL0 signal frame records Joey Gouly
2024-08-22 15:11 ` [PATCH v5 30/30] KVM: selftests: get-reg-list: add Permission Overlay registers Joey Gouly

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240822151113.1479789-12-joey.gouly@arm.com \
    --to=joey.gouly@arm.com \
    --cc=akpm@linux-foundation.org \
    --cc=aneesh.kumar@kernel.org \
    --cc=aneesh.kumar@linux.ibm.com \
    --cc=anshuman.khandual@arm.com \
    --cc=bp@alien8.de \
    --cc=broonie@kernel.org \
    --cc=catalin.marinas@arm.com \
    --cc=christophe.leroy@csgroup.eu \
    --cc=dave.hansen@linux.intel.com \
    --cc=hpa@zytor.com \
    --cc=kvmarm@lists.linux.dev \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-fsdevel@vger.kernel.org \
    --cc=linux-kselftest@vger.kernel.org \
    --cc=linux-mm@kvack.org \
    --cc=linuxppc-dev@lists.ozlabs.org \
    --cc=maz@kernel.org \
    --cc=mingo@redhat.com \
    --cc=mpe@ellerman.id.au \
    --cc=naveen.n.rao@linux.ibm.com \
    --cc=nd@arm.com \
    --cc=npiggin@gmail.com \
    --cc=oliver.upton@linux.dev \
    --cc=shuah@kernel.org \
    --cc=skhan@linuxfoundation.org \
    --cc=szabolcs.nagy@arm.com \
    --cc=tglx@linutronix.de \
    --cc=will@kernel.org \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).