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[92.21.58.28]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454b168664bsm61780085e9.20.2025.07.05.11.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Jul 2025 11:33:33 -0700 (PDT) Date: Sat, 5 Jul 2025 19:33:32 +0100 From: David Laight To: Segher Boessenkool Cc: Christophe Leroy , Michael Ellerman , Nicholas Piggin , Naveen N Rao , Madhavan Srinivasan , Alexander Viro , Christian Brauner , Jan Kara , Thomas Gleixner , Ingo Molnar , Peter Zijlstra , Darren Hart , Davidlohr Bueso , Andre Almeida , Andrew Morton , Dave Hansen , Linus Torvalds , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org Subject: Re: [PATCH 0/5] powerpc: Implement masked user access Message-ID: <20250705193332.251e0b1f@pumpkin> In-Reply-To: <20250626220148.GR17294@gate.crashing.org> References: <20250622172043.3fb0e54c@pumpkin> <20250624131714.GG17294@gate.crashing.org> <20250624175001.148a768f@pumpkin> <20250624182505.GH17294@gate.crashing.org> <20250624220816.078f960d@pumpkin> <83fb5685-a206-477c-bff3-03e0ebf4c40c@csgroup.eu> <20250626220148.GR17294@gate.crashing.org> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-fsdevel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 26 Jun 2025 17:01:48 -0500 Segher Boessenkool wrote: > On Thu, Jun 26, 2025 at 07:56:10AM +0200, Christophe Leroy wrote: ... > I have no idea why you think power9 has it while older CPUS do not. In > the GCC source code we have this comment: > /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but > altivec is a win so enable it. */ > and in fact we do not enable it for ISA 2.06 (p8) either, probably for > a similar reason. Odd, I'd have thought that replacing a conditional branch with a conditional move would pretty much always be a win. Unless, of course, you only consider benchmark loops where the branch predictor in 100% accurate. OTOH isn't altivec 'simd' instructions? They pretty much only help for loops with lots of iterations. I don't know about ppc, but I've seen gcc make a real 'pigs breakfast' of loop vectorisation on x86. For the linux kernel (which as Linus keeps reminding people) tends to run 'cold cache', you probably want conditional moves in order to avoid mis-predicted branches and non-linear execution, but don't want loop vectorisation because the setup and end cases cost too much compared to the gain for each iteration. David