From: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
To: linux-riscv@lists.infradead.org, linux-fsdevel@vger.kernel.org,
linux-mm@kvack.org, linux-kernel@vger.kernel.org
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Conor Dooley <conor@kernel.org>,
Deepak Gupta <debug@rivosinc.com>,
Ved Shanbhogue <ved@rivosinc.com>,
Alexander Viro <viro@zeniv.linux.org.uk>,
Christian Brauner <brauner@kernel.org>, Jan Kara <jack@suse.cz>,
Andrew Morton <akpm@linux-foundation.org>,
Peter Xu <peterx@redhat.com>, Arnd Bergmann <arnd@arndb.de>,
David Hildenbrand <david@redhat.com>,
Lorenzo Stoakes <lorenzo.stoakes@oracle.com>,
"Liam R . Howlett" <Liam.Howlett@oracle.com>,
Vlastimil Babka <vbabka@suse.cz>, Mike Rapoport <rppt@kernel.org>,
Suren Baghdasaryan <surenb@google.com>,
Michal Hocko <mhocko@suse.com>,
Axel Rasmussen <axelrasmussen@google.com>,
Yuanchu Xie <yuanchu@google.com>,
Chunyan Zhang <zhang.lyra@gmail.com>
Subject: [PATCH V13 6/6] dt-bindings: riscv: Add Svrsw60t59b extension description
Date: Wed, 17 Sep 2025 11:37:03 +0800 [thread overview]
Message-ID: <20250917033703.1695933-7-zhangchunyan@iscas.ac.cn> (raw)
In-Reply-To: <20250917033703.1695933-1-zhangchunyan@iscas.ac.cn>
Add description for the Svrsw60t59b extension (PTE Reserved for SW
bits 60:59) extension which was ratified recently in
riscv-non-isa/riscv-iommu.
Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index ede6a58ccf53..7e1a59c7d911 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -217,6 +217,12 @@ properties:
memory types as ratified in the 20191213 version of the privileged
ISA specification.
+ - const: svrsw60t59b
+ description:
+ The svrsw60t59b for providing two more bits[60:59] to PTE/PMD entry
+ as ratified at commit 28bde925e7a7 ("PTE Reserved for SW bits 60:59")
+ of riscv-non-isa/riscv-iommu.
+
- const: svvptc
description:
The standard Svvptc supervisor-level extension for
--
2.34.1
next prev parent reply other threads:[~2025-09-17 3:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-17 3:36 [PATCH V13 0/6] riscv: mm: Add soft-dirty and uffd-wp support Chunyan Zhang
2025-09-17 3:36 ` [PATCH V13 1/6] mm: softdirty: Add pgtable_supports_soft_dirty() Chunyan Zhang
2025-09-17 3:36 ` [PATCH V13 2/6] mm: userfaultfd: Add pgtable_supports_uffd_wp() Chunyan Zhang
2025-09-17 7:25 ` David Hildenbrand
2025-09-17 9:20 ` Chunyan Zhang
2025-09-17 3:37 ` [PATCH V13 3/6] riscv: Add RISC-V Svrsw60t59b extension support Chunyan Zhang
2025-09-17 3:37 ` [PATCH V13 4/6] riscv: mm: Add soft-dirty page tracking support Chunyan Zhang
2025-09-17 3:37 ` [PATCH V13 5/6] riscv: mm: Add userfaultfd write-protect support Chunyan Zhang
2025-09-17 3:37 ` Chunyan Zhang [this message]
2025-09-18 0:10 ` [PATCH V13 6/6] dt-bindings: riscv: Add Svrsw60t59b extension description Krzysztof Kozlowski
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