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[66.111.4.228]) by smtp.gmail.com with ESMTPSA id ay18-20020a05620a179200b006a8b6848556sm8886496qkb.7.2022.08.01.11.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Aug 2022 11:18:28 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailauth.nyi.internal (Postfix) with ESMTP id A8D3F27C0077; Mon, 1 Aug 2022 14:18:27 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Mon, 01 Aug 2022 14:18:27 -0400 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvddvfedguddvfecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpeffhffvvefukfhfgggtuggjsehttdertddttddvnecuhfhrohhmpeeuohhq uhhnucfhvghnghcuoegsohhquhhnrdhfvghnghesghhmrghilhdrtghomheqnecuggftrf grthhtvghrnhephedugfduffffteeutddvheeuveelvdfhleelieevtdeguefhgeeuveei udffiedvnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomh epsghoqhhunhdomhgvshhmthhprghuthhhphgvrhhsohhnrghlihhthidqieelvdeghedt ieegqddujeejkeehheehvddqsghoqhhunhdrfhgvnhhgpeepghhmrghilhdrtghomhesfh higihmvgdrnhgrmhgv X-ME-Proxy: Feedback-ID: iad51458e:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 1 Aug 2022 14:18:26 -0400 (EDT) Date: Mon, 1 Aug 2022 11:17:28 -0700 From: Boqun Feng To: Mikulas Patocka Cc: Will Deacon , Linus Torvalds , "Paul E. McKenney" , Ard Biesheuvel , Alexander Viro , Alan Stern , Andrea Parri , Peter Zijlstra , Nicholas Piggin , David Howells , Jade Alglave , Luc Maranget , Akira Yokosawa , Daniel Lustig , Joel Fernandes , Linux Kernel Mailing List , linux-arch , linux-fsdevel@vger.kernel.org Subject: Re: [PATCH v4 1/2] introduce test_bit_acquire and use it in wait_on_bit Message-ID: References: <20220801155421.GB26280@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-fsdevel@vger.kernel.org On Mon, Aug 01, 2022 at 12:12:47PM -0400, Mikulas Patocka wrote: > > > On Mon, 1 Aug 2022, Will Deacon wrote: > > > On Mon, Aug 01, 2022 at 06:42:15AM -0400, Mikulas Patocka wrote: > > > > > Index: linux-2.6/arch/x86/include/asm/bitops.h > > > =================================================================== > > > --- linux-2.6.orig/arch/x86/include/asm/bitops.h 2022-08-01 12:27:43.000000000 +0200 > > > +++ linux-2.6/arch/x86/include/asm/bitops.h 2022-08-01 12:27:43.000000000 +0200 > > > @@ -203,8 +203,10 @@ arch_test_and_change_bit(long nr, volati > > > > > > static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr) > > > { > > > - return ((1UL << (nr & (BITS_PER_LONG-1))) & > > > + bool r = ((1UL << (nr & (BITS_PER_LONG-1))) & > > > (addr[nr >> _BITOPS_LONG_SHIFT])) != 0; > > > + barrier(); > > > + return r; > > > > Hmm, I find it a bit weird to have a barrier() here given that 'addr' is > > volatile and we don't need a barrier() like this in the definition of > > READ_ONCE(), for example. > > gcc doesn't reorder two volatile accesses, but it can reorder non-volatile > accesses around volatile accesses. > > The purpose of the compiler barrier is to make sure that the non-volatile > accesses that follow test_bit are not reordered by the compiler before the > volatile access to addr. > Better to have a constant_test_bit_acquire()? I don't think all test_bit() call sites need the ordering? Regards, Boqun > > > Index: linux-2.6/include/linux/wait_bit.h > > > =================================================================== > > > --- linux-2.6.orig/include/linux/wait_bit.h 2022-08-01 12:27:43.000000000 +0200 > > > +++ linux-2.6/include/linux/wait_bit.h 2022-08-01 12:27:43.000000000 +0200 > > > @@ -71,7 +71,7 @@ static inline int > > > wait_on_bit(unsigned long *word, int bit, unsigned mode) > > > { > > > might_sleep(); > > > - if (!test_bit(bit, word)) > > > + if (!test_bit_acquire(bit, word)) > > > return 0; > > > return out_of_line_wait_on_bit(word, bit, > > > bit_wait, > > > > Yet another approach here would be to leave test_bit as-is and add a call to > > smp_acquire__after_ctrl_dep() since that exists already -- I don't have > > strong opinions about it, but it saves you having to add another stub to > > x86. > > It would be the same as my previous patch with smp_rmb() that Linus didn't > like. But I think smp_rmb (or smp_acquire__after_ctrl_dep) would be > correct here. > > > Will > > Mikulas >