From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C3319198A3E for ; Tue, 16 Jul 2024 10:42:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721126530; cv=none; b=NUiqUgSlZwM85DQ16t0tcf8+QwIVtoEwebbSlYiQhtbVbhOTDBWBuDuFZOGYZhwFsF2uEBPMQzeyniXpqrH+UfehpfbVzu3UQVbSlaFKMnaJWUq0rkzoFsKXterxfF8UjYoeM7ZRIv+8VJbVyWZY6zyMfcQ9k8UrvIuDYZelYAM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721126530; c=relaxed/simple; bh=h0Az1/JAIMkfMYS5Dfd4ULPX/G/mcs7foDYK/doGzow=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=aLtZRCTvhMfzqudjjsAT418/DdSYfg7iI4fsTVwm9WhU9XPBg9YmLWEh+U4ES3zmNgRRwEz4MC6s32Ne9bFW54mBnLICXI8eCWqXxeXQtgMs/BpXaY9cqv55CldWJ11zZAJQ3Wx7EUf+vgS044hQYgcQ3ac/qBEmCGJdIn3u/v4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 644EA1063; Tue, 16 Jul 2024 03:42:33 -0700 (PDT) Received: from [10.163.52.225] (unknown [10.163.52.225]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A5F513F762; Tue, 16 Jul 2024 03:41:58 -0700 (PDT) Message-ID: Date: Tue, 16 Jul 2024 16:11:54 +0530 Precedence: bulk X-Mailing-List: linux-fsdevel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 20/29] arm64: enable POE and PIE to coexist To: Joey Gouly , linux-arm-kernel@lists.infradead.org Cc: akpm@linux-foundation.org, aneesh.kumar@kernel.org, aneesh.kumar@linux.ibm.com, bp@alien8.de, broonie@kernel.org, catalin.marinas@arm.com, christophe.leroy@csgroup.eu, dave.hansen@linux.intel.com, hpa@zytor.com, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linuxppc-dev@lists.ozlabs.org, maz@kernel.org, mingo@redhat.com, mpe@ellerman.id.au, naveen.n.rao@linux.ibm.com, npiggin@gmail.com, oliver.upton@linux.dev, shuah@kernel.org, szabolcs.nagy@arm.com, tglx@linutronix.de, will@kernel.org, x86@kernel.org, kvmarm@lists.linux.dev References: <20240503130147.1154804-1-joey.gouly@arm.com> <20240503130147.1154804-21-joey.gouly@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20240503130147.1154804-21-joey.gouly@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/3/24 18:31, Joey Gouly wrote: > Set the EL0/userspace indirection encodings to be the overlay enabled > variants of the permissions. Could you please explain the rationale for this ? Should POE variants for pte permissions be used (when available) instead of permission indirection ones. > > Signed-off-by: Joey Gouly > Cc: Catalin Marinas > Cc: Will Deacon > --- > arch/arm64/include/asm/pgtable-prot.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h > index dd9ee67d1d87..4f9f85437d3d 100644 > --- a/arch/arm64/include/asm/pgtable-prot.h > +++ b/arch/arm64/include/asm/pgtable-prot.h > @@ -147,10 +147,10 @@ static inline bool __pure lpa2_is_enabled(void) > > #define PIE_E0 ( \ > PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY), PIE_X_O) | \ > - PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX) | \ > - PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RWX) | \ > - PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY), PIE_R) | \ > - PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED), PIE_RW)) > + PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX_O) | \ > + PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RWX_O) | \ > + PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY), PIE_R_O) | \ > + PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED), PIE_RW_O)) > > #define PIE_E1 ( \ > PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY), PIE_NONE_O) | \