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[24.148.33.89]) by smtp.gmail.com with ESMTPSA id t38sm4905845qta.78.2019.12.01.13.58.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 01 Dec 2019 13:58:27 -0800 (PST) Subject: Re: DAX filesystem support on ARMv8 To: Bharat Kumar Gogada , Matthew Wilcox , Dan Williams Cc: "linux-nvdimm@lists.01.org" , "linux-fsdevel@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "viro@zeniv.linux.org.uk" , "jack@suse.cz" References: <20191112220212.GC7934@bombadil.infradead.org> From: Jon Masters Organization: World Organi{s,z}ation of Broken Dreams Message-ID: Date: Sun, 1 Dec 2019 13:54:45 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-fsdevel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fsdevel@vger.kernel.org On 11/14/19 1:54 AM, Bharat Kumar Gogada wrote: >> >> On Tue, Nov 12, 2019 at 09:15:18AM -0800, Dan Williams wrote: >>> On Mon, Nov 11, 2019 at 6:12 PM Bharat Kumar Gogada >> wrote: >>>> >>>> Hi All, >>>> >>>> As per Documentation/filesystems/dax.txt >>>> >>>> The DAX code does not work correctly on architectures which have >>>> virtually mapped caches such as ARM, MIPS and SPARC. >>>> >>>> Can anyone please shed light on dax filesystem issue w.r.t ARM architecture >> ? >>> >>> The concern is VIVT caches since the kernel will want to flush pmem >>> addresses with different virtual addresses than what userspace is >>> using. As far as I know, ARMv8 has VIPT caches, so should not have an >>> issue. Willy initially wrote those restrictions, but I am assuming >>> that the concern was managing the caches in the presence of virtual >>> aliases. >> >> The kernel will also access data at different virtual addresses from userspace. >> So VIVT CPUs will be mmap/read/write incoherent, as well as being flush >> incoherent. > > Thanks a lot Wilcox and Dan for clarification. > So the above restriction only applies to ARM architectures with VIVT caches and not > for VIPT caches. VMSAv8-64 (Armv8) requires that data caches behave as if they were PIPT. Meaning there is not a situation as described above. Jon. -- Computer Architect