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From: "Jiawen Wu" <jiawenwu@trustnetic.com>
To: <andy.shevchenko@gmail.com>
Cc: <netdev@vger.kernel.org>, <jarkko.nikula@linux.intel.com>,
	<andriy.shevchenko@linux.intel.com>,
	<mika.westerberg@linux.intel.com>, <jsd@semihalf.com>,
	<Jose.Abreu@synopsys.com>, <andrew@lunn.ch>,
	<hkallweit1@gmail.com>, <linux@armlinux.org.uk>,
	<linux-i2c@vger.kernel.org>, <linux-gpio@vger.kernel.org>,
	<mengyuanlou@net-swift.com>
Subject: RE: [PATCH net-next v7 6/9] net: txgbe: Support GPIO to SFP socket
Date: Fri, 12 May 2023 16:57:32 +0800	[thread overview]
Message-ID: <000001d984af$c9bc89e0$5d359da0$@trustnetic.com> (raw)
In-Reply-To: <ZF1T62BnVFgR33w0@surfacebook>

> > +static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset,
> > +				    int val)
> > +{
> > +	struct wx *wx = gpiochip_get_data(chip);
> > +	u32 mask;
> > +
> > +	mask = BIT(offset) | BIT(offset - 1);
> > +	if (val)
> > +		wr32m(wx, WX_GPIO_DR, mask, mask);
> > +	else
> > +		wr32m(wx, WX_GPIO_DR, mask, 0);
> > +
> > +	wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset));
> 
> Can you explain, what prevents to have this flow to be interleaved by other API
> calls, like ->direction_in()? Didn't you missed proper locking schema?

It's true, I should add spinlock for writing GPIO registers.

> 
> > +	return 0;
> > +}
> 
> ...
> 
> > +	switch (type) {
> > +	case IRQ_TYPE_EDGE_BOTH:
> > +		level |= BIT(hwirq);
> > +		break;
> > +	case IRQ_TYPE_EDGE_RISING:
> > +		level |= BIT(hwirq);
> > +		polarity |= BIT(hwirq);
> > +		break;
> > +	case IRQ_TYPE_EDGE_FALLING:
> > +		level |= BIT(hwirq);
> 
> > +		polarity &= ~BIT(hwirq);
> 
> This...
> 
> > +		break;
> > +	case IRQ_TYPE_LEVEL_HIGH:
> > +		level &= ~BIT(hwirq);
> 
> ...and this can be done outside of the switch-case. Then you simply set certain
> bits where it's needed.
> 
> > +		polarity |= BIT(hwirq);
> > +		break;
> > +	case IRQ_TYPE_LEVEL_LOW:
> > +		level &= ~BIT(hwirq);
> > +		polarity &= ~BIT(hwirq);
> > +		break;
> 
> default?

Do you mean that treat IRQ_TYPE_LEVEL_LOW as default case, clear level and
polarity firstly, then set the bits in other needed case? 



  reply	other threads:[~2023-05-12  8:58 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-09  2:27 [PATCH net-next v7 0/9] TXGBE PHYLINK support Jiawen Wu
2023-05-09  2:27 ` [PATCH net-next v7 1/9] net: txgbe: Add software nodes to support phylink Jiawen Wu
2023-05-09 12:38   ` Piotr Raczynski
2023-05-09  2:27 ` [PATCH net-next v7 2/9] i2c: designware: Add driver support for Wangxun 10Gb NIC Jiawen Wu
2023-05-09 13:52   ` Piotr Raczynski
2023-05-10  6:43     ` Jiawen Wu
2023-05-10  7:47       ` andy.shevchenko
2023-05-10  8:00         ` Jiawen Wu
2023-05-09  2:27 ` [PATCH net-next v7 3/9] net: txgbe: Register fixed rate clock Jiawen Wu
2023-05-09 15:32   ` Simon Horman
2023-05-10  6:47     ` Jiawen Wu
2023-05-09  2:27 ` [PATCH net-next v7 4/9] net: txgbe: Register I2C platform device Jiawen Wu
2023-05-11 12:13   ` Andrew Lunn
2023-05-11 20:16   ` Piotr Raczynski
2023-05-09  2:27 ` [PATCH net-next v7 5/9] net: txgbe: Add SFP module identify Jiawen Wu
2023-05-11 12:13   ` Andrew Lunn
2023-05-11 20:18   ` Piotr Raczynski
2023-05-09  2:27 ` [PATCH net-next v7 6/9] net: txgbe: Support GPIO to SFP socket Jiawen Wu
2023-05-11 12:31   ` Andrew Lunn
2023-05-12  6:38     ` Jiawen Wu
2023-05-12 14:20       ` Andrew Lunn
2023-05-11 12:38   ` Andrew Lunn
2023-05-12  6:35     ` Jiawen Wu
2023-05-11 20:45   ` andy.shevchenko
2023-05-12  8:57     ` Jiawen Wu [this message]
2023-05-12  9:43       ` Andy Shevchenko
2023-05-12  9:32   ` Russell King (Oracle)
2023-05-12 10:46     ` Jiawen Wu
2023-05-09  2:27 ` [PATCH net-next v7 7/9] net: pcs: Add 10GBASE-R mode for Synopsys Designware XPCS Jiawen Wu
2023-05-11 12:40   ` Andrew Lunn
2023-05-09  2:27 ` [PATCH net-next v7 8/9] net: txgbe: Implement phylink pcs Jiawen Wu
2023-05-11 19:33   ` Andrew Lunn
2023-05-11 20:32   ` Piotr Raczynski
2023-05-12  9:22     ` Jiawen Wu
2023-05-09  2:27 ` [PATCH net-next v7 9/9] net: txgbe: Support phylink MAC layer Jiawen Wu

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